Index: llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h =================================================================== --- llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -111,15 +111,18 @@ /// argument should go, exactly what happens can vary slightly. This /// class abstracts the differences. struct ValueHandler { - ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, - CCAssignFn *AssignFn) - : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {} + ValueHandler(bool IsIncoming, MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI, CCAssignFn *AssignFn) + : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn), + IsIncomingArgumentHandler(IsIncoming) {} virtual ~ValueHandler() = default; /// Returns true if the handler is dealing with incoming arguments, /// i.e. those that move values from some physical location to vregs. - virtual bool isIncomingArgumentHandler() const = 0; + bool isIncomingArgumentHandler() const { + return IsIncomingArgumentHandler; + } /// Materialize a VReg containing the address of the specified /// stack-based object. This is either based on a FrameIndex or @@ -177,9 +180,22 @@ CCAssignFn *AssignFn; private: + bool IsIncomingArgumentHandler; virtual void anchor(); }; + struct IncomingValueHandler : public ValueHandler { + IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, + CCAssignFn *AssignFn) + : ValueHandler(true, MIRBuilder, MRI, AssignFn) {} + }; + + struct OutgoingValueHandler : public ValueHandler { + OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, + CCAssignFn *AssignFn) + : ValueHandler(false, MIRBuilder, MRI, AssignFn) {} + }; + protected: /// Getter for generic TargetLowering class. const TargetLowering *getTLI() const { Index: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -52,10 +52,10 @@ : CallLowering(&TLI) {} namespace { -struct IncomingArgHandler : public CallLowering::ValueHandler { +struct IncomingArgHandler : public CallLowering::IncomingValueHandler { IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, CCAssignFn *AssignFn) - : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {} + : IncomingValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {} Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { @@ -98,8 +98,6 @@ /// (it's an implicit-def of the BL). virtual void markPhysRegUsed(unsigned PhysReg) = 0; - bool isIncomingArgumentHandler() const override { return true; } - uint64_t StackUsed; }; @@ -126,17 +124,15 @@ MachineInstrBuilder MIB; }; -struct OutgoingArgHandler : public CallLowering::ValueHandler { +struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler { OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB, CCAssignFn *AssignFn, CCAssignFn *AssignFnVarArg, bool IsTailCall = false, int FPDiff = 0) - : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), + : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), AssignFnVarArg(AssignFnVarArg), IsTailCall(IsTailCall), FPDiff(FPDiff), StackSize(0), SPReg(0) {} - bool isIncomingArgumentHandler() const override { return false; } - Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { MachineFunction &MF = MIRBuilder.getMF(); Index: llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -35,9 +35,9 @@ namespace { struct AMDGPUValueHandler : public CallLowering::ValueHandler { - AMDGPUValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, - CCAssignFn *AssignFn) - : ValueHandler(B, MRI, AssignFn) {} + AMDGPUValueHandler(bool IsIncoming, MachineIRBuilder &B, + MachineRegisterInfo &MRI, CCAssignFn *AssignFn) + : ValueHandler(IsIncoming, B, MRI, AssignFn) {} /// Wrapper around extendRegister to ensure we extend to a full 32-bit /// register. @@ -52,15 +52,13 @@ } }; -struct OutgoingValueHandler : public AMDGPUValueHandler { - OutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, - MachineInstrBuilder MIB, CCAssignFn *AssignFn) - : AMDGPUValueHandler(B, MRI, AssignFn), MIB(MIB) {} +struct AMDGPUOutgoingValueHandler : public AMDGPUValueHandler { + AMDGPUOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, + MachineInstrBuilder MIB, CCAssignFn *AssignFn) + : AMDGPUValueHandler(false, B, MRI, AssignFn), MIB(MIB) {} MachineInstrBuilder MIB; - bool isIncomingArgumentHandler() const override { return false; } - Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { llvm_unreachable("not implemented"); @@ -100,12 +98,12 @@ } }; -struct IncomingArgHandler : public AMDGPUValueHandler { +struct AMDGPUIncomingArgHandler : public AMDGPUValueHandler { uint64_t StackUsed = 0; - IncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, - CCAssignFn *AssignFn) - : AMDGPUValueHandler(B, MRI, AssignFn) {} + AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, + CCAssignFn *AssignFn) + : AMDGPUValueHandler(true, B, MRI, AssignFn) {} Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { @@ -159,25 +157,22 @@ /// parameters (it's a basic-block live-in), and a call instruction /// (it's an implicit-def of the BL). virtual void markPhysRegUsed(unsigned PhysReg) = 0; - - // FIXME: What is the point of this being a callback? - bool isIncomingArgumentHandler() const override { return true; } }; -struct FormalArgHandler : public IncomingArgHandler { +struct FormalArgHandler : public AMDGPUIncomingArgHandler { FormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, CCAssignFn *AssignFn) - : IncomingArgHandler(B, MRI, AssignFn) {} + : AMDGPUIncomingArgHandler(B, MRI, AssignFn) {} void markPhysRegUsed(unsigned PhysReg) override { MIRBuilder.getMBB().addLiveIn(PhysReg); } }; -struct CallReturnHandler : public IncomingArgHandler { +struct CallReturnHandler : public AMDGPUIncomingArgHandler { CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB, CCAssignFn *AssignFn) - : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} + : AMDGPUIncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} void markPhysRegUsed(unsigned PhysReg) override { MIB.addDef(PhysReg, RegState::Implicit); @@ -186,7 +181,7 @@ MachineInstrBuilder MIB; }; -struct OutgoingArgHandler : public AMDGPUValueHandler { +struct AMDGPUOutgoingArgHandler : public AMDGPUValueHandler { MachineInstrBuilder MIB; CCAssignFn *AssignFnVarArg; @@ -199,15 +194,13 @@ bool IsTailCall; - OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, - MachineInstrBuilder MIB, CCAssignFn *AssignFn, - CCAssignFn *AssignFnVarArg, bool IsTailCall = false, - int FPDiff = 0) - : AMDGPUValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), - AssignFnVarArg(AssignFnVarArg), - FPDiff(FPDiff), IsTailCall(IsTailCall) {} - - bool isIncomingArgumentHandler() const override { return false; } + AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI, MachineInstrBuilder MIB, + CCAssignFn *AssignFn, CCAssignFn *AssignFnVarArg, + bool IsTailCall = false, int FPDiff = 0) + : AMDGPUValueHandler(false, MIRBuilder, MRI, AssignFn), MIB(MIB), + AssignFnVarArg(AssignFnVarArg), FPDiff(FPDiff), IsTailCall(IsTailCall) { + } Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { @@ -439,7 +432,7 @@ }); CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg()); - OutgoingValueHandler RetHandler(B, *MRI, Ret, AssignFn); + AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret, AssignFn); return handleAssignments(B, SplitRetInfos, RetHandler); } @@ -1188,8 +1181,8 @@ // Do the actual argument marshalling. SmallVector PhysRegs; - OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed, - AssignFnVarArg, false); + AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed, + AssignFnVarArg, false); if (!handleAssignments(CCInfo, ArgLocs, MIRBuilder, OutArgs, Handler)) return false; Index: llvm/lib/Target/ARM/ARMCallLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMCallLowering.cpp +++ llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -85,12 +85,11 @@ /// Helper class for values going out through an ABI boundary (used for handling /// function return values and call parameters). -struct OutgoingValueHandler : public CallLowering::ValueHandler { - OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, - MachineInstrBuilder &MIB, CCAssignFn *AssignFn) - : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} - - bool isIncomingArgumentHandler() const override { return false; } +struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler { + ARMOutgoingValueHandler(MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI, MachineInstrBuilder &MIB, + CCAssignFn *AssignFn) + : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { @@ -258,7 +257,8 @@ CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg()); - OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn); + ARMOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, + AssignFn); return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler); } @@ -282,12 +282,10 @@ /// Helper class for values coming in through an ABI boundary (used for handling /// formal arguments and call return values). -struct IncomingValueHandler : public CallLowering::ValueHandler { - IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, - CCAssignFn AssignFn) - : ValueHandler(MIRBuilder, MRI, AssignFn) {} - - bool isIncomingArgumentHandler() const override { return true; } +struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler { + ARMIncomingValueHandler(MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI, CCAssignFn AssignFn) + : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {} Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { @@ -399,10 +397,10 @@ virtual void markPhysRegUsed(unsigned PhysReg) = 0; }; -struct FormalArgHandler : public IncomingValueHandler { +struct FormalArgHandler : public ARMIncomingValueHandler { FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, CCAssignFn AssignFn) - : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {} + : ARMIncomingValueHandler(MIRBuilder, MRI, AssignFn) {} void markPhysRegUsed(unsigned PhysReg) override { MIRBuilder.getMRI()->addLiveIn(PhysReg); @@ -469,10 +467,10 @@ namespace { -struct CallReturnHandler : public IncomingValueHandler { +struct CallReturnHandler : public ARMIncomingValueHandler { CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB, CCAssignFn *AssignFn) - : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} + : ARMIncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} void markPhysRegUsed(unsigned PhysReg) override { MIB.addDef(PhysReg, RegState::Implicit); @@ -554,7 +552,7 @@ } auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, IsVarArg); - OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn); + ARMOutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn); if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler)) return false; Index: llvm/lib/Target/Mips/MipsCallLowering.cpp =================================================================== --- llvm/lib/Target/Mips/MipsCallLowering.cpp +++ llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -87,9 +87,10 @@ } namespace { -class IncomingValueHandler : public MipsCallLowering::MipsHandler { +class MipsIncomingValueHandler : public MipsCallLowering::MipsHandler { public: - IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) + MipsIncomingValueHandler(MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI) : MipsHandler(MIRBuilder, MRI) {} private: @@ -117,11 +118,11 @@ } }; -class CallReturnHandler : public IncomingValueHandler { +class CallReturnHandler : public MipsIncomingValueHandler { public: CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) - : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} + : MipsIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} private: void markPhysRegUsed(unsigned PhysReg) override { @@ -133,9 +134,9 @@ } // end anonymous namespace -void IncomingValueHandler::assignValueToReg(Register ValVReg, - const CCValAssign &VA, - const EVT &VT) { +void MipsIncomingValueHandler::assignValueToReg(Register ValVReg, + const CCValAssign &VA, + const EVT &VT) { Register PhysReg = VA.getLocReg(); if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { const MipsSubtarget &STI = @@ -167,8 +168,8 @@ } } -Register IncomingValueHandler::getStackAddress(const CCValAssign &VA, - MachineMemOperand *&MMO) { +Register MipsIncomingValueHandler::getStackAddress(const CCValAssign &VA, + MachineMemOperand *&MMO) { MachineFunction &MF = MIRBuilder.getMF(); unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8; unsigned Offset = VA.getLocMemOffset(); @@ -186,8 +187,8 @@ return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0); } -void IncomingValueHandler::assignValueToAddress(Register ValVReg, - const CCValAssign &VA) { +void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg, + const CCValAssign &VA) { if (VA.getLocInfo() == CCValAssign::SExt || VA.getLocInfo() == CCValAssign::ZExt || VA.getLocInfo() == CCValAssign::AExt) { @@ -197,10 +198,10 @@ buildLoad(ValVReg, VA); } -bool IncomingValueHandler::handleSplit(SmallVectorImpl &VRegs, - ArrayRef ArgLocs, - unsigned ArgLocsStartIndex, - Register ArgsReg, const EVT &VT) { +bool MipsIncomingValueHandler::handleSplit(SmallVectorImpl &VRegs, + ArrayRef ArgLocs, + unsigned ArgLocsStartIndex, + Register ArgsReg, const EVT &VT) { if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT)) return false; setLeastSignificantFirst(VRegs); @@ -209,10 +210,10 @@ } namespace { -class OutgoingValueHandler : public MipsCallLowering::MipsHandler { +class MipsOutgoingValueHandler : public MipsCallLowering::MipsHandler { public: - OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, - MachineInstrBuilder &MIB) + MipsOutgoingValueHandler(MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) : MipsHandler(MIRBuilder, MRI), MIB(MIB) {} private: @@ -234,9 +235,9 @@ }; } // end anonymous namespace -void OutgoingValueHandler::assignValueToReg(Register ValVReg, - const CCValAssign &VA, - const EVT &VT) { +void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg, + const CCValAssign &VA, + const EVT &VT) { Register PhysReg = VA.getLocReg(); if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { const MipsSubtarget &STI = @@ -254,8 +255,8 @@ } } -Register OutgoingValueHandler::getStackAddress(const CCValAssign &VA, - MachineMemOperand *&MMO) { +Register MipsOutgoingValueHandler::getStackAddress(const CCValAssign &VA, + MachineMemOperand *&MMO) { MachineFunction &MF = MIRBuilder.getMF(); const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); @@ -278,16 +279,16 @@ return AddrReg.getReg(0); } -void OutgoingValueHandler::assignValueToAddress(Register ValVReg, - const CCValAssign &VA) { +void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg, + const CCValAssign &VA) { MachineMemOperand *MMO; Register Addr = getStackAddress(VA, MMO); Register ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildStore(ExtReg, Addr, *MMO); } -Register OutgoingValueHandler::extendRegister(Register ValReg, - const CCValAssign &VA) { +Register MipsOutgoingValueHandler::extendRegister(Register ValReg, + const CCValAssign &VA) { LLT LocTy{VA.getLocVT()}; switch (VA.getLocInfo()) { case CCValAssign::SExt: { @@ -308,10 +309,10 @@ llvm_unreachable("unable to extend register"); } -bool OutgoingValueHandler::handleSplit(SmallVectorImpl &VRegs, - ArrayRef ArgLocs, - unsigned ArgLocsStartIndex, - Register ArgsReg, const EVT &VT) { +bool MipsOutgoingValueHandler::handleSplit(SmallVectorImpl &VRegs, + ArrayRef ArgLocs, + unsigned ArgLocsStartIndex, + Register ArgsReg, const EVT &VT) { MIRBuilder.buildUnmerge(VRegs, ArgsReg); setLeastSignificantFirst(VRegs); if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT)) @@ -403,7 +404,7 @@ CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn()); setLocInfo(ArgLocs, Outs); - OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret); + MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret); if (!RetHandler.handle(ArgLocs, RetInfos)) { return false; } @@ -455,7 +456,7 @@ CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall()); setLocInfo(ArgLocs, Ins); - IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo()); + MipsIncomingValueHandler Handler(MIRBuilder, MF.getRegInfo()); if (!Handler.handle(ArgLocs, ArgInfos)) return false; @@ -579,7 +580,7 @@ CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call); setLocInfo(ArgLocs, Outs); - OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB); + MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB); if (!RetHandler.handle(ArgLocs, ArgInfos)) { return false; } Index: llvm/lib/Target/X86/X86CallLowering.cpp =================================================================== --- llvm/lib/Target/X86/X86CallLowering.cpp +++ llvm/lib/Target/X86/X86CallLowering.cpp @@ -95,15 +95,14 @@ namespace { -struct OutgoingValueHandler : public CallLowering::ValueHandler { - OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, - MachineInstrBuilder &MIB, CCAssignFn *AssignFn) - : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), +struct X86OutgoingValueHandler : public CallLowering::IncomingValueHandler { + X86OutgoingValueHandler(MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI, MachineInstrBuilder &MIB, + CCAssignFn *AssignFn) + : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), DL(MIRBuilder.getMF().getDataLayout()), STI(MIRBuilder.getMF().getSubtarget()) {} - bool isIncomingArgumentHandler() const override { return false; } - Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0)); @@ -215,7 +214,7 @@ return false; } - OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86); + X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86); if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) return false; } @@ -226,14 +225,12 @@ namespace { -struct IncomingValueHandler : public CallLowering::ValueHandler { - IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, - CCAssignFn *AssignFn) - : ValueHandler(MIRBuilder, MRI, AssignFn), +struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler { + X86IncomingValueHandler(MachineIRBuilder &MIRBuilder, + MachineRegisterInfo &MRI, CCAssignFn *AssignFn) + : IncomingValueHandler(MIRBuilder, MRI, AssignFn), DL(MIRBuilder.getMF().getDataLayout()) {} - bool isIncomingArgumentHandler() const override { return true; } - Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO) override { auto &MFI = MIRBuilder.getMF().getFrameInfo(); @@ -298,10 +295,10 @@ const DataLayout &DL; }; -struct FormalArgHandler : public IncomingValueHandler { +struct FormalArgHandler : public X86IncomingValueHandler { FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, CCAssignFn *AssignFn) - : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {} + : X86IncomingValueHandler(MIRBuilder, MRI, AssignFn) {} void markPhysRegUsed(unsigned PhysReg) override { MIRBuilder.getMRI()->addLiveIn(PhysReg); @@ -309,10 +306,10 @@ } }; -struct CallReturnHandler : public IncomingValueHandler { +struct CallReturnHandler : public X86IncomingValueHandler { CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, CCAssignFn *AssignFn, MachineInstrBuilder &MIB) - : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} + : X86IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} void markPhysRegUsed(unsigned PhysReg) override { MIB.addDef(PhysReg, RegState::Implicit); @@ -421,7 +418,7 @@ return false; } // Do the actual argument marshalling. - OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86); + X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86); if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) return false;