diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -186,13 +186,16 @@
 
 BUILTIN(__builtin_altivec_vsl, "V4iV4iV4i", "")
 BUILTIN(__builtin_altivec_vslo, "V4iV4iV4i", "")
+BUILTIN(__builtin_altivec_vslq, "V1ULLLiV1ULLLiV1ULLLi", "")
 
 BUILTIN(__builtin_altivec_vsrab, "V16cV16cV16Uc", "")
 BUILTIN(__builtin_altivec_vsrah, "V8sV8sV8Us", "")
 BUILTIN(__builtin_altivec_vsraw, "V4iV4iV4Ui", "")
+BUILTIN(__builtin_altivec_vsraq, "V1ULLLiV1ULLLiV1ULLLi", "")
 
 BUILTIN(__builtin_altivec_vsr, "V4iV4iV4i", "")
 BUILTIN(__builtin_altivec_vsro, "V4iV4iV4i", "")
+BUILTIN(__builtin_altivec_vsrq, "V1ULLLiV1ULLLiV1ULLLi", "")
 
 BUILTIN(__builtin_altivec_vrfin, "V4fV4f", "")
 
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -17095,6 +17095,37 @@
   return __builtin_vsx_xxblendvd(__a, __b, __c);
 }
 #endif /* __VSX__ */
+
+/* vector shifts for quadwords */
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sl(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+  return __builtin_altivec_vsl(__a, __b);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sl(vector unsigned __int128 __a, vector signed __int128 __b) {
+  return __builtin_altivec_vsl(__a, (vector unsigned __int128) __b);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sr(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+  return __builtin_altivec_vsr(__a, __b);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sr(vector unsigned __int128 __a, vector signed __int128 __b) {
+  return __builtin_altivec_vsr(__a, (vector unsigned __int128) __b);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sra(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+  return __builtin_altivec_vsraq(__a, __b);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sra(vector unsigned __int128 __a, vector signed __int128 __b) {
+  return __builtin_altivec_vsraq(__a, (vector unsigned __int128) __b);
+}
 #endif /* __POWER10_VECTOR__ */
 
 #undef __ATTRS_o_ai
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -788,6 +788,7 @@
 def int_ppc_altivec_vsrv  : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
 def int_ppc_altivec_vslh  : PowerPC_Vec_HHH_Intrinsic<"vslh">;
 def int_ppc_altivec_vslw  : PowerPC_Vec_WWW_Intrinsic<"vslw">;
+def int_ppc_altivec_vslq  : PowerPC_Vec_QQQ_Intrinsic<"vslq">;
 
 // Right Shifts.
 def int_ppc_altivec_vsr   : PowerPC_Vec_WWW_Intrinsic<"vsr">;
@@ -796,9 +797,11 @@
 def int_ppc_altivec_vsrb  : PowerPC_Vec_BBB_Intrinsic<"vsrb">;
 def int_ppc_altivec_vsrh  : PowerPC_Vec_HHH_Intrinsic<"vsrh">;
 def int_ppc_altivec_vsrw  : PowerPC_Vec_WWW_Intrinsic<"vsrw">;
+def int_ppc_altivec_vsrq   : PowerPC_Vec_QQQ_Intrinsic<"vsrq">;
 def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">;
 def int_ppc_altivec_vsrah : PowerPC_Vec_HHH_Intrinsic<"vsrah">;
 def int_ppc_altivec_vsraw : PowerPC_Vec_WWW_Intrinsic<"vsraw">;
+def int_ppc_altivec_vsraq : PowerPC_Vec_QQQ_Intrinsic<"vsraq">;
 
 // Rotates.
 def int_ppc_altivec_vrlb  : PowerPC_Vec_BBB_Intrinsic<"vrlb">;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -915,6 +915,11 @@
                          "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
                          [(set v16i8:$vD,
                                (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+
+  def VSLQ   : VX1_Int_Ty< 261, "vslq", int_ppc_altivec_vslq, v1i128>;
+  def VSRAQ  : VX1_Int_Ty< 773, "vsraq", int_ppc_altivec_vsraq, v1i128>;
+  def VSRQ   : VX1_Int_Ty< 517, "vsrq" , int_ppc_altivec_vsrq, v1i128>;
+
 }
 
 //---------------------------- Anonymous Patterns ----------------------------//
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -278,3 +278,12 @@
 
 # CHECK: vinsdrx 1, 2, 3
 0x10 0x22 0x1b 0xcf
+
+# CHECK: vsrq 2, 3, 4
+0x10 0x43 0x22 0x05
+
+# CHECK: vslq 2, 3, 4
+0x10 0x43 0x21 0x05
+
+# CHECK: vsraq 2, 3, 4
+0x10 0x43 0x23 0x05
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -405,3 +405,12 @@
 # CHECK-BE: vinsdrx 1, 2, 3                       # encoding: [0x10,0x22,0x1b,0xcf]
 # CHECK-LE: vinsdrx 1, 2, 3                       # encoding: [0xcf,0x1b,0x22,0x10]
             vinsdrx 1, 2, 3
+# CHECK-BE: vslq 2, 3, 4                          # encoding: [0x10,0x43,0x21,0x05]
+# CHECK-LE: vslq 2, 3, 4                          # encoding: [0x05,0x21,0x43,0x10]
+            vslq 2, 3, 4
+# CHECK-BE: vsraq 2, 3, 4                         # encoding: [0x10,0x43,0x23,0x05]
+# CHECK-LE: vsraq 2, 3, 4                         # encoding: [0x05,0x23,0x43,0x10]
+            vsraq 2, 3, 4
+# CHECK-BE: vsrq 2, 3, 4                          # encoding: [0x10,0x43,0x22,0x05]
+# CHECK-LE: vsrq 2, 3, 4                          # encoding: [0x05,0x22,0x43,0x10]
+            vsrq 2, 3, 4