diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -83,11 +83,8 @@
       return;
     }
     int64_t Imm = ConstNode->getSExtValue();
-    if (XLenVT == MVT::i64) {
-      ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));
-      return;
-    }
-    break;
+    ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));
+    return;
   }
   case ISD::FrameIndex: {
     SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT);
diff --git a/llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp
--- a/llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp
@@ -16,7 +16,62 @@
 namespace llvm {
 
 namespace RISCVMatInt {
-void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) {
+static void generateInstSeq32(int32_t Val, InstSeq &Res) {
+  int32_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
+  int32_t Lo12 = SignExtend32<12>(Val);
+
+  // Does the general case require LUI+ADDI, and they aren't both compressed?
+  // If so, first try to materialize the constant using shifts.
+  if (Hi20 && Lo12 && (!isInt<6>(Hi20) || !isInt<6>(Lo12))) {
+    unsigned FirstSet = findFirstSet((uint32_t)Val);
+
+    // Try XXX0* -> ADDI(XXX)+SLLI.
+    int ShiftAmount = FirstSet;
+    if (ShiftAmount > 0) {
+      int32_t AltVal = SignExtend32(Val >> ShiftAmount, 32 - ShiftAmount);
+      if (isInt<12>(AltVal)) {
+        Res.push_back(Inst(RISCV::ADDI, AltVal));
+        Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
+        return;
+      }
+    }
+
+    if (Val > 0) {
+      // Try 0*XXX -> ADDI(XXX1*)+SRLI.
+      int ShiftAmount = countLeadingZeros((uint32_t)Val);
+      int32_t AltVal = (Val << ShiftAmount) | ((1 << ShiftAmount) - 1);
+      if (isInt<12>(AltVal)) {
+        Res.push_back(Inst(RISCV::ADDI, AltVal));
+        Res.push_back(Inst(RISCV::SRLI, ShiftAmount));
+        return;
+      }
+
+      // Try 0*XXX -> LUI(XXX)+SRLI.
+      if (isUInt<20>(Val >> FirstSet)) {
+        AltVal = uint32_t(Val << ShiftAmount) >> 12;
+        Res.push_back(Inst(RISCV::LUI, AltVal));
+        Res.push_back(Inst(RISCV::SRLI, ShiftAmount));
+        return;
+      }
+    }
+  }
+
+  // Depending on the active bits in the constant, the following
+  // instruction sequences are emitted in the general case:
+  //
+  // Val == 0                          : ADDI
+  // Val[0,12) != 0 && Val[12,32) == 0 : ADDI
+  // Val[0,12) == 0 && Val[12,32) != 0 : LUI
+  // Val[0,32) != 0                    : LUI+ADDI(W)
+
+  if (Hi20)
+    Res.push_back(Inst(RISCV::LUI, Hi20));
+
+  if (Lo12 || Hi20 == 0)
+    Res.push_back(Inst(RISCV::ADDI, Lo12));
+}
+
+static void generateInstSeq64(int64_t Val, InstSeq &Res) {
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
     // instruction sequences are emitted:
@@ -32,14 +87,12 @@
       Res.push_back(Inst(RISCV::LUI, Hi20));
 
     if (Lo12 || Hi20 == 0) {
-      unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
+      unsigned AddiOpc = Hi20 ? RISCV::ADDIW : RISCV::ADDI;
       Res.push_back(Inst(AddiOpc, Lo12));
     }
     return;
   }
 
-  assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
-
   // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
   // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
   // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
@@ -68,13 +121,22 @@
   int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
   Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
 
-  generateInstSeq(Hi52, IsRV64, Res);
+  generateInstSeq64(Hi52, Res);
 
   Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
   if (Lo12)
     Res.push_back(Inst(RISCV::ADDI, Lo12));
 }
 
+void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) {
+  if (!IsRV64) {
+    assert(isInt<32>(Val));
+    generateInstSeq32(Val, Res);
+  }
+  else
+    generateInstSeq64(Val, Res);
+}
+
 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) {
   int PlatRegSize = IsRV64 ? 64 : 32;
 
diff --git a/llvm/test/CodeGen/RISCV/alu16.ll b/llvm/test/CodeGen/RISCV/alu16.ll
--- a/llvm/test/CodeGen/RISCV/alu16.ll
+++ b/llvm/test/CodeGen/RISCV/alu16.ll
@@ -121,8 +121,8 @@
 define i16 @srli(i16 %a) nounwind {
 ; RV32I-LABEL: srli:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi a1, a1, -64
+; RV32I-NEXT:    addi a1, zero, 1023
+; RV32I-NEXT:    slli a1, a1, 6
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    srli a0, a0, 6
 ; RV32I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
--- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
@@ -30,8 +30,8 @@
 ; RV32I-LABEL: test_bswap_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a1, a0, 8
-; RV32I-NEXT:    lui a2, 16
-; RV32I-NEXT:    addi a2, a2, -256
+; RV32I-NEXT:    addi a2, zero, 255
+; RV32I-NEXT:    slli a2, a2, 8
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    srli a2, a0, 24
 ; RV32I-NEXT:    or a1, a1, a2
@@ -50,8 +50,8 @@
 ; RV32I-LABEL: test_bswap_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a2, a1, 8
-; RV32I-NEXT:    lui a3, 16
-; RV32I-NEXT:    addi a3, a3, -256
+; RV32I-NEXT:    addi a3, zero, 255
+; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    srli a4, a1, 24
 ; RV32I-NEXT:    or a2, a2, a4
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
@@ -788,8 +788,8 @@
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
 ; RV32I-FPELIM-NEXT:    call callee_small_scalar_ret
-; RV32I-FPELIM-NEXT:    lui a2, 56
-; RV32I-FPELIM-NEXT:    addi a2, a2, 580
+; RV32I-FPELIM-NEXT:    lui a2, 919824
+; RV32I-FPELIM-NEXT:    srli a2, a2, 14
 ; RV32I-FPELIM-NEXT:    xor a1, a1, a2
 ; RV32I-FPELIM-NEXT:    lui a2, 200614
 ; RV32I-FPELIM-NEXT:    addi a2, a2, 647
@@ -807,8 +807,8 @@
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    call callee_small_scalar_ret
-; RV32I-WITHFP-NEXT:    lui a2, 56
-; RV32I-WITHFP-NEXT:    addi a2, a2, 580
+; RV32I-WITHFP-NEXT:    lui a2, 919824
+; RV32I-WITHFP-NEXT:    srli a2, a2, 14
 ; RV32I-WITHFP-NEXT:    xor a1, a1, a2
 ; RV32I-WITHFP-NEXT:    lui a2, 200614
 ; RV32I-WITHFP-NEXT:    addi a2, a2, 647
diff --git a/llvm/test/CodeGen/RISCV/copysign-casts.ll b/llvm/test/CodeGen/RISCV/copysign-casts.ll
--- a/llvm/test/CodeGen/RISCV/copysign-casts.ll
+++ b/llvm/test/CodeGen/RISCV/copysign-casts.ll
@@ -21,7 +21,8 @@
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 524288
 ; RV32I-NEXT:    and a2, a2, a3
-; RV32I-NEXT:    addi a3, a3, -1
+; RV32I-NEXT:    addi a3, zero, -1
+; RV32I-NEXT:    srli a3, a3, 1
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
@@ -44,7 +45,8 @@
 ; RV32IF-NEXT:    fmv.x.w a2, fa0
 ; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:    and a2, a2, a3
-; RV32IF-NEXT:    addi a3, a3, -1
+; RV32IF-NEXT:    addi a3, zero, -1
+; RV32IF-NEXT:    srli a3, a3, 1
 ; RV32IF-NEXT:    and a1, a1, a3
 ; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    ret
@@ -69,10 +71,11 @@
 ; RV32I-LABEL: fold_demote:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    and a2, a2, a1
-; RV32I-NEXT:    addi a1, a1, -1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    addi a2, zero, -1
+; RV32I-NEXT:    srli a2, a2, 1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_demote:
diff --git a/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
--- a/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
@@ -52,15 +52,15 @@
 define double @fabs(double %a) nounwind {
 ; RV32I-LABEL: fabs:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 524288
-; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    addi a2, zero, -1
+; RV32I-NEXT:    srli a2, a2, 1
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fabs:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    addi a2, zero, -1
+; RV32IFD-NEXT:    srli a2, a2, 1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
@@ -95,7 +95,8 @@
 ; RV32I-NEXT:    not a2, a3
 ; RV32I-NEXT:    lui a3, 524288
 ; RV32I-NEXT:    and a2, a2, a3
-; RV32I-NEXT:    addi a3, a3, -1
+; RV32I-NEXT:    addi a3, zero, -1
+; RV32I-NEXT:    srli a3, a3, 1
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
--- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll
@@ -380,8 +380,8 @@
 define double @fabs_f64(double %a) nounwind {
 ; RV32IFD-LABEL: fabs_f64:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    addi a2, a2, -1
+; RV32IFD-NEXT:    addi a2, zero, -1
+; RV32IFD-NEXT:    srli a2, a2, 1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
--- a/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
@@ -73,8 +73,8 @@
 ; RV32F-NEXT:    mv s1, a0
 ; RV32F-NEXT:    call __adddf3
 ; RV32F-NEXT:    mv a2, a0
-; RV32F-NEXT:    lui a0, 524288
-; RV32F-NEXT:    addi a0, a0, -1
+; RV32F-NEXT:    addi a0, zero, -1
+; RV32F-NEXT:    srli a0, a0, 1
 ; RV32F-NEXT:    and a3, a1, a0
 ; RV32F-NEXT:    mv a0, s1
 ; RV32F-NEXT:    mv a1, s0
diff --git a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
--- a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
+++ b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
@@ -47,15 +47,15 @@
 define float @fabs(float %a) nounwind {
 ; RV32I-LABEL: fabs:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    addi a1, a1, -1
+; RV32I-NEXT:    addi a1, zero, -1
+; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fabs:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    addi a1, a1, -1
+; RV32IF-NEXT:    addi a1, zero, -1
+; RV32IF-NEXT:    srli a1, a1, 1
 ; RV32IF-NEXT:    and a0, a0, a1
 ; RV32IF-NEXT:    ret
 ;
@@ -88,7 +88,8 @@
 ; RV32I-NEXT:    not a1, a1
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    and a1, a1, a2
-; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    addi a2, zero, -1
+; RV32I-NEXT:    srli a2, a2, 1
 ; RV32I-NEXT:    and a0, a0, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
--- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -348,8 +348,8 @@
 define float @fabs_f32(float %a) nounwind {
 ; RV32IF-LABEL: fabs_f32:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    addi a1, a1, -1
+; RV32IF-NEXT:    addi a1, zero, -1
+; RV32IF-NEXT:    srli a1, a1, 1
 ; RV32IF-NEXT:    and a0, a0, a1
 ; RV32IF-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
--- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
@@ -279,8 +279,9 @@
 define i64 @load_cost_overflow() nounwind {
 ; RV32I-LABEL: load_cost_overflow:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    lw a1, -2048(a0)
+; RV32I-NEXT:    addi a0, zero, 1
+; RV32I-NEXT:    slli a0, a0, 11
+; RV32I-NEXT:    lw a1, 0(a0)
 ; RV32I-NEXT:    lw a0, 2044(zero)
 ; RV32I-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
--- a/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
+++ b/llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
@@ -60,8 +60,11 @@
 define i8* @big_offset_neg_addi() nounwind {
 ; CHECK-LABEL: big_offset_neg_addi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(g+73568)
-; CHECK-NEXT:    addi a0, a0, %lo(g+73568)
+; CHECK-NEXT:    lui a0, 588544
+; CHECK-NEXT:    srli a0, a0, 15
+; CHECK-NEXT:    lui a1, %hi(g)
+; CHECK-NEXT:    addi a1, a1, %lo(g)
+; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    ret
   ret i8* getelementptr inbounds ([1048576 x i8], [1048576 x i8]* @g, i32 0, i32 73568)
 }
@@ -84,8 +87,11 @@
 define dso_local i32* @big_offset_one_use() local_unnamed_addr nounwind {
 ; CHECK-LABEL: big_offset_one_use:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lui a0, %hi(s+16572)
-; CHECK-NEXT:    addi a0, a0, %lo(s+16572)
+; CHECK-NEXT:    lui a0, 530304
+; CHECK-NEXT:    srli a0, a0, 17
+; CHECK-NEXT:    lui a1, %hi(s)
+; CHECK-NEXT:    addi a1, a1, %lo(s)
+; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    ret
 entry:
   ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 5)
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -110,8 +110,8 @@
 define signext i32 @imm_left_shifted_addi() nounwind {
 ; RV32I-LABEL: imm_left_shifted_addi:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 32
-; RV32I-NEXT:    addi a0, a0, -64
+; RV32I-NEXT:    addi a0, zero, 2047
+; RV32I-NEXT:    slli a0, a0, 6
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_left_shifted_addi:
@@ -127,8 +127,8 @@
 define signext i32 @imm_right_shifted_addi() nounwind {
 ; RV32I-LABEL: imm_right_shifted_addi:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 524288
-; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    addi a0, zero, -1
+; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_right_shifted_addi:
@@ -144,8 +144,8 @@
 define signext i32 @imm_right_shifted_lui() nounwind {
 ; RV32I-LABEL: imm_right_shifted_lui:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 56
-; RV32I-NEXT:    addi a0, a0, 580
+; RV32I-NEXT:    lui a0, 919824
+; RV32I-NEXT:    srli a0, a0, 14
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_right_shifted_lui:
@@ -428,8 +428,8 @@
 define i64 @imm_end_xori_1() nounwind {
 ; RV32I-LABEL: imm_end_xori_1:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a0, 8192
-; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    addi a0, zero, -1
+; RV32I-NEXT:    srli a0, a0, 7
 ; RV32I-NEXT:    lui a1, 917504
 ; RV32I-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/RISCV/large-stack.ll b/llvm/test/CodeGen/RISCV/large-stack.ll
--- a/llvm/test/CodeGen/RISCV/large-stack.ll
+++ b/llvm/test/CodeGen/RISCV/large-stack.ll
@@ -54,12 +54,12 @@
 ; RV32I-FPELIM-NEXT:    sw s1, 2024(sp)
 ; RV32I-FPELIM-NEXT:    .cfi_offset s0, -4
 ; RV32I-FPELIM-NEXT:    .cfi_offset s1, -8
-; RV32I-FPELIM-NEXT:    lui a1, 97
-; RV32I-FPELIM-NEXT:    addi a1, a1, 672
+; RV32I-FPELIM-NEXT:    lui a1, 795968
+; RV32I-FPELIM-NEXT:    srli a1, a1, 13
 ; RV32I-FPELIM-NEXT:    sub sp, sp, a1
 ; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 400016
-; RV32I-FPELIM-NEXT:    lui a1, 78
-; RV32I-FPELIM-NEXT:    addi a1, a1, 512
+; RV32I-FPELIM-NEXT:    addi a1, zero, 625
+; RV32I-FPELIM-NEXT:    slli a1, a1, 9
 ; RV32I-FPELIM-NEXT:    addi a2, sp, 8
 ; RV32I-FPELIM-NEXT:    add a1, a2, a1
 ; RV32I-FPELIM-NEXT:    #APP
@@ -69,8 +69,8 @@
 ; RV32I-FPELIM-NEXT:    #APP
 ; RV32I-FPELIM-NEXT:    nop
 ; RV32I-FPELIM-NEXT:    #NO_APP
-; RV32I-FPELIM-NEXT:    lui a0, 97
-; RV32I-FPELIM-NEXT:    addi a0, a0, 672
+; RV32I-FPELIM-NEXT:    lui a0, 795968
+; RV32I-FPELIM-NEXT:    srli a0, a0, 13
 ; RV32I-FPELIM-NEXT:    add sp, sp, a0
 ; RV32I-FPELIM-NEXT:    lw s1, 2024(sp)
 ; RV32I-FPELIM-NEXT:    lw s0, 2028(sp)
@@ -91,11 +91,11 @@
 ; RV32I-WITHFP-NEXT:    .cfi_offset s2, -16
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 2032
 ; RV32I-WITHFP-NEXT:    .cfi_def_cfa s0, 0
-; RV32I-WITHFP-NEXT:    lui a1, 97
-; RV32I-WITHFP-NEXT:    addi a1, a1, 688
+; RV32I-WITHFP-NEXT:    lui a1, 796000
+; RV32I-WITHFP-NEXT:    srli a1, a1, 13
 ; RV32I-WITHFP-NEXT:    sub sp, sp, a1
-; RV32I-WITHFP-NEXT:    lui a1, 78
-; RV32I-WITHFP-NEXT:    addi a1, a1, 512
+; RV32I-WITHFP-NEXT:    addi a1, zero, 625
+; RV32I-WITHFP-NEXT:    slli a1, a1, 9
 ; RV32I-WITHFP-NEXT:    lui a2, 1048478
 ; RV32I-WITHFP-NEXT:    addi a2, a2, 1388
 ; RV32I-WITHFP-NEXT:    add a2, s0, a2
@@ -108,8 +108,8 @@
 ; RV32I-WITHFP-NEXT:    #APP
 ; RV32I-WITHFP-NEXT:    nop
 ; RV32I-WITHFP-NEXT:    #NO_APP
-; RV32I-WITHFP-NEXT:    lui a0, 97
-; RV32I-WITHFP-NEXT:    addi a0, a0, 688
+; RV32I-WITHFP-NEXT:    lui a0, 796000
+; RV32I-WITHFP-NEXT:    srli a0, a0, 13
 ; RV32I-WITHFP-NEXT:    add sp, sp, a0
 ; RV32I-WITHFP-NEXT:    lw s2, 2016(sp)
 ; RV32I-WITHFP-NEXT:    lw s1, 2020(sp)
diff --git a/llvm/test/CodeGen/RISCV/split-offsets.ll b/llvm/test/CodeGen/RISCV/split-offsets.ll
--- a/llvm/test/CodeGen/RISCV/split-offsets.ll
+++ b/llvm/test/CodeGen/RISCV/split-offsets.ll
@@ -12,8 +12,8 @@
 ; RV32I-LABEL: test1:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lw a0, 0(a0)
-; RV32I-NEXT:    lui a2, 20
-; RV32I-NEXT:    addi a2, a2, -1920
+; RV32I-NEXT:    addi a2, zero, 625
+; RV32I-NEXT:    slli a2, a2, 7
 ; RV32I-NEXT:    add a1, a1, a2
 ; RV32I-NEXT:    add a0, a0, a2
 ; RV32I-NEXT:    addi a2, zero, 2
@@ -57,8 +57,8 @@
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    lw a4, 0(a0)
-; RV32I-NEXT:    lui a0, 20
-; RV32I-NEXT:    addi a5, a0, -1920
+; RV32I-NEXT:    addi a0, zero, 625
+; RV32I-NEXT:    slli a5, a0, 7
 ; RV32I-NEXT:    add a0, a1, a5
 ; RV32I-NEXT:    add a1, a4, a5
 ; RV32I-NEXT:    bge a3, a2, .LBB1_2
diff --git a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
--- a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
@@ -677,18 +677,19 @@
 ; RV32I-NEXT:    lh a1, 4(a1)
 ; RV32I-NEXT:    srli a4, a2, 26
 ; RV32I-NEXT:    add a4, a2, a4
-; RV32I-NEXT:    lui a6, 16
-; RV32I-NEXT:    addi a5, a6, -64
+; RV32I-NEXT:    addi a5, zero, 1023
+; RV32I-NEXT:    slli a5, a5, 6
 ; RV32I-NEXT:    and a4, a4, a5
 ; RV32I-NEXT:    sub s2, a2, a4
 ; RV32I-NEXT:    srli a2, a1, 27
 ; RV32I-NEXT:    add a2, a1, a2
-; RV32I-NEXT:    addi a4, a6, -32
-; RV32I-NEXT:    and a2, a2, a4
+; RV32I-NEXT:    lui a4, 16
+; RV32I-NEXT:    addi a5, a4, -32
+; RV32I-NEXT:    and a2, a2, a5
 ; RV32I-NEXT:    sub s3, a1, a2
 ; RV32I-NEXT:    srli a1, a3, 29
 ; RV32I-NEXT:    add a1, a3, a1
-; RV32I-NEXT:    addi a2, a6, -8
+; RV32I-NEXT:    addi a2, a4, -8
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub s1, a3, a1
 ; RV32I-NEXT:    addi a1, zero, 95
@@ -723,14 +724,15 @@
 ; RV32IM-NEXT:    sub a7, a4, a2
 ; RV32IM-NEXT:    srli a4, a1, 26
 ; RV32IM-NEXT:    add a4, a1, a4
+; RV32IM-NEXT:    addi a5, zero, 1023
+; RV32IM-NEXT:    slli a5, a5, 6
+; RV32IM-NEXT:    and a4, a4, a5
+; RV32IM-NEXT:    sub a1, a1, a4
+; RV32IM-NEXT:    srli a4, a3, 27
+; RV32IM-NEXT:    add a4, a3, a4
 ; RV32IM-NEXT:    lui a5, 16
-; RV32IM-NEXT:    addi a2, a5, -64
+; RV32IM-NEXT:    addi a2, a5, -32
 ; RV32IM-NEXT:    and a2, a4, a2
-; RV32IM-NEXT:    sub a1, a1, a2
-; RV32IM-NEXT:    srli a2, a3, 27
-; RV32IM-NEXT:    add a2, a3, a2
-; RV32IM-NEXT:    addi a4, a5, -32
-; RV32IM-NEXT:    and a2, a2, a4
 ; RV32IM-NEXT:    sub a2, a3, a2
 ; RV32IM-NEXT:    srli a3, a6, 29
 ; RV32IM-NEXT:    add a3, a6, a3
@@ -855,8 +857,8 @@
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a1, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a1, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    sh zero, 0(s0)
@@ -902,8 +904,8 @@
 ; RV32IM-NEXT:    srli a5, a4, 31
 ; RV32IM-NEXT:    srli a4, a4, 11
 ; RV32IM-NEXT:    add a4, a4, a5
-; RV32IM-NEXT:    lui a5, 1
-; RV32IM-NEXT:    addi a5, a5, 1327
+; RV32IM-NEXT:    lui a5, 694144
+; RV32IM-NEXT:    srli a5, a5, 19
 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a2, a2, a4
 ; RV32IM-NEXT:    sh zero, 0(a0)
@@ -1031,8 +1033,8 @@
 ; RV32I-NEXT:    addi a1, zero, 23
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a1, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a1, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __modsi3
 ; RV32I-NEXT:    sh zero, 0(s0)
@@ -1068,8 +1070,8 @@
 ; RV32IM-NEXT:    srli a5, a4, 31
 ; RV32IM-NEXT:    srli a4, a4, 11
 ; RV32IM-NEXT:    add a4, a4, a5
-; RV32IM-NEXT:    lui a5, 1
-; RV32IM-NEXT:    addi a5, a5, 1327
+; RV32IM-NEXT:    lui a5, 694144
+; RV32IM-NEXT:    srli a5, a5, 19
 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a1, a1, a4
 ; RV32IM-NEXT:    srli a4, a2, 17
@@ -1215,8 +1217,8 @@
 ; RV32I-NEXT:    call __moddi3
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a2, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a2, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
@@ -1286,8 +1288,8 @@
 ; RV32IM-NEXT:    call __moddi3
 ; RV32IM-NEXT:    mv s4, a0
 ; RV32IM-NEXT:    mv s1, a1
-; RV32IM-NEXT:    lui a0, 1
-; RV32IM-NEXT:    addi a2, a0, 1327
+; RV32IM-NEXT:    lui a0, 694144
+; RV32IM-NEXT:    srli a2, a0, 19
 ; RV32IM-NEXT:    mv a0, s2
 ; RV32IM-NEXT:    mv a1, s3
 ; RV32IM-NEXT:    mv a3, zero
diff --git a/llvm/test/CodeGen/RISCV/stack-realignment.ll b/llvm/test/CodeGen/RISCV/stack-realignment.ll
--- a/llvm/test/CodeGen/RISCV/stack-realignment.ll
+++ b/llvm/test/CodeGen/RISCV/stack-realignment.ll
@@ -315,13 +315,13 @@
 ; RV32I-NEXT:    addi s0, sp, 2032
 ; RV32I-NEXT:    addi sp, sp, -1040
 ; RV32I-NEXT:    andi sp, sp, -1024
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    addi a0, zero, 1
+; RV32I-NEXT:    slli a0, a0, 11
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a0, a0, -1024
+; RV32I-NEXT:    addi a0, zero, 3
+; RV32I-NEXT:    slli a0, a0, 10
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    addi sp, sp, 1040
 ; RV32I-NEXT:    lw s0, 2024(sp)
@@ -395,8 +395,8 @@
 ; RV32I-NEXT:    add a0, sp, a0
 ; RV32I-NEXT:    mv a0, a0
 ; RV32I-NEXT:    call callee
-; RV32I-NEXT:    lui a0, 2
-; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    addi a0, zero, 3
+; RV32I-NEXT:    slli a0, a0, 11
 ; RV32I-NEXT:    sub sp, s0, a0
 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    addi a0, a0, 16
@@ -467,8 +467,8 @@
 ; RV32I-NEXT:    sw ra, 2028(sp)
 ; RV32I-NEXT:    sw s0, 2024(sp)
 ; RV32I-NEXT:    addi s0, sp, 2032
-; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    addi a0, a0, -2032
+; RV32I-NEXT:    addi a0, zero, 641
+; RV32I-NEXT:    slli a0, a0, 4
 ; RV32I-NEXT:    sub sp, sp, a0
 ; RV32I-NEXT:    srli a0, sp, 12
 ; RV32I-NEXT:    slli sp, a0, 12
@@ -478,8 +478,8 @@
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    lui a0, 3
 ; RV32I-NEXT:    sub sp, s0, a0
-; RV32I-NEXT:    lui a0, 3
-; RV32I-NEXT:    addi a0, a0, -2032
+; RV32I-NEXT:    addi a0, zero, 641
+; RV32I-NEXT:    slli a0, a0, 4
 ; RV32I-NEXT:    add sp, sp, a0
 ; RV32I-NEXT:    lw s0, 2024(sp)
 ; RV32I-NEXT:    lw ra, 2028(sp)
diff --git a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
--- a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
@@ -795,8 +795,8 @@
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a1, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a1, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __umodsi3
 ; RV32I-NEXT:    sh zero, 0(s0)
@@ -835,8 +835,8 @@
 ; RV32IM-NEXT:    addi a4, a4, -2009
 ; RV32IM-NEXT:    mulhu a4, a3, a4
 ; RV32IM-NEXT:    srli a4, a4, 11
-; RV32IM-NEXT:    lui a5, 1
-; RV32IM-NEXT:    addi a5, a5, 1327
+; RV32IM-NEXT:    lui a5, 694144
+; RV32IM-NEXT:    srli a5, a5, 19
 ; RV32IM-NEXT:    mul a4, a4, a5
 ; RV32IM-NEXT:    sub a3, a3, a4
 ; RV32IM-NEXT:    sh zero, 0(a0)
@@ -993,8 +993,8 @@
 ; RV32I-NEXT:    call __umoddi3
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv s1, a1
-; RV32I-NEXT:    lui a0, 1
-; RV32I-NEXT:    addi a2, a0, 1327
+; RV32I-NEXT:    lui a0, 694144
+; RV32I-NEXT:    srli a2, a0, 19
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
@@ -1064,8 +1064,8 @@
 ; RV32IM-NEXT:    call __umoddi3
 ; RV32IM-NEXT:    mv s4, a0
 ; RV32IM-NEXT:    mv s1, a1
-; RV32IM-NEXT:    lui a0, 1
-; RV32IM-NEXT:    addi a2, a0, 1327
+; RV32IM-NEXT:    lui a0, 694144
+; RV32IM-NEXT:    srli a2, a0, 19
 ; RV32IM-NEXT:    mv a0, s2
 ; RV32IM-NEXT:    mv a1, s3
 ; RV32IM-NEXT:    mv a3, zero
diff --git a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
--- a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
+++ b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
@@ -47,8 +47,8 @@
 ; RV32I-NEXT:    lhu a1, %lo(shorts)(a0)
 ; RV32I-NEXT:    addi a0, a0, %lo(shorts)
 ; RV32I-NEXT:    lhu a0, 2(a0)
-; RV32I-NEXT:    lui a2, 16
-; RV32I-NEXT:    addi a2, a2, -120
+; RV32I-NEXT:    lui a2, 1046656
+; RV32I-NEXT:    srli a2, a2, 16
 ; RV32I-NEXT:    xor a1, a1, a2
 ; RV32I-NEXT:    xori a0, a0, 7
 ; RV32I-NEXT:    or a0, a1, a0
diff --git a/llvm/test/MC/RISCV/rv32c-aliases-valid.s b/llvm/test/MC/RISCV/rv32c-aliases-valid.s
--- a/llvm/test/MC/RISCV/rv32c-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-aliases-valid.s
@@ -18,13 +18,13 @@
 li x10, 2047
 # CHECK-EXPAND: addi a0, zero, -2047
 li x10, -2047
-# CHECK-EXPAND: c.lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2048
+# CHECK-EXPAND: c.li a1, 1
+# CHECK-EXPAND: c.slli a1, 11
 li x11, 2048
 # CHECK-EXPAND: addi a1, zero, -2048
 li x11, -2048
-# CHECK-EXPAND: c.lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2047
+# CHECK-EXPAND: lui a1, 524544
+# CHECK-EXPAND: c.srli a1, 20
 li x11, 2049
 # CHECK-EXPAND: lui a1, 1048575
 # CHECK-EXPAND: addi a1, a1, 2047
@@ -45,8 +45,8 @@
 # CHECK-EXPAND: lui a2, 1048575
 # CHECK-EXPAND: c.addi a2, -1
 li x12, -4097
-# CHECK-EXPAND: lui a2, 524288
-# CHECK-EXPAND: c.addi a2, -1
+# CHECK-EXPAND: c.li a2, -1
+# CHECK-EXPAND: c.srli a2, 1
 li x12, 2147483647
 # CHECK-EXPAND: lui a2, 524288
 # CHECK-EXPAND: c.addi a2, 1
diff --git a/llvm/test/MC/RISCV/rv32i-aliases-valid.s b/llvm/test/MC/RISCV/rv32i-aliases-valid.s
--- a/llvm/test/MC/RISCV/rv32i-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32i-aliases-valid.s
@@ -28,13 +28,13 @@
 li x10, 2047
 # CHECK-EXPAND: addi a0, zero, -2047
 li x10, -2047
-# CHECK-EXPAND: lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2048
+# CHECK-EXPAND: addi a1, zero, 1
+# CHECK-EXPAND: slli a1, a1, 11
 li x11, 2048
 # CHECK-EXPAND: addi a1, zero, -2048
 li x11, -2048
-# CHECK-EXPAND: lui a1, 1
-# CHECK-EXPAND: addi a1, a1, -2047
+# CHECK-EXPAND: lui a1, 524544
+# CHECK-EXPAND: srli a1, a1, 20
 li x11, 2049
 # CHECK-EXPAND: lui a1, 1048575
 # CHECK-EXPAND: addi a1, a1, 2047
@@ -55,8 +55,8 @@
 # CHECK-EXPAND: lui a2, 1048575
 # CHECK-EXPAND: addi a2, a2, -1
 li x12, -4097
-# CHECK-EXPAND: lui a2, 524288
-# CHECK-EXPAND: addi a2, a2, -1
+# CHECK-EXPAND: addi a2, zero, -1
+# CHECK-EXPAND: srli a2, a2, 1
 li x12, 2147483647
 # CHECK-EXPAND: lui a2, 524288
 # CHECK-EXPAND: addi a2, a2, 1
@@ -82,8 +82,8 @@
 li a0, %pcrel_lo(.Lpcrel_hi0)
 
 .equ CONST, 0x123456
-# CHECK-EXPAND: lui a0, 291
-# CHECK-EXPAND: addi a0, a0, 1110
+# CHECK-EXPAND: lui a0, 596523
+# CHECK-EXPAND: srli a0, a0, 11
 li a0, CONST
 # CHECK-EXPAND: lui a0, 291
 # CHECK-EXPAND: addi a0, a0, 1111