diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -225,6 +225,14 @@
let Inst{21-31} = xo;
}
+// VX-Form: [PO VRT / UIM RB XO].
+// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
+// "/ UIM" (unused bit followed by a 4-bit immediate)
+class VX_VRT5_UIM5_RB5<bits<11> xo, string opc, list<dag> pattern>
+ : VXForm_1<xo, (outs vrrc:$VRT), (ins vrrc:$VRTi, u4imm:$UIM, g8rc:$RB),
+ !strconcat(opc, " $VRT, $RB, $UIM"), IIC_VecGeneral, pattern>,
+ RegConstraint<"$VRTi = $VRT">, NoEncode<"$VRTi">;
+
// VN-Form: [PO VRT VRA VRB PS SD XO]
// SD is "Shift Direction"
class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
@@ -751,6 +759,64 @@
(int_ppc_altivec_vsrdbi v16i8:$VRA,
v16i8:$VRB,
i32:$SH))]>;
+ def VINSW : VX_VRT5_UIM5_RB5<207, "vinsw", []>;
+ def VINSD : VX_VRT5_UIM5_RB5<463, "vinsd", []>;
+ def VINSBVLX : VXForm_1<15, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ vrrc:$vB), "vinsbvlx $vD, $rA, $vB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSBVRX : VXForm_1<271, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ vrrc:$vB), "vinsbvrx $vD, $rA, $vB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSHVLX : VXForm_1<79, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ vrrc:$vB), "vinshvlx $vD, $rA, $vB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSHVRX : VXForm_1<335, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ vrrc:$vB), "vinshvrx $vD, $rA, $vB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSWVLX : VXForm_1<143, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ vrrc:$vB), "vinswvlx $vD, $rA, $vB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSWVRX : VXForm_1<399, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ vrrc:$vB), "vinswvrx $vD, $rA, $vB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSBLX : VXForm_1<527, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ g8rc:$rB), "vinsblx $vD, $rA, $rB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSBRX : VXForm_1<783, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ g8rc:$rB), "vinsbrx $vD, $rA, $rB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSHLX : VXForm_1<591, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ g8rc:$rB), "vinshlx $vD, $rA, $rB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSHRX : VXForm_1<847, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ g8rc:$rB), "vinshrx $vD, $rA, $rB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSWLX : VXForm_1<655, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ g8rc:$rB), "vinswlx $vD, $rA, $rB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSWRX : VXForm_1<911, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ g8rc:$rB), "vinswrx $vD, $rA, $rB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSDLX : VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ g8rc:$rB), "vinsdlx $vD, $rA, $rB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VINSDRX : VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA,
+ g8rc:$rB), "vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
+ []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpdepd $vD, $vA, $vB", IIC_VecGeneral,
[(set v2i64:$vD,
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -230,3 +230,51 @@
# CHECK: vsrdbi 2, 3, 4, 5
0x10 0x43 0x23 0x56
+
+# CHECK: vinsw 2, 3, 12
+0x10 0x4c 0x18 0xcf
+
+# CHECK: vinsd 2, 3, 12
+0x10 0x4c 0x19 0xcf
+
+# CHECK: vinsbvlx 1, 3, 5
+0x10 0x23 0x28 0x0f
+
+# CHECK: vinsbvrx 1, 3, 5
+0x10 0x23 0x29 0x0f
+
+# CHECK: vinshvlx 1, 3, 5
+0x10 0x23 0x28 0x4f
+
+# CHECK: vinshvrx 1, 3, 5
+0x10 0x23 0x29 0x4f
+
+# CHECK: vinswvlx 1, 3, 5
+0x10 0x23 0x28 0x8f
+
+# CHECK: vinswvrx 1, 3, 5
+0x10 0x23 0x29 0x8f
+
+# CHECK: vinsblx 1, 2, 3
+0x10 0x22 0x1a 0x0f
+
+# CHECK: vinsbrx 1, 2, 3
+0x10 0x22 0x1b 0x0f
+
+# CHECK: vinshlx 1, 2, 3
+0x10 0x22 0x1a 0x4f
+
+# CHECK: vinshrx 1, 2, 3
+0x10 0x22 0x1b 0x4f
+
+# CHECK: vinswlx 1, 2, 3
+0x10 0x22 0x1a 0x8f
+
+# CHECK: vinswrx 1, 2, 3
+0x10 0x22 0x1b 0x8f
+
+# CHECK: vinsdlx 1, 2, 3
+0x10 0x22 0x1a 0xcf
+
+# CHECK: vinsdrx 1, 2, 3
+0x10 0x22 0x1b 0xcf
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -357,3 +357,51 @@
# CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56]
# CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10]
vsrdbi 2, 3, 4, 5
+# CHECK-BE: vinsw 2, 3, 12 # encoding: [0x10,0x4c,0x18,0xcf]
+# CHECK-LE: vinsw 2, 3, 12 # encoding: [0xcf,0x18,0x4c,0x10]
+ vinsw 2, 3, 12
+# CHECK-BE: vinsd 2, 3, 12 # encoding: [0x10,0x4c,0x19,0xcf]
+# CHECK-LE: vinsd 2, 3, 12 # encoding: [0xcf,0x19,0x4c,0x10]
+ vinsd 2, 3, 12
+# CHECK-BE: vinsbvlx 1, 3, 5 # encoding: [0x10,0x23,0x28,0x0f]
+# CHECK-LE: vinsbvlx 1, 3, 5 # encoding: [0x0f,0x28,0x23,0x10]
+ vinsbvlx 1, 3, 5
+# CHECK-BE: vinsbvrx 1, 3, 5 # encoding: [0x10,0x23,0x29,0x0f]
+# CHECK-LE: vinsbvrx 1, 3, 5 # encoding: [0x0f,0x29,0x23,0x10]
+ vinsbvrx 1, 3, 5
+# CHECK-BE: vinshvlx 1, 3, 5 # encoding: [0x10,0x23,0x28,0x4f]
+# CHECK-LE: vinshvlx 1, 3, 5 # encoding: [0x4f,0x28,0x23,0x10]
+ vinshvlx 1, 3, 5
+# CHECK-BE: vinshvrx 1, 3, 5 # encoding: [0x10,0x23,0x29,0x4f]
+# CHECK-LE: vinshvrx 1, 3, 5 # encoding: [0x4f,0x29,0x23,0x10]
+ vinshvrx 1, 3, 5
+# CHECK-BE: vinswvlx 1, 3, 5 # encoding: [0x10,0x23,0x28,0x8f]
+# CHECK-LE: vinswvlx 1, 3, 5 # encoding: [0x8f,0x28,0x23,0x10]
+ vinswvlx 1, 3, 5
+# CHECK-BE: vinswvrx 1, 3, 5 # encoding: [0x10,0x23,0x29,0x8f]
+# CHECK-LE: vinswvrx 1, 3, 5 # encoding: [0x8f,0x29,0x23,0x10]
+ vinswvrx 1, 3, 5
+# CHECK-BE: vinsblx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x0f]
+# CHECK-LE: vinsblx 1, 2, 3 # encoding: [0x0f,0x1a,0x22,0x10]
+ vinsblx 1, 2, 3
+# CHECK-BE: vinsbrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x0f]
+# CHECK-LE: vinsbrx 1, 2, 3 # encoding: [0x0f,0x1b,0x22,0x10]
+ vinsbrx 1, 2, 3
+# CHECK-BE: vinshlx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x4f]
+# CHECK-LE: vinshlx 1, 2, 3 # encoding: [0x4f,0x1a,0x22,0x10]
+ vinshlx 1, 2, 3
+# CHECK-BE: vinshrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x4f]
+# CHECK-LE: vinshrx 1, 2, 3 # encoding: [0x4f,0x1b,0x22,0x10]
+ vinshrx 1, 2, 3
+# CHECK-BE: vinswlx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x8f]
+# CHECK-LE: vinswlx 1, 2, 3 # encoding: [0x8f,0x1a,0x22,0x10]
+ vinswlx 1, 2, 3
+# CHECK-BE: vinswrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x8f]
+# CHECK-LE: vinswrx 1, 2, 3 # encoding: [0x8f,0x1b,0x22,0x10]
+ vinswrx 1, 2, 3
+# CHECK-BE: vinsdlx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0xcf]
+# CHECK-LE: vinsdlx 1, 2, 3 # encoding: [0xcf,0x1a,0x22,0x10]
+ vinsdlx 1, 2, 3
+# CHECK-BE: vinsdrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xcf]
+# CHECK-LE: vinsdrx 1, 2, 3 # encoding: [0xcf,0x1b,0x22,0x10]
+ vinsdrx 1, 2, 3