This is an archive of the discontinued LLVM Phabricator instance.

[AArch64][SVE] Add FP unpredicated to predicated two-op codegen
AbandonedPublic

Authored by dancgr on Jul 2 2020, 6:26 AM.

Details

Summary

This patch changes the predicated fmin, fmax, fminnm, fmaxnm from intrinsics to custom ISD nodes for lowering. These custom ISD nodes are then used to lower unpredicated versions of those instructions to be lowered to predicated ones.

I initially created an unpredicated intrinsic for this, because I didn't find any other way of generating the unpredicated fmin, fmax, etc. So I would appreciate any suggestions as to how to generate those unpredicated instructions without having to add more intrinsics.

Diff Detail

Event Timeline

dancgr created this revision.Jul 2 2020, 6:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 2 2020, 6:26 AM

I initially created an unpredicated intrinsic for this, because I didn't find any other way of generating the unpredicated fmin, fmax, etc. So I would appreciate any suggestions as to how to generate those unpredicated instructions without having to add more intrinsics.

I might be missing the motivation for the unpredicated intrinsic, but in the non-scalable world an unpredicated operation would be canonicalized as a predicated intrinsic with all-1s mask. That would then be lowered during ISel. Something like:

%mask = shufflevector <vscale x 4 x i1> 1, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
%res = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(
  <vscale x 4 x i1> %mask
  <vscale x 4 x float> %a,
  <vscale x 4 x float> %b)

X86 does something similar in X86ISelLowering.cpp:getVectorMaskingNode(...), although it's not really apples-to-apples since X86's masks are represented differently.

llvm/include/llvm/IR/IntrinsicsAArch64.td
1749

Unnecessary whitespace change?

There are a couple of these in this patch.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
1579

Was this #undef intentionally removed?

11909

This looks good, but it may be table-worthy, if this is the way forward. X86 does something similar in llvm/lib/Target/X86/X86IntrinsicsInfo.h. Just a heads up.

dancgr abandoned this revision.Jul 13 2020, 11:04 AM