diff --git a/llvm/test/TableGen/ContextlessPredicates.td b/llvm/test/TableGen/ContextlessPredicates.td
new file mode 100644
--- /dev/null
+++ b/llvm/test/TableGen/ContextlessPredicates.td
@@ -0,0 +1,73 @@
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
+// RUN: FileCheck %s --check-prefixes=CHECK_NOPT -input-file=%T/context-non-optimized.cpp
+//
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/context-optimized.cpp
+// RUN: FileCheck %s --check-prefixes=CHECK_OPT -input-file=%T/context-optimized.cpp
+
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+def test_atomic_op_frag : PatFrag<(ops node:$ptr, node:$val),
+	                                             (atomic_swap node:$ptr, node:$val)> {
+  let GISelPredicateCode = [{ dbgs() <<  return !MRI.use_nodbg_empty(MI.getOperand(0).getReg()); }];
+  let IsAtomic = 1;
+  let MemoryVT = i32;
+}
+ 
+def INSN : I<(outs GPR32:$dst), (ins GPR32Op:$src1, GPR32Op:$src2), []>;
+
+def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) ,
+	      (INSN GPR32:$ptr, GPR32:$val)>;
+
+// CHECK_NOPT-LABEL: const int64_t *MyTargetInstructionSelector::getMatchTable() const {
+// CHECK_NOPT-NEXT:   constexpr static int64_t MatchTable0[] = {
+// CHECK_NOPT-NEXT:   GIM_Try, /*On fail goto*//*Label 0*/ 46, // Rule ID 0 //
+// CHECK_NOPT-NEXT:     GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
+// CHECK_NOPT-NEXT:     GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_XCHG,
+// CHECK_NOPT-NEXT:     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_test_atomic_op_frag,
+// CHECK_NOPT-NEXT:     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+// CHECK_NOPT-NEXT:     // MIs[0] dst
+// CHECK_NOPT-NEXT:     GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+// CHECK_NOPT-NEXT:     GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK_NOPT-NEXT:     // MIs[0] ptr
+// CHECK_NOPT-NEXT:     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+// CHECK_NOPT-NEXT:     GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK_NOPT-NEXT:     // MIs[0] val
+// CHECK_NOPT-NEXT:     GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK_NOPT-NEXT:     GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK_NOPT-NEXT:     // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>>  =>  (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)
+// CHECK_NOPT-NEXT:     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN,
+// CHECK_NOPT-NEXT:     GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK_NOPT-NEXT:     // GIR_Coverage, 0,
+// CHECK_NOPT-NEXT:     GIR_Done,
+// CHECK_NOPT-NEXT:   // Label 0: @46
+// CHECK_NOPT-NEXT:   GIM_Reject,
+// CHECK_NOPT-NEXT:         };
+// CHECK_NOPT-NEXT:  return MatchTable0;
+// CHECK_NOPT-NEXT: }
+//
+//
+// CHECK_OPT-LABEL: const int64_t *MyTargetInstructionSelector::getMatchTable() const {
+// CHECK_OPT-NEXT:  constexpr static int64_t MatchTable0[] = {
+// CHECK_OPT-NEXT:    GIM_Try, /*On fail goto*//*Label 0*/ 43, // Rule ID 0 //
+// CHECK_OPT-NEXT:      GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_XCHG,
+// CHECK_OPT-NEXT:      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+// CHECK_OPT-NEXT:      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK_OPT-NEXT:      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_test_atomic_op_frag,
+// CHECK_OPT-NEXT:      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+// CHECK_OPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK_OPT-NEXT:      // MIs[0] ptr
+// CHECK_OPT-NEXT:      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+// CHECK_OPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK_OPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK_OPT-NEXT:      // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>>  =>  (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)
+// CHECK_OPT-NEXT:      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN,
+// CHECK_OPT-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK_OPT-NEXT:      // GIR_Coverage, 0,
+// CHECK_OPT-NEXT:      GIR_Done,
+// CHECK_OPT-NEXT:    // Label 0: @43
+// CHECK_OPT-NEXT:    GIM_Reject,
+// CHECK_OPT-NEXT:    };
+// CHECK_OPT-NEXT:  return MatchTable0;
+// CHECK_OPT-NEXT: } 
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -3561,6 +3561,7 @@
 
   for (const TreePredicateCall &Call : Src->getPredicateCalls()) {
     const TreePredicateFn &Predicate = Call.Fn;
+    bool HasPredicateCode = false;
     if (Predicate.isAlwaysTrue())
       continue;
 
@@ -3569,6 +3570,11 @@
       continue;
     }
 
+    if (Predicate.hasGISelPredicateCode()) {
+      HasPredicateCode = true;
+      InsnMatcher.addPredicate<GenericInstructionPredicateMatcher>(Predicate);
+    }
+
     // An address space check is needed in all contexts if there is one.
     if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) {
       if (const ListInit *AddrSpaces = Predicate.getAddressSpaces()) {
@@ -3705,14 +3711,9 @@
         continue;
       }
     }
-
-    if (Predicate.hasGISelPredicateCode()) {
-      InsnMatcher.addPredicate<GenericInstructionPredicateMatcher>(Predicate);
-      continue;
-    }
-
-    return failedImport("Src pattern child has predicate (" +
-                        explainPredicates(Src) + ")");
+    if (!HasPredicateCode)
+      return failedImport("Src pattern child has predicate (" +
+                          explainPredicates(Src) + ")");
   }
   if (SrcGIEquivOrNull && SrcGIEquivOrNull->getValueAsBit("CheckMMOIsNonAtomic"))
     InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("NotAtomic");