[CodeGen] Fix warnings in sve-vector-splat.ll and sve-trunc.ll

[david-arm]

Summary

This patch fixes all remaining warnings in:

llvm/test/CodeGen/AArch64/sve-trunc.ll
llvm/test/CodeGen/AArch64/sve-vector-splat.ll

I hit some warnings related to getCopyPartsToVector. I fixed two
issues:

1. In widenVectorToPartType() we assumed that we'd always be

using BUILD_VECTOR nodes to expand from one vector type to another,
which is incorrect for scalable vector types. I've fixed this for now
by simply bailing out immediately for scalable vectors.

2. In getCopyToPartsVector() I've changed the code to compare

the element counts of different types.

[fpetrogalli]

LGTM, thank you.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
   }
 
   if (DAG.getDataLayout().isBigEndian())
     std::reverse(Parts, Parts + OrigNumParts);
 }
 
 static SDValue widenVectorToPartType(SelectionDAG &DAG,
                                      SDValue Val, const SDLoc &DL, EVT PartVT) {
-  if (!PartVT.isVector())
+  if (!PartVT.isFixedLengthVector())
     return SDValue();
 
   EVT ValueVT = Val.getValueType();
   unsigned PartNumElts = PartVT.getVectorNumElements();
   unsigned ValueNumElts = ValueVT.getVectorNumElements();
   if (PartNumElts > ValueNumElts &&
       PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
     EVT ElementVT = PartVT.getVectorElementType();
if (PartEVT == ValueVT) {
       // Nothing to do.
     } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
       // Bitconvert vector->vector case.
       Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
     } else if (SDValue Widened = widenVectorToPartType(DAG, Val, DL, PartVT)) {
       Val = Widened;
     } else if (PartVT.isVector() &&
                PartEVT.getVectorElementType().bitsGE(
                    ValueVT.getVectorElementType()) &&
-               PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
+               PartEVT.getVectorElementCount() ==
+                   ValueVT.getVectorElementCount()) {
 
       // Promoted vector extract
       Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
     } else {
       if (ValueVT.getVectorNumElements() == 1) {
         Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
                           DAG.getVectorIdxConstant(0, DL));
       } else {

llvm/test/CodeGen/AArch64/sve-trunc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; WARN-NOT: warning
 
 ; For all the functions below should the operation is a nop
 define <vscale x 8 x i8> @trunc_i16toi8(<vscale x 8 x i16> %in) {
 ; CHECK-LABEL: trunc_i16toi8:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ret
 entry:
   %out = trunc <vscale x 8 x i16> %in to <vscale x 8 x i8>

llvm/test/CodeGen/AArch64/sve-vector-splat.ll

-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; WARN-NOT: warning
 
 ;; Splats of legal integer vector types
 
 define <vscale x 16 x i8> @sve_splat_16xi8(i8 %val) {
 ; CHECK-LABEL: @sve_splat_16xi8
 ; CHECK: mov z0.b, w0
 ; CHECK-NEXT: ret
   %ins = insertelement <vscale x 16 x i8> undef, i8 %val, i32 0