Index: test/TableGen/AsmPredicateCondsEmission.td =================================================================== --- /dev/null +++ test/TableGen/AsmPredicateCondsEmission.td @@ -0,0 +1,31 @@ +// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s + +// Check that we don't generate invalid code of the form "( && Cond2)" when +// emitting AssemblerPredicate conditions. In the example below, the invalid +// code would be: "return ( && (Bits & arch::AssemblerCondition2));". + +include "llvm/Target/Target.td" + +def archInstrInfo : InstrInfo { } + +def arch : Target { + let InstructionSet = archInstrInfo; +} + +def Pred1 : Predicate<"Condition1">; +def Pred2 : Predicate<"Condition2">, + AssemblerPredicate<"AssemblerCondition2">; + +def foo : Instruction { + let Size = 2; + let OutOperandList = (outs); + let InOperandList = (ins); + field bits<16> Inst; + let Inst = 0xAAAA; + let AsmString = "foo"; + field bits<16> SoftFail = 0; + // This is the important bit: + let Predicates = [Pred1, Pred2]; +} + +// CHECK: return ((Bits & arch::AssemblerCondition2)); Index: utils/TableGen/FixedLenDecoderEmitter.cpp =================================================================== --- utils/TableGen/FixedLenDecoderEmitter.cpp +++ utils/TableGen/FixedLenDecoderEmitter.cpp @@ -1112,6 +1112,7 @@ unsigned Opc) const { ListInit *Predicates = AllInstructions[Opc]->TheDef->getValueAsListInit("Predicates"); + bool IsFirstEmission = true; for (unsigned i = 0; i < Predicates->getSize(); ++i) { Record *Pred = Predicates->getElementAsRecord(i); if (!Pred->getValue("AssemblerMatcherPredicate")) @@ -1122,7 +1123,7 @@ if (!P.length()) continue; - if (i != 0) + if (!IsFirstEmission) o << " && "; StringRef SR(P); @@ -1133,6 +1134,7 @@ pairs = pairs.second.split(','); } emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace); + IsFirstEmission = false; } return Predicates->getSize() > 0; }