diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -2081,8 +2081,8 @@ const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo(); unsigned Size = TRI.getSpillSize(RC); - unsigned Align = TRI.getSpillAlignment(RC); - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false)); + Align Alignment = TRI.getSpillAlign(RC); + RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); // Might we have over-aligned allocas? bool HasAlVars = @@ -2090,8 +2090,8 @@ // These kinds of spills might need two registers. if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false)); - + RS->addScavengingFrameIndex( + MFI.CreateStackObject(Size, Alignment, false)); } } diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1389,25 +1389,24 @@ /// getMaxByValAlign - Helper for getByValTypeAlignment to determine /// the desired ByVal argument alignment. -static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign, - unsigned MaxMaxAlign) { +static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) { if (MaxAlign == MaxMaxAlign) return; if (VectorType *VTy = dyn_cast(Ty)) { if (MaxMaxAlign >= 32 && VTy->getPrimitiveSizeInBits().getFixedSize() >= 256) - MaxAlign = 32; + MaxAlign = Align(32); else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 && MaxAlign < 16) - MaxAlign = 16; + MaxAlign = Align(16); } else if (ArrayType *ATy = dyn_cast(Ty)) { - unsigned EltAlign = 0; + Align EltAlign; getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign); if (EltAlign > MaxAlign) MaxAlign = EltAlign; } else if (StructType *STy = dyn_cast(Ty)) { for (auto *EltTy : STy->elements()) { - unsigned EltAlign = 0; + Align EltAlign; getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign); if (EltAlign > MaxAlign) MaxAlign = EltAlign; @@ -1423,10 +1422,10 @@ const DataLayout &DL) const { // 16byte and wider vectors are passed on 16byte boundary. // The rest is 8 on PPC64 and 4 on PPC32 boundary. - unsigned Align = Subtarget.isPPC64() ? 8 : 4; + Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); if (Subtarget.hasAltivec() || Subtarget.hasQPX()) - getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16); - return Align; + getMaxByValAlign(Ty, Alignment, Subtarget.hasQPX() ? Align(32) : Align(16)); + return Alignment.value(); } bool PPCTargetLowering::useSoftFloat() const { diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -71,14 +71,14 @@ const char *ES; MCSymbol *MCSym; int JT; - unsigned Align; // CP alignment. + Align Alignment; // CP alignment. unsigned char SymbolFlags; // X86II::MO_* bool NegateIndex = false; X86ISelAddressMode() : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr), - MCSym(nullptr), JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {} + MCSym(nullptr), JT(-1), SymbolFlags(X86II::MO_NO_FLAG) {} bool hasSymbolicDisplacement() const { return GV != nullptr || CP != nullptr || ES != nullptr || @@ -144,7 +144,7 @@ dbgs() << MCSym; else dbgs() << "nul"; - dbgs() << " JT" << JT << " Align" << Align << '\n'; + dbgs() << " JT" << JT << " Align" << Alignment.value() << '\n'; } #endif }; @@ -296,7 +296,7 @@ MVT::i32, AM.Disp, AM.SymbolFlags); else if (AM.CP) - Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, Align(AM.Align), + Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Alignment, AM.Disp, AM.SymbolFlags); else if (AM.ES) { assert(!AM.Disp && "Non-zero displacement is ignored with ES."); @@ -1622,7 +1622,7 @@ Offset = G->getOffset(); } else if (ConstantPoolSDNode *CP = dyn_cast(N0)) { AM.CP = CP->getConstVal(); - AM.Align = CP->getAlign().value(); + AM.Alignment = CP->getAlign(); AM.SymbolFlags = CP->getTargetFlags(); Offset = CP->getOffset(); } else if (ExternalSymbolSDNode *S = dyn_cast(N0)) { diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2187,20 +2187,20 @@ /// Helper for getByValTypeAlignment to determine /// the desired ByVal argument alignment. -static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { +static void getMaxByValAlign(Type *Ty, Align &MaxAlign) { if (MaxAlign == 16) return; if (VectorType *VTy = dyn_cast(Ty)) { if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128) - MaxAlign = 16; + MaxAlign = Align(16); } else if (ArrayType *ATy = dyn_cast(Ty)) { - unsigned EltAlign = 0; + Align EltAlign; getMaxByValAlign(ATy->getElementType(), EltAlign); if (EltAlign > MaxAlign) MaxAlign = EltAlign; } else if (StructType *STy = dyn_cast(Ty)) { for (auto *EltTy : STy->elements()) { - unsigned EltAlign = 0; + Align EltAlign; getMaxByValAlign(EltTy, EltAlign); if (EltAlign > MaxAlign) MaxAlign = EltAlign; @@ -2218,16 +2218,16 @@ const DataLayout &DL) const { if (Subtarget.is64Bit()) { // Max of 8 and alignment of type. - unsigned TyAlign = DL.getABITypeAlignment(Ty); + Align TyAlign = DL.getABITypeAlign(Ty); if (TyAlign > 8) - return TyAlign; + return TyAlign.value(); return 8; } - unsigned Align = 4; + Align Alignment(4); if (Subtarget.hasSSE1()) - getMaxByValAlign(Ty, Align); - return Align; + getMaxByValAlign(Ty, Alignment); + return Alignment.value(); } /// It returns EVT::Other if the type should be determined using generic @@ -30956,7 +30956,7 @@ MachineOperand &Segment = MI.getOperand(5); unsigned ArgSize = MI.getOperand(6).getImm(); unsigned ArgMode = MI.getOperand(7).getImm(); - unsigned Align = MI.getOperand(8).getImm(); + Align Alignment = Align(MI.getOperand(8).getImm()); MachineFunction *MF = MBB->getParent(); @@ -30996,7 +30996,7 @@ /* Align ArgSize to a multiple of 8 */ unsigned ArgSizeA8 = (ArgSize + 7) & ~7; - bool NeedsAlign = (Align > 8); + bool NeedsAlign = (Alignment > 8); MachineBasicBlock *thisMBB = MBB; MachineBasicBlock *overflowMBB; @@ -31144,17 +31144,16 @@ // to OverflowDestReg. if (NeedsAlign) { // Align the overflow address - assert(isPowerOf2_32(Align) && "Alignment must be a power of 2"); Register TmpReg = MRI.createVirtualRegister(AddrRegClass); // aligned_addr = (addr + (align-1)) & ~(align-1) BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) - .addReg(OverflowAddrReg) - .addImm(Align-1); + .addReg(OverflowAddrReg) + .addImm(Alignment.value() - 1); BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) - .addReg(TmpReg) - .addImm(~(uint64_t)(Align-1)); + .addReg(TmpReg) + .addImm(~(uint64_t)(Alignment.value() - 1)); } else { BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) .addReg(OverflowAddrReg); diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -575,9 +575,9 @@ // When using SP for large frames, we may need 2 scratch registers. // When using FP, for large or small frames, we may need 1 scratch register. unsigned Size = TRI.getSpillSize(RC); - unsigned Align = TRI.getSpillAlignment(RC); + Align Alignment = TRI.getSpillAlign(RC); if (XFI->isLargeFrame(MF) || hasFP(MF)) - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false)); + RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); if (XFI->isLargeFrame(MF) && !hasFP(MF)) - RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false)); + RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Alignment, false)); } diff --git a/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp b/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp --- a/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp @@ -70,9 +70,9 @@ const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); unsigned Size = TRI.getSpillSize(RC); - unsigned Align = TRI.getSpillAlignment(RC); - EHSpillSlot[0] = MFI.CreateStackObject(Size, Align, true); - EHSpillSlot[1] = MFI.CreateStackObject(Size, Align, true); + Align Alignment = TRI.getSpillAlign(RC); + EHSpillSlot[0] = MFI.CreateStackObject(Size, Alignment, true); + EHSpillSlot[1] = MFI.CreateStackObject(Size, Alignment, true); EHSpillSlotSet = true; return EHSpillSlot; }