Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1695,6 +1695,15 @@
       if (!RC) {
         // This is a generic virtual register.
 
+        // Do not allow undef uses for generic virtual registers. This ensures
+        // getVRegDef can never fail and return null on a generic register.
+        //
+        // FIXME: This restriction should probably be broadened to all SSA
+        // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
+        // run on the SSA function just before phi elimination.
+        if (MO->isUndef() && MRI->isSSA())
+          report("Generic virtual register use cannot be undef", MO, MONum);
+
         // If we're post-Select, we can't have gvregs anymore.
         if (isFunctionSelected) {
           report("Generic virtual register invalid in a Selected function",
Index: llvm/test/MachineVerifier/generic-vreg-undef-use.mir
===================================================================
--- /dev/null
+++ llvm/test/MachineVerifier/generic-vreg-undef-use.mir
@@ -0,0 +1,25 @@
+# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+# Undef uses are illegal for generic vregs.
+
+---
+name:            test_undef_use
+liveins:
+body:             |
+  bb.0:
+    %0:_(s32) = G_CONSTANT i32 0
+
+    ; Test generic instruction
+    ; CHECK: *** Bad machine code: Generic virtual register use cannot be undef ***
+    G_STORE %0, undef %1:_(p0) :: (store 4)
+
+    ; Make sure this fails on a post-isel generic instruction.
+    ; CHECK: *** Bad machine code: Generic virtual register use cannot be undef ***
+    $x0 = COPY undef %2:_(s64)
+
+    ; Make sure this fails with a target instruction
+    ; CHECK: *** Bad machine code: Generic virtual register use cannot be undef ***
+    RET_ReallyLR implicit $x0, implicit undef %3:_(s32)
+...
+