Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -32448,12 +32448,17 @@
   MBB->addSuccessor(checkSspMBB);
 
   // Initialize a register with zero.
-  Register ZReg = MRI.createVirtualRegister(PtrRC);
-  unsigned XorRROpc = (PVT == MVT::i64) ? X86::XOR64rr : X86::XOR32rr;
-  BuildMI(checkSspMBB, DL, TII->get(XorRROpc))
-      .addDef(ZReg)
-      .addReg(ZReg, RegState::Undef)
-      .addReg(ZReg, RegState::Undef);
+  Register ZReg = MRI.createVirtualRegister(&X86::GR32RegClass);
+  BuildMI(checkSspMBB, DL, TII->get(X86::MOV32r0), ZReg);
+
+  if (PVT == MVT::i64) {
+    Register TmpZReg = MRI.createVirtualRegister(PtrRC);
+    BuildMI(checkSspMBB, DL, TII->get(X86::SUBREG_TO_REG), TmpZReg)
+      .addImm(0)
+      .addReg(ZReg)
+      .addImm(X86::sub_32bit);
+    ZReg = TmpZReg;
+  }
 
   // Read the current SSP Register value to the zeroed register.
   Register SSPCopyReg = MRI.createVirtualRegister(PtrRC);
Index: llvm/test/CodeGen/X86/shadow-stack.ll
===================================================================
--- llvm/test/CodeGen/X86/shadow-stack.ll
+++ llvm/test/CodeGen/X86/shadow-stack.ll
@@ -38,7 +38,7 @@
 ; X86_64-NEXT:    .cfi_offset %rbp, -16
 ; X86_64-NEXT:    movq _buf@{{.*}}(%rip), %rax
 ; X86_64-NEXT:    movq (%rax), %rax
-; X86_64-NEXT:    xorq %rdx, %rdx
+; X86_64-NEXT:    xorl %edx, %edx
 ; X86_64-NEXT:    rdsspq %rdx
 ; X86_64-NEXT:    testq %rdx, %rdx
 ; X86_64-NEXT:    je LBB0_5