Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3330,7 +3330,7 @@
 // containing zero.
 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
   // If we're not using isel, then this does not matter.
-  if (!PPCSubTarget->hasISEL())
+  if (!PPCSubTarget->hasISEL() || !PPCSubTarget->useISELRatherThanBranches())
     return false;
 
   for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8296,10 +8296,11 @@
 
   MachineFunction *F = BB->getParent();
 
-  if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
-                              MI->getOpcode() == PPC::SELECT_CC_I8 ||
-                              MI->getOpcode() == PPC::SELECT_I4 ||
-                              MI->getOpcode() == PPC::SELECT_I8)) {
+  if (Subtarget.hasISEL() && Subtarget.useISELRatherThanBranches() &&
+      (MI->getOpcode() == PPC::SELECT_CC_I4 ||
+       MI->getOpcode() == PPC::SELECT_CC_I8 ||
+       MI->getOpcode() == PPC::SELECT_I4 ||
+       MI->getOpcode() == PPC::SELECT_I8)) {
     SmallVector<MachineOperand, 2> Cond;
     if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
         MI->getOpcode() == PPC::SELECT_CC_I8)
Index: lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.cpp
+++ lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -596,7 +596,7 @@
                 const SmallVectorImpl<MachineOperand> &Cond,
                 unsigned TrueReg, unsigned FalseReg,
                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
-  if (!Subtarget.hasISEL())
+  if (!Subtarget.hasISEL() || !Subtarget.useISELRatherThanBranches())
     return false;
 
   if (Cond.size() != 2)
@@ -643,6 +643,9 @@
   assert(Subtarget.hasISEL() &&
          "Cannot insert select on target without ISEL support");
 
+  assert(Subtarget.useISELRatherThanBranches() &&
+         "Should not insert select when not recommended for the target");
+
   // Get the register classes.
   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =
Index: lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.h
+++ lib/Target/PowerPC/PPCSubtarget.h
@@ -261,7 +261,19 @@
   bool isSVR4ABI() const { return !isDarwinABI(); }
   bool isELFv2ABI() const;
 
-  bool enableEarlyIfConversion() const override { return hasISEL(); }
+  // For P7 and P8, using branches is almost always better than using select.
+  // The decision outcome must be almost completely random for isel to win,
+  // otherwise the branch predictor can predict the outcome. Also isel has a
+  // non-trivial latency for those subtargets.
+  bool useISELRatherThanBranches() const {
+    return HasISEL &&
+           DarwinDirective != PPC::DIR_PWR7 &&
+           DarwinDirective != PPC::DIR_PWR8;
+  }
+
+  bool enableEarlyIfConversion() const override {
+    return useISELRatherThanBranches();
+  }
 
   // Scheduling customization.
   bool enableMachineScheduler() const override;
Index: test/CodeGen/PowerPC/crbit-asm.ll
===================================================================
--- test/CodeGen/PowerPC/crbit-asm.ll
+++ test/CodeGen/PowerPC/crbit-asm.ll
@@ -15,8 +15,8 @@
 ; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], 1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
+; CHECK-DAG: bclr {{[0-9]+}}, [[REG3]], 0
+; CHECK-DAG: li 3, 0
 ; CHECK: blr
 }
 
@@ -34,8 +34,8 @@
 ; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], -1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
+; CHECK-DAG: bclr {{[0-9]+}}, [[REG3]], 0
+; CHECK-DAG: li 3, 0
 ; CHECK: blr
 }
 
@@ -50,8 +50,8 @@
 ; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], 1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
+; CHECK-DAG: bclr {{[0-9]+}}, [[REG3]], 0
+; CHECK-DAG: li 3, 0
 ; CHECK: blr
 }
 
Index: test/CodeGen/PowerPC/crbits.ll
===================================================================
--- test/CodeGen/PowerPC/crbits.ll
+++ test/CodeGen/PowerPC/crbits.ll
@@ -17,8 +17,9 @@
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
 ; CHECK: crnor
 ; CHECK: crnor
-; CHECK: crnand [[REG4:[0-9]+]],
-; CHECK: isel 3, 0, [[REG1]], [[REG4]]
+; CHECK: crand [[REG4:[0-9]+]],
+; CHECK: bclr {{[0-9]+}}, [[REG4]], 0
+; CHECK: li 3, 0
 ; CHECK: blr
 }
 
@@ -37,8 +38,9 @@
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
 ; CHECK: crnor
 ; CHECK: crnor
-; CHECK: creqv [[REG4:[0-9]+]],
-; CHECK: isel 3, 0, [[REG1]], [[REG4]]
+; CHECK: crxor [[REG4:[0-9]+]],
+; CHECK: bclr {{[0-9]+}}, [[REG4]], 0
+; CHECK: li 3, 0
 ; CHECK: blr
 }
 
@@ -60,8 +62,9 @@
 ; CHECK: crnor
 ; CHECK: crnor
 ; CHECK: crandc
-; CHECK: creqv [[REG4:[0-9]+]],
-; CHECK: isel 3, 0, [[REG1]], [[REG4]]
+; CHECK: crxor [[REG4:[0-9]+]],
+; CHECK: bclr {{[0-9]+}}, [[REG4]], 0
+; CHECK: li 3, 0
 ; CHECK: blr
 }
 
@@ -91,8 +94,9 @@
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
 ; CHECK-DAG: li [[REG3:[0-9]+]], 1
 ; CHECK-DAG: andi. {{[0-9]+}}, [[REG1]], 1
-; CHECK-DAG: crandc [[REG5:[0-9]+]],
-; CHECK: isel 3, 0, [[REG3]], [[REG5]]
+; CHECK-DAG: crorc [[REG5:[0-9]+]],
+; CHECK: bclr {{[0-9]+}}, [[REG5]], 0
+; CHECK: li 3, 0
 ; CHECK: blr
 }
 
@@ -111,8 +115,9 @@
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: crorc [[REG4:[0-9]+]], 1,
-; CHECK-DAG: crnand [[REG5:[0-9]+]], [[REG4]], [[REG1]]
-; CHECK: isel 3, 0, [[REG2]], [[REG5]]
+; CHECK-DAG: crand [[REG5:[0-9]+]], [[REG4]], [[REG1]]
+; CHECK: bclr {{[0-9]+}}, [[REG5]], 0
+; CHECK: li 3, 0
 ; CHECK: blr
 }
 
@@ -124,7 +129,7 @@
 
 ; CHECK-LABEL: @test7
 ; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK: isel 3, 4, 5, 1
+; CHECK: bc {{[0-9]+}}, 1
 ; CHECK: blr
 }
 
@@ -136,9 +141,9 @@
 
 ; CHECK-LABEL: @exttest7
 ; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 5
-; CHECK-DAG: li [[REG1:[0-9]+]], 8
-; CHECK-DAG: li [[REG2:[0-9]+]], 7
-; CHECK: isel 3, [[REG2]], [[REG1]],
+; CHECK-DAG: li 3, 7
+; CHECK: beqlr 0
+; CHECK-DAG: li 3, 8
 ; CHECK-NOT: rldicl
 ; CHECK: blr
 }
@@ -183,8 +188,9 @@
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
-; CHECK-DAG: crorc [[REG3:[0-9]+]],
-; CHECK: isel 3, 0, [[REG2]], [[REG3]]
+; CHECK-DAG: crandc [[REG3:[0-9]+]],
+; CHECK: bclr {{[0-9]+}}, [[REG3]], 0
+; CHECK: li 3, 0
 ; CHECK: blr
 }
 
Index: test/CodeGen/PowerPC/fold-zero.ll
===================================================================
--- test/CodeGen/PowerPC/fold-zero.ll
+++ test/CodeGen/PowerPC/fold-zero.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck -check-prefix=CHECK-CRB %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-CRB %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: test/CodeGen/PowerPC/i1-ext-fold.ll
===================================================================
--- test/CodeGen/PowerPC/i1-ext-fold.ll
+++ test/CodeGen/PowerPC/i1-ext-fold.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mcpu=a2 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: test/CodeGen/PowerPC/i64_fp_round.ll
===================================================================
--- test/CodeGen/PowerPC/i64_fp_round.ll
+++ test/CodeGen/PowerPC/i64_fp_round.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
+; RUN: llc -mcpu=a2 -mattr=-fpcvt < %s | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: test/CodeGen/PowerPC/ifcvt.ll
===================================================================
--- test/CodeGen/PowerPC/ifcvt.ll
+++ test/CodeGen/PowerPC/ifcvt.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: test/CodeGen/PowerPC/isel.ll
===================================================================
--- test/CodeGen/PowerPC/isel.ll
+++ test/CodeGen/PowerPC/isel.ll
@@ -1,7 +1,6 @@
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 ; RUN: llc -mcpu=a2 < %s | FileCheck %s
-; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
 
 define i64 @test1(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
Index: test/CodeGen/PowerPC/subreg-postra-2.ll
===================================================================
--- test/CodeGen/PowerPC/subreg-postra-2.ll
+++ test/CodeGen/PowerPC/subreg-postra-2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mcpu=a2 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: test/CodeGen/PowerPC/subreg-postra.ll
===================================================================
--- test/CodeGen/PowerPC/subreg-postra.ll
+++ test/CodeGen/PowerPC/subreg-postra.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mcpu=a2 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"