Index: llvm/lib/Target/ARM/MVETailPredication.cpp =================================================================== --- llvm/lib/Target/ARM/MVETailPredication.cpp +++ llvm/lib/Target/ARM/MVETailPredication.cpp @@ -107,11 +107,11 @@ private: /// Perform the relevant checks on the loop and convert if possible. - bool TryConvert(Value *TripCount); + bool TryConvert(Value *TripCount, const ARMSubtarget* ST); /// Return whether this is a vectorized loop, that contains masked /// load/stores. - bool IsPredicatedVectorLoop(); + bool IsPredicatedVectorLoop(const ARMSubtarget* ST); /// Perform checks on the arguments of @llvm.get.active.lane.mask /// intrinsic: check if the first is a loop induction variable, and for the @@ -235,7 +235,7 @@ LLVM_DEBUG(dbgs() << "ARM TP: Running on Loop: " << *L << *Setup << "\n" << *Decrement << "\n"); - if (!TryConvert(Setup->getArgOperand(0))) { + if (!TryConvert(Setup->getArgOperand(0), ST)) { LLVM_DEBUG(dbgs() << "ARM TP: Can't tail-predicate this loop.\n"); return false; } @@ -253,7 +253,7 @@ return VecTy; } -bool MVETailPredication::IsPredicatedVectorLoop() { +bool MVETailPredication::IsPredicatedVectorLoop(const ARMSubtarget* ST) { // Check that the loop contains at least one masked load/store intrinsic. // We only support 'normal' vector instructions - other than masked // load/stores. @@ -272,6 +272,13 @@ case Intrinsic::sadd_sat: case Intrinsic::uadd_sat: continue; + case Intrinsic::trunc: + case Intrinsic::rint: + case Intrinsic::round: + case Intrinsic::floor: + case Intrinsic::ceil: + if (ST->hasMVEFloatOps()) + continue; default: break; } @@ -593,8 +600,8 @@ << "ARM TP: Inserted VCTP: " << *VCTPCall << "\n"); } -bool MVETailPredication::TryConvert(Value *TripCount) { - if (!IsPredicatedVectorLoop()) { +bool MVETailPredication::TryConvert(Value *TripCount, const ARMSubtarget *ST) { + if (!IsPredicatedVectorLoop(ST)) { LLVM_DEBUG(dbgs() << "ARM TP: no masked instructions in loop.\n"); return false; } Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll @@ -0,0 +1,287 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -disable-mve-tail-predication=false -o - %s | FileCheck %s +define arm_aapcs_vfpcc void @round(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 { +; CHECK-LABEL: round: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: it eq +; CHECK-NEXT: popeq {r7, pc} +; CHECK-NEXT: dlstp.32 lr, r2 +; CHECK-NEXT: .LBB0_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q0, [r0], #16 +; CHECK-NEXT: vrinta.f32 q0, q0 +; CHECK-NEXT: vstrw.32 q0, [r1], #16 +; CHECK-NEXT: letp lr, .LBB0_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp5 = icmp eq i32 %n, 0 + br i1 %cmp5, label %for.cond.cleanup, label %vector.ph + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %next.gep = getelementptr float, float* %pSrcA, i32 %index + %next.gep14 = getelementptr float, float* %pDst, i32 %index + %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1) + %0 = bitcast float* %next.gep to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef) + %1 = call fast <4 x float> @llvm.round.v4f32(<4 x float> %wide.masked.load) + %2 = bitcast float* %next.gep14 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) + %index.next = add i32 %index, 4 + %3 = icmp eq i32 %index.next, %n.vec + br i1 %3, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @rint(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 { +; CHECK-LABEL: rint: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: it eq +; CHECK-NEXT: popeq {r7, pc} +; CHECK-NEXT: dlstp.32 lr, r2 +; CHECK-NEXT: .LBB1_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q0, [r0], #16 +; CHECK-NEXT: vrintx.f32 q0, q0 +; CHECK-NEXT: vstrw.32 q0, [r1], #16 +; CHECK-NEXT: letp lr, .LBB1_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp5 = icmp eq i32 %n, 0 + br i1 %cmp5, label %for.cond.cleanup, label %vector.ph + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %next.gep = getelementptr float, float* %pSrcA, i32 %index + %next.gep14 = getelementptr float, float* %pDst, i32 %index + %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1) + %0 = bitcast float* %next.gep to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef) + %1 = call fast <4 x float> @llvm.rint.v4f32(<4 x float> %wide.masked.load) + %2 = bitcast float* %next.gep14 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) + %index.next = add i32 %index, 4 + %3 = icmp eq i32 %index.next, %n.vec + br i1 %3, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @trunc(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 { +; CHECK-LABEL: trunc: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: it eq +; CHECK-NEXT: popeq {r7, pc} +; CHECK-NEXT: dlstp.32 lr, r2 +; CHECK-NEXT: .LBB2_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q0, [r0], #16 +; CHECK-NEXT: vrintz.f32 q0, q0 +; CHECK-NEXT: vstrw.32 q0, [r1], #16 +; CHECK-NEXT: letp lr, .LBB2_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp5 = icmp eq i32 %n, 0 + br i1 %cmp5, label %for.cond.cleanup, label %vector.ph + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %next.gep = getelementptr float, float* %pSrcA, i32 %index + %next.gep14 = getelementptr float, float* %pDst, i32 %index + %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1) + %0 = bitcast float* %next.gep to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef) + %1 = call fast <4 x float> @llvm.trunc.v4f32(<4 x float> %wide.masked.load) + %2 = bitcast float* %next.gep14 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) + %index.next = add i32 %index, 4 + %3 = icmp eq i32 %index.next, %n.vec + br i1 %3, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @ceil(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 { +; CHECK-LABEL: ceil: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: it eq +; CHECK-NEXT: popeq {r7, pc} +; CHECK-NEXT: dlstp.32 lr, r2 +; CHECK-NEXT: .LBB3_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q0, [r0], #16 +; CHECK-NEXT: vrintp.f32 q0, q0 +; CHECK-NEXT: vstrw.32 q0, [r1], #16 +; CHECK-NEXT: letp lr, .LBB3_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp5 = icmp eq i32 %n, 0 + br i1 %cmp5, label %for.cond.cleanup, label %vector.ph + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %next.gep = getelementptr float, float* %pSrcA, i32 %index + %next.gep14 = getelementptr float, float* %pDst, i32 %index + %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1) + %0 = bitcast float* %next.gep to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef) + %1 = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.masked.load) + %2 = bitcast float* %next.gep14 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) + %index.next = add i32 %index, 4 + %3 = icmp eq i32 %index.next, %n.vec + br i1 %3, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @floor(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 { +; CHECK-LABEL: floor: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: it eq +; CHECK-NEXT: popeq {r7, pc} +; CHECK-NEXT: dlstp.32 lr, r2 +; CHECK-NEXT: .LBB4_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q0, [r0], #16 +; CHECK-NEXT: vrintm.f32 q0, q0 +; CHECK-NEXT: vstrw.32 q0, [r1], #16 +; CHECK-NEXT: letp lr, .LBB4_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp5 = icmp eq i32 %n, 0 + br i1 %cmp5, label %for.cond.cleanup, label %vector.ph + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %next.gep = getelementptr float, float* %pSrcA, i32 %index + %next.gep14 = getelementptr float, float* %pDst, i32 %index + %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1) + %0 = bitcast float* %next.gep to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef) + %1 = call fast <4 x float> @llvm.floor.v4f32(<4 x float> %wide.masked.load) + %2 = bitcast float* %next.gep14 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask) + %index.next = add i32 %index, 4 + %3 = icmp eq i32 %index.next, %n.vec + br i1 %3, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +; nearbyint shouldn't be tail predicated because it's lowered into multiple instructions +define arm_aapcs_vfpcc void @nearbyint(i32* noalias nocapture %dst, float* noalias nocapture readonly %src, i32 %n) #0 { +; CHECK-LABEL: nearbyint: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: wls lr, r2, .LBB5_3 +; CHECK-NEXT: @ %bb.1: @ %while.body.preheader +; CHECK-NEXT: mov lr, r2 +; CHECK-NEXT: .LBB5_2: @ %while.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldr s0, [r1] +; CHECK-NEXT: adds r1, #4 +; CHECK-NEXT: vrintr.f32 s0, s0 +; CHECK-NEXT: vcvt.s32.f32 s0, s0 +; CHECK-NEXT: vmov r2, s0 +; CHECK-NEXT: str r2, [r0], #4 +; CHECK-NEXT: le lr, .LBB5_2 +; CHECK-NEXT: .LBB5_3: @ %while.end +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp3 = icmp eq i32 %n, 0 + br i1 %cmp3, label %while.end, label %while.body + +while.body: ; preds = %entry, %while.body + %n.addr.06 = phi i32 [ %dec, %while.body ], [ %n, %entry ] + %src.addr.05 = phi float* [ %incdec.ptr, %while.body ], [ %src, %entry ] + %dst.addr.04 = phi i32* [ %incdec.ptr2, %while.body ], [ %dst, %entry ] + %dec = add i32 %n.addr.06, -1 + %incdec.ptr = getelementptr inbounds float, float* %src.addr.05, i32 1 + %0 = load float, float* %src.addr.05, align 4 + %1 = tail call fast float @llvm.nearbyint.f32(float %0) + %conv1 = fptosi float %1 to i32 + %incdec.ptr2 = getelementptr inbounds i32, i32* %dst.addr.04, i32 1 + store i32 %conv1, i32* %dst.addr.04, align 4 + %cmp = icmp eq i32 %dec, 0 + br i1 %cmp, label %while.end, label %while.body + +while.end: ; preds = %while.body, %entry + ret void +} + +; Function Attrs: nounwind readnone speculatable willreturn +declare float @llvm.nearbyint.f32(float) #1 + +declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #1 + +declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2 + +declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #3 + +declare <4 x float> @llvm.rint.v4f32(<4 x float>) #3 + +declare <4 x float> @llvm.round.v4f32(<4 x float>) #3 + +declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #3 + +declare <4 x float> @llvm.floor.v4f32(<4 x float>) #3 + +declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>) #4