diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4173,7 +4173,11 @@
 bool ARMTargetLowering::splitValueIntoRegisterParts(
     SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
     unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
-  bool IsABIRegCopy = CC.hasValue();
+  bool IsABIRegCopy = false;
+  if (CC.hasValue()) {
+    auto CCVal = CC.getValue();
+    IsABIRegCopy = (CCVal != CallingConv::Fast);
+  }
   EVT ValueVT = Val.getValueType();
   if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
       PartVT == MVT::f32) {
@@ -4191,7 +4195,11 @@
 SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
     SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
     MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
-  bool IsABIRegCopy = CC.hasValue();
+  bool IsABIRegCopy = false;
+  if (CC.hasValue()) {
+    auto CCVal = CC.getValue();
+    IsABIRegCopy = (CCVal != CallingConv::Fast);
+  }
   if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
       PartVT == MVT::f32) {
     unsigned ValueBits = ValueVT.getSizeInBits();
diff --git a/llvm/test/CodeGen/ARM/arm-half-promote.ll b/llvm/test/CodeGen/ARM/arm-half-promote.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/arm-half-promote.ll
@@ -0,0 +1,8 @@
+; RUN: llc -mtriple=thumbv7s-apple-ios7.0.0 %s -o -
+
+target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-ios7.0.0"
+
+define fastcc { <8 x half>, <8 x half> } @f1() {
+  ret { <8 x half>, <8 x half> } zeroinitializer
+}