Index: llvm/lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -1748,7 +1748,7 @@
 
 // ldrd / strd pre / post variants
 
-let mayLoad = 1 in
+let mayLoad = 1, hasSideEffects = 0 in
 def t2LDRD_PRE  : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
                  (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
                  "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
@@ -1756,13 +1756,13 @@
   let DecoderMethod = "DecodeT2LDRDPreInstruction";
 }
 
-let mayLoad = 1 in
+let mayLoad = 1, hasSideEffects = 0 in
 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
                  (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
                  IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
                  "$addr.base = $wb", []>, Sched<[WriteLd]>;
 
-let mayStore = 1 in
+let mayStore = 1, hasSideEffects = 0 in
 def t2STRD_PRE  : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
                  (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
                  IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
@@ -1770,7 +1770,7 @@
   let DecoderMethod = "DecodeT2STRDPreInstruction";
 }
 
-let mayStore = 1 in
+let mayStore = 1, hasSideEffects = 0 in
 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
                  (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
                       t2am_imm8s4_offset:$imm),
@@ -2765,6 +2765,8 @@
   let Inst{25} = 1;
   let Inst{24-20} = 0b10100;
   let Inst{15} = 0;
+
+  let hasSideEffects = 0;
 }
 
 def t2UBFX: T2TwoRegBitFI<
@@ -2774,6 +2776,8 @@
   let Inst{25} = 1;
   let Inst{24-20} = 0b11100;
   let Inst{15} = 0;
+
+  let hasSideEffects = 0;
 }
 
 // A8.8.247  UDF - Undefined (Encoding T2)
Index: llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
+++ llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
@@ -913,11 +913,11 @@
 ; CHECK-NEXT:    vmov.16 q1[3], r1
 ; CHECK-NEXT:  .LBB18_9: @ %else8
 ; CHECK-NEXT:    vmrs r2, p0
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vmovx.f16 s0, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s3, s0
 ; CHECK-NEXT:    vmovx.f16 s8, s4
+; CHECK-NEXT:    vcvtb.f32.f16 s3, s0
 ; CHECK-NEXT:    vcvtb.f32.f16 s2, s5
-; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcvtb.f32.f16 s1, s8
 ; CHECK-NEXT:    vcvtb.f32.f16 s0, s4
 ; CHECK-NEXT:    and r3, r2, #1
@@ -1041,11 +1041,11 @@
 ; CHECK-NEXT:    vmov.16 q1[3], r1
 ; CHECK-NEXT:  .LBB19_9: @ %else8
 ; CHECK-NEXT:    vmrs r2, p0
+; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vmovx.f16 s0, s5
-; CHECK-NEXT:    vcvtb.f32.f16 s3, s0
 ; CHECK-NEXT:    vmovx.f16 s8, s4
+; CHECK-NEXT:    vcvtb.f32.f16 s3, s0
 ; CHECK-NEXT:    vcvtb.f32.f16 s2, s5
-; CHECK-NEXT:    movs r1, #0
 ; CHECK-NEXT:    vcvtb.f32.f16 s1, s8
 ; CHECK-NEXT:    vcvtb.f32.f16 s0, s4
 ; CHECK-NEXT:    and r3, r2, #1
Index: llvm/test/tools/llvm-mca/ARM/m4-int.s
===================================================================
--- llvm/test/tools/llvm-mca/ARM/m4-int.s
+++ llvm/test/tools/llvm-mca/ARM/m4-int.s
@@ -562,8 +562,8 @@
 # CHECK-NEXT:  1      2     1.00                  U     ldrbt	r0, [r1, #1]
 # CHECK-NEXT:  1      2     1.00    *                   ldrd	r0, r2, [r1]
 # CHECK-NEXT:  1      2     1.00    *                   ldrd	r0, r2, [r1, #-4]
-# CHECK-NEXT:  1      2     1.00    *             U     ldrd	r0, r2, [r1], #4
-# CHECK-NEXT:  1      2     1.00    *             U     ldrd	r0, r2, [r1, #4]!
+# CHECK-NEXT:  1      2     1.00    *                   ldrd	r0, r2, [r1], #4
+# CHECK-NEXT:  1      2     1.00    *                   ldrd	r0, r2, [r1, #4]!
 # CHECK-NEXT:  1      2     1.00    *                   ldrd	r0, r2, next
 # CHECK-NEXT:  1      2     1.00    *      *      U     ldrex	r0, [r1]
 # CHECK-NEXT:  1      2     1.00    *      *      U     ldrex	r0, [r1, #4]
@@ -700,7 +700,7 @@
 # CHECK-NEXT:  1      1     1.00                        sbcs.w	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        sbc.w	r0, r1, r2, lsl #1
 # CHECK-NEXT:  1      1     1.00                        sbcs.w	r0, r1, r2, lsl #1
-# CHECK-NEXT:  1      1     1.00                  U     sbfx	r0, r1, #1, #2
+# CHECK-NEXT:  1      1     1.00                        sbfx	r0, r1, #1, #2
 # CHECK-NEXT:  1      2     1.00                        sdiv	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00    *                   sel	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00    *      *      U     sev
@@ -778,8 +778,8 @@
 # CHECK-NEXT:  1      1     1.00           *            strb.w	r0, [r1, r2, lsl #1]
 # CHECK-NEXT:  1      1     1.00                  U     strbt	r0, [r1, #1]
 # CHECK-NEXT:  1      1     1.00           *            strd	r0, r1, [r2, #4]
-# CHECK-NEXT:  1      1     1.00           *      U     strd	r0, r1, [r2], #4
-# CHECK-NEXT:  1      1     1.00           *      U     strd	r0, r1, [r2, #4]!
+# CHECK-NEXT:  1      1     1.00           *            strd	r0, r1, [r2], #4
+# CHECK-NEXT:  1      1     1.00           *            strd	r0, r1, [r2, #4]!
 # CHECK-NEXT:  1      1     1.00    *      *      U     strex	r0, r1, [r2]
 # CHECK-NEXT:  1      1     1.00    *      *      U     strex	r0, r1, [r2, #4]
 # CHECK-NEXT:  1      1     1.00    *      *      U     strexb	r0, r1, [r2]
@@ -839,7 +839,7 @@
 # CHECK-NEXT:  1      1     1.00    *      *      U     uadd16	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00    *      *      U     uadd8	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00    *      *      U     uasx	r0, r1, r2
-# CHECK-NEXT:  1      1     1.00                  U     ubfx	r0, r1, #1, #2
+# CHECK-NEXT:  1      1     1.00                        ubfx	r0, r1, #1, #2
 # CHECK-NEXT:  1      2     1.00                        udiv	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        uhadd16	r0, r1, r2
 # CHECK-NEXT:  1      1     1.00                        uhadd8	r0, r1, r2