diff --git a/llvm/include/llvm/CodeGen/TargetCallingConv.h b/llvm/include/llvm/CodeGen/TargetCallingConv.h --- a/llvm/include/llvm/CodeGen/TargetCallingConv.h +++ b/llvm/include/llvm/CodeGen/TargetCallingConv.h @@ -59,7 +59,7 @@ : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsNest(0), IsReturned(0), IsSplit(0), IsInAlloca(0), IsPreallocated(0), IsSplitEnd(0), IsSwiftSelf(0), IsSwiftError(0), IsCFGuardTarget(0), - IsHva(0), IsHvaStart(0), IsSecArgPass(0), ByValAlign(0), OrigAlign(0), + IsHva(0), IsHvaStart(0), IsSecArgPass(0), ByValAlign(0), OrigAlign(1), IsInConsecutiveRegsLast(0), IsInConsecutiveRegs(0), IsCopyElisionCandidate(0), IsPointer(0), ByValSize(0), PointerAddrSpace(0) { @@ -144,13 +144,19 @@ assert(getNonZeroByValAlign() == A && "bitfield overflow"); } - unsigned getOrigAlign() const { + LLVM_ATTRIBUTE_DEPRECATED(unsigned getOrigAlign() const, + "Use getNonZeroOrigAlign() instead") { MaybeAlign A = decodeMaybeAlign(OrigAlign); return A ? A->value() : 0; } + Align getNonZeroOrigAlign() const { + MaybeAlign A = decodeMaybeAlign(OrigAlign); + assert(A && "OrigAlign must be defined"); + return *A; + } void setOrigAlign(Align A) { OrigAlign = encode(A); - assert(getOrigAlign() == A.value() && "bitfield overflow"); + assert(getNonZeroOrigAlign() == A && "bitfield overflow"); } unsigned getByValSize() const { return ByValSize; } diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp b/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp --- a/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp +++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.cpp @@ -42,7 +42,7 @@ unsigned Size = LocVT.getSizeInBits() / 8; const Align StackAlign = State.getMachineFunction().getDataLayout().getStackAlignment(); - const Align OrigAlign(ArgFlags.getOrigAlign()); + const Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); const Align Alignment = std::min(OrigAlign, StackAlign); for (auto &It : PendingMembers) { diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.td b/llvm/lib/Target/AArch64/AArch64CallingConvention.td --- a/llvm/lib/Target/AArch64/AArch64CallingConvention.td +++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.td @@ -10,9 +10,6 @@ // //===----------------------------------------------------------------------===// -/// CCIfAlign - Match of the original alignment of the arg -class CCIfAlign : - CCIf; /// CCIfBigEndian - Match only if we're in big endian mode. class CCIfBigEndian : CCIf<"State.getMachineFunction().getDataLayout().isBigEndian()", A>; diff --git a/llvm/lib/Target/ARM/ARMCallingConv.cpp b/llvm/lib/Target/ARM/ARMCallingConv.cpp --- a/llvm/lib/Target/ARM/ARMCallingConv.cpp +++ b/llvm/lib/Target/ARM/ARMCallingConv.cpp @@ -181,8 +181,8 @@ // aggregate. Store the type's required alignment as extra info for later: in // the [N x i64] case all trace has been removed by the time we actually get // to do allocation. - PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo, - ArgFlags.getOrigAlign())); + PendingMembers.push_back(CCValAssign::getPending( + ValNo, ValVT, LocVT, LocInfo, ArgFlags.getNonZeroOrigAlign().value())); if (!ArgFlags.isInConsecutiveRegsLast()) return true; diff --git a/llvm/lib/Target/ARM/ARMCallingConv.td b/llvm/lib/Target/ARM/ARMCallingConv.td --- a/llvm/lib/Target/ARM/ARMCallingConv.td +++ b/llvm/lib/Target/ARM/ARMCallingConv.td @@ -10,7 +10,7 @@ /// CCIfAlign - Match of the original alignment of the arg class CCIfAlign: - CCIf; + CCIf; //===----------------------------------------------------------------------===// // ARM APCS Calling Convention @@ -134,7 +134,7 @@ // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register // (and the same is true for f64 if VFP is not enabled) CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>, - CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8", + CCIfType<[i32], CCIf<"ArgFlags.getNonZeroOrigAlign() != Align(8)", CCAssignToReg<[R0, R1, R2, R3]>>>, CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>, diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -2908,8 +2908,8 @@ // argument which is not f32 or f64. bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || State.getFirstUnallocated(F32Regs) != ValNo; - unsigned OrigAlign = ArgFlags.getOrigAlign(); - bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); + Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); + bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8)); bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); // The MIPS vector ABI for floats passes them in a pair of registers @@ -2963,8 +2963,7 @@ llvm_unreachable("Cannot handle this ValVT."); if (!Reg) { - unsigned Offset = - State.AllocateStack(ValVT.getStoreSize(), Align(OrigAlign)); + unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); } else State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1492,10 +1492,11 @@ VA1.getLocVT(), CCValAssign::Full)); } else { // Both halves must be passed on the stack, with proper alignment. - unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign()); + Align StackAlign = + std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign()); State.addLoc( CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), - State.AllocateStack(XLenInBytes, Align(StackAlign)), + State.AllocateStack(XLenInBytes, StackAlign), VA1.getLocVT(), CCValAssign::Full)); State.addLoc(CCValAssign::getMem( ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), @@ -1579,7 +1580,7 @@ // original type is larger than 2*XLEN, so the register alignment rule does // not apply. unsigned TwoXLenInBytes = (2 * XLen) / 8; - if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes && + if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); // Skip 'odd' register if necessary. diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -841,7 +841,7 @@ assert(VT != MVT::iPTR && "Legalized args should be concrete"); Type *Ty = VT.getTypeForEVT(*DAG.getContext()); Align Alignment = - std::max(Align(Out.Flags.getOrigAlign()), Layout.getABITypeAlign(Ty)); + std::max(Out.Flags.getNonZeroOrigAlign(), Layout.getABITypeAlign(Ty)); unsigned Offset = CCInfo.AllocateStack(Layout.getTypeAllocSize(Ty), Alignment); CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(), @@ -915,7 +915,7 @@ if (In.Flags.isInConsecutiveRegsLast()) fail(DL, DAG, "WebAssembly hasn't implemented cons regs last return values"); - // Ignore In.getOrigAlign() because all our arguments are passed in + // Ignore In.getNonZeroOrigAlign() because all our arguments are passed in // registers. InTys.push_back(In.VT); } @@ -1002,7 +1002,7 @@ fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments"); if (In.Flags.isInConsecutiveRegsLast()) fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments"); - // Ignore In.getOrigAlign() because all our arguments are passed in + // Ignore In.getNonZeroOrigAlign() because all our arguments are passed in // registers. InVals.push_back(In.Used ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT, DAG.getTargetConstant(InVals.size(),