Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6900,6 +6900,29 @@
                              DAG.getZExtOrTrunc(Const, getCurSDLoc(), PtrVT)));
     return;
   }
+  case Intrinsic::get_active_lane_mask: {
+    auto DL = getCurSDLoc();
+    SDValue Index = getValue(I.getOperand(0));
+    SDValue BTC = getValue(I.getOperand(1));
+    EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
+    unsigned VecWidth = VT.getVectorNumElements();
+
+    SmallVector<SDValue, 16> OpsBTC;
+    SmallVector<SDValue, 16> OpsIndex;
+    for (unsigned i = 0; i < VecWidth; i++) {
+      OpsBTC.push_back(BTC);
+      OpsIndex.push_back(Index);
+    }
+
+    EVT CCVT = MVT::i1;
+    auto *VecTy = FixedVectorType::get(I.getOperand(0)->getType(), VecWidth);
+    SDValue VectorBTC = DAG.getBuildVector(MVT::getVT(VecTy), DL, OpsBTC);
+    SDValue VectorIndex = DAG.getBuildVector(MVT::getVT(VecTy), DL, OpsIndex);
+    CCVT = EVT::getVectorVT(I.getContext(), CCVT, VecWidth);
+    setValue(&I,
+        DAG.getSetCC(DL, CCVT, VectorIndex, VectorBTC, ISD::CondCode::SETULE));
+    return;
+  }
   }
 }
 
Index: llvm/test/CodeGen/Thumb2/active_lane_mask.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/active_lane_mask.ll
@@ -0,0 +1,122 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -o - | FileCheck %s
+
+define <4 x i32> @v4i32(i32 %index, i32 %BTC, <4 x i32> %V1, <4 x i32> %V2) {
+; CHECK-LABEL: v4i32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vdup.32 q0, r1
+; CHECK-NEXT:    vcmp.u32 cs, q0, r0
+; CHECK-NEXT:    vmov d0, r2, r3
+; CHECK-NEXT:    add r0, sp, #8
+; CHECK-NEXT:    vldr d1, [sp]
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    vpsel q0, q0, q1
+; CHECK-NEXT:    vmov r0, r1, d0
+; CHECK-NEXT:    vmov r2, r3, d1
+; CHECK-NEXT:    bx lr
+  %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %BTC)
+  %select = select <4 x i1> %active.lane.mask, <4 x i32> %V1, <4 x i32> %V2
+  ret <4 x i32> %select
+}
+
+define <8 x i16> @v8i16(i32 %index, i32 %BTC, <8 x i16> %V1, <8 x i16> %V2) {
+; CHECK-LABEL: v8i16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    push {r7, lr}
+; CHECK-NEXT:    vdup.32 q0, r1
+; CHECK-NEXT:    vmov.i8 q1, #0xff
+; CHECK-NEXT:    vcmp.u32 cs, q0, r0
+; CHECK-NEXT:    vmov.i8 q0, #0x0
+; CHECK-NEXT:    vpsel q1, q1, q0
+; CHECK-NEXT:    vmov r12, s4
+; CHECK-NEXT:    vmov.16 q0[0], r12
+; CHECK-NEXT:    vmov lr, s5
+; CHECK-NEXT:    vmov.16 q0[1], lr
+; CHECK-NEXT:    vmov r0, s6
+; CHECK-NEXT:    vmov.16 q0[2], r0
+; CHECK-NEXT:    vmov r1, s7
+; CHECK-NEXT:    vmov.16 q0[3], r1
+; CHECK-NEXT:    vmov.16 q0[4], r12
+; CHECK-NEXT:    vmov.16 q0[5], lr
+; CHECK-NEXT:    vmov.16 q0[6], r0
+; CHECK-NEXT:    add r0, sp, #16
+; CHECK-NEXT:    vmov.16 q0[7], r1
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    vcmp.i16 ne, q0, zr
+; CHECK-NEXT:    vmov d0, r2, r3
+; CHECK-NEXT:    vldr d1, [sp, #8]
+; CHECK-NEXT:    vpsel q0, q0, q1
+; CHECK-NEXT:    vmov r0, r1, d0
+; CHECK-NEXT:    vmov r2, r3, d1
+; CHECK-NEXT:    pop {r7, pc}
+  %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %BTC)
+  %select = select <8 x i1> %active.lane.mask, <8 x i16> %V1, <8 x i16> %V2
+  ret <8 x i16> %select
+}
+
+define <16 x i8> @v16i8(i32 %index, i32 %BTC, <16 x i8> %V1, <16 x i8> %V2) {
+; CHECK-LABEL: v16i8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
+; CHECK-NEXT:    sub sp, #4
+; CHECK-NEXT:    vdup.32 q0, r1
+; CHECK-NEXT:    vmov.i8 q1, #0xff
+; CHECK-NEXT:    vcmp.u32 cs, q0, r0
+; CHECK-NEXT:    vmov.i8 q0, #0x0
+; CHECK-NEXT:    vpsel q3, q1, q0
+; CHECK-NEXT:    vmov r12, s12
+; CHECK-NEXT:    vmov.16 q2[0], r12
+; CHECK-NEXT:    vmov lr, s13
+; CHECK-NEXT:    vmov.16 q2[1], lr
+; CHECK-NEXT:    vmov r0, s14
+; CHECK-NEXT:    vmov.16 q2[2], r0
+; CHECK-NEXT:    vmov r1, s15
+; CHECK-NEXT:    vmov.16 q2[3], r1
+; CHECK-NEXT:    vmov.16 q2[4], r12
+; CHECK-NEXT:    vmov.16 q2[5], lr
+; CHECK-NEXT:    vmov.16 q2[6], r0
+; CHECK-NEXT:    vmov.16 q2[7], r1
+; CHECK-NEXT:    vcmp.i16 ne, q2, zr
+; CHECK-NEXT:    vpsel q1, q1, q0
+; CHECK-NEXT:    vmov.u16 r12, q1[0]
+; CHECK-NEXT:    vmov.u16 lr, q1[1]
+; CHECK-NEXT:    vmov.8 q0[0], r12
+; CHECK-NEXT:    vmov.u16 r0, q1[2]
+; CHECK-NEXT:    vmov.8 q0[1], lr
+; CHECK-NEXT:    vmov.u16 r1, q1[3]
+; CHECK-NEXT:    vmov.8 q0[2], r0
+; CHECK-NEXT:    vmov.u16 r4, q1[4]
+; CHECK-NEXT:    vmov.8 q0[3], r1
+; CHECK-NEXT:    vmov.u16 r5, q1[5]
+; CHECK-NEXT:    vmov.8 q0[4], r4
+; CHECK-NEXT:    vmov.u16 r6, q1[6]
+; CHECK-NEXT:    vmov.8 q0[5], r5
+; CHECK-NEXT:    vmov.u16 r7, q1[7]
+; CHECK-NEXT:    vmov.8 q0[6], r6
+; CHECK-NEXT:    vmov.8 q0[7], r7
+; CHECK-NEXT:    vmov.8 q0[8], r12
+; CHECK-NEXT:    vmov.8 q0[9], lr
+; CHECK-NEXT:    vmov.8 q0[10], r0
+; CHECK-NEXT:    add r0, sp, #32
+; CHECK-NEXT:    vmov.8 q0[11], r1
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    vmov.8 q0[12], r4
+; CHECK-NEXT:    vmov.8 q0[13], r5
+; CHECK-NEXT:    vmov.8 q0[14], r6
+; CHECK-NEXT:    vmov.8 q0[15], r7
+; CHECK-NEXT:    vcmp.i8 ne, q0, zr
+; CHECK-NEXT:    vmov d0, r2, r3
+; CHECK-NEXT:    vldr d1, [sp, #24]
+; CHECK-NEXT:    vpsel q0, q0, q1
+; CHECK-NEXT:    vmov r0, r1, d0
+; CHECK-NEXT:    vmov r2, r3, d1
+; CHECK-NEXT:    add sp, #4
+; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
+  %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %BTC)
+  %select = select <16 x i1> %active.lane.mask, <16 x i8> %V1, <16 x i8> %V2
+  ret <16 x i8> %select
+}
+
+declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
+declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
+declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)