diff --git a/mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp b/mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp --- a/mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp +++ b/mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp @@ -72,7 +72,8 @@ auto dstType = this->typeConverter.convertType(operation.getType()); if (!dstType) return failure(); - rewriter.template replaceOpWithNewOp(operation, dstType, operands); + rewriter.template replaceOpWithNewOp(operation, dstType, operands, + operation.getAttrs()); return success(); } }; @@ -340,6 +341,8 @@ DirectConversionPattern, // Bitwise ops + DirectConversionPattern, + DirectConversionPattern, DirectConversionPattern, DirectConversionPattern, DirectConversionPattern, diff --git a/mlir/test/Conversion/SPIRVToLLVM/bitwise-ops-to-llvm.mlir b/mlir/test/Conversion/SPIRVToLLVM/bitwise-ops-to-llvm.mlir --- a/mlir/test/Conversion/SPIRVToLLVM/bitwise-ops-to-llvm.mlir +++ b/mlir/test/Conversion/SPIRVToLLVM/bitwise-ops-to-llvm.mlir @@ -1,6 +1,38 @@ // RUN: mlir-opt -convert-spirv-to-llvm %s | FileCheck %s //===----------------------------------------------------------------------===// +// spv.BitCount +//===----------------------------------------------------------------------===// + +func @bitcount_scalar(%arg0: i16) { + // CHECK: %{{.*}} = "llvm.intr.ctpop"(%{{.*}}) : (!llvm.i16) -> !llvm.i16 + %0 = spv.BitCount %arg0: i16 + return +} + +func @bitcount_vector(%arg0: vector<3xi32>) { + // CHECK: %{{.*}} = "llvm.intr.ctpop"(%{{.*}}) : (!llvm<"<3 x i32>">) -> !llvm<"<3 x i32>"> + %0 = spv.BitCount %arg0: vector<3xi32> + return +} + +//===----------------------------------------------------------------------===// +// spv.BitReverse +//===----------------------------------------------------------------------===// + +func @bitreverse_scalar(%arg0: i64) { + // CHECK: %{{.*}} = "llvm.intr.bitreverse"(%{{.*}}) : (!llvm.i64) -> !llvm.i64 + %0 = spv.BitReverse %arg0: i64 + return +} + +func @bitreverse_vector(%arg0: vector<4xi32>) { + // CHECK: %{{.*}} = "llvm.intr.bitreverse"(%{{.*}}) : (!llvm<"<4 x i32>">) -> !llvm<"<4 x i32>"> + %0 = spv.BitReverse %arg0: vector<4xi32> + return +} + +//===----------------------------------------------------------------------===// // spv.BitwiseAnd //===----------------------------------------------------------------------===//