Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -74,6 +74,32 @@
   EVT VT = Node->getValueType(0);
 
   switch (Opcode) {
+  // Optimize the node (add r, imm) to (addi (addi r, imm0) imm1)
+  // if possible.
+  case ISD::ADD: {
+    // The second operand must be an immediate.
+    if (auto ConstOp = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
+      // The immediate operand must not have other use.
+      if (!ConstOp->hasOneUse())
+        break;
+      // The immediate must be in range [-4095,-2049] or [2048,4094].
+      int64_t imm = ConstOp->getSExtValue();
+      if (imm < -4095 || (-2049 < imm && imm < 2048) || 4094 < imm)
+        break;
+      // Break the immediate to Imm0+Imm1.
+      SDLoc DL(Node);
+      EVT VT = Node->getValueType(0);
+      SDValue Imm0 = CurDAG->getTargetConstant(imm / 2, DL, VT);
+      SDValue Imm1 = CurDAG->getTargetConstant(imm - imm / 2, DL, VT);
+      auto Node0 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT,
+                                          Node->getOperand(0), Imm0);
+      auto Node1 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT,
+                                          SDValue(Node0, 0), Imm1);
+      ReplaceNode(Node, Node1);
+      return;
+    }
+    break;
+  }
   case ISD::Constant: {
     auto ConstNode = cast<ConstantSDNode>(Node);
     if (VT == XLenVT && ConstNode->isNullValue()) {
Index: llvm/test/CodeGen/RISCV/add-imm.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/add-imm.ll
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+; These test how the immediate in an addition is materialized.
+
+define i32 @add_0(i32 %a) nounwind {
+; RV32I-LABEL: add_0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 2047
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 2047
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, 2047
+  ret i32 %1
+}
+
+define i32 @add_1(i32 %a) nounwind {
+; RV32I-LABEL: add_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 1024
+; RV32I-NEXT:    addi a0, a0, 1024
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 1024
+; RV64I-NEXT:    addi a0, a0, 1024
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, 2048
+  ret i32 %1
+}
+
+define i32 @add_2(i32 %a) nounwind {
+; RV32I-LABEL: add_2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 2047
+; RV32I-NEXT:    addi a0, a0, 2047
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 2047
+; RV64I-NEXT:    addi a0, a0, 2047
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, 4094
+  ret i32 %1
+}
+
+define i32 @add_3(i32 %a) nounwind {
+; RV32I-LABEL: add_3:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, -1
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_3:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, -1
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, 4095
+  ret i32 %1
+}
+
+define i32 @add_4(i32 %a) nounwind {
+; RV32I-LABEL: add_4:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_4:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, -2048
+  ret i32 %1
+}
+
+define i32 @add_5(i32 %a) nounwind {
+; RV32I-LABEL: add_5:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, -1024
+; RV32I-NEXT:    addi a0, a0, -1025
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_5:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, -1024
+; RV64I-NEXT:    addi a0, a0, -1025
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, -2049
+  ret i32 %1
+}
+
+define i32 @add_6(i32 %a) nounwind {
+; RV32I-LABEL: add_6:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, -2047
+; RV32I-NEXT:    addi a0, a0, -2048
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_6:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, -2047
+; RV64I-NEXT:    addi a0, a0, -2048
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, -4095
+  ret i32 %1
+}
+
+define i32 @add_7(i32 %a) nounwind {
+; RV32I-LABEL: add_7:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1048575
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_7:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1048575
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, -4096
+  ret i32 %1
+}