Index: llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
+++ llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
@@ -172,6 +172,29 @@
     AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26,
     AArch64::X27, AArch64::X28, AArch64::FP,  AArch64::XZR};
 
+static const char *getThunkNameFromRegister(Register Reg) {
+  int Index = -1;
+  for (int i = 0; i < (int)SLSBLRThunkRegs.size(); ++i)
+    if (Reg == SLSBLRThunkRegs[i]) {
+      Index = i;
+      break;
+    }
+  assert(Index != -1);
+  return SLSBLRThunkNames[Index];
+}
+
+static Register getThunkRegisterFromName(StringRef Name) {
+  int Index = -1;
+  for (int i = 0; i < (int)SLSBLRThunkNames.size(); ++i)
+    if (Name == SLSBLRThunkNames[i]) {
+      Index = i;
+      break;
+    }
+  assert(Index != -1);
+  return SLSBLRThunkRegs[Index];
+}
+
+
 namespace {
 struct SLSBLRThunkInserter : ThunkInserter<SLSBLRThunkInserter> {
   const char *getThunkPrefix() { return SLSBLRNamePrefix; }
@@ -197,18 +220,11 @@
   // FIXME: How to better communicate Register number, rather than through
   // name and lookup table?
   assert(MF.getName().startswith(getThunkPrefix()));
-  int Index = -1;
-  for (int i = 0; i < (int)SLSBLRThunkNames.size(); ++i)
-    if (MF.getName() == SLSBLRThunkNames[i]) {
-      Index = i;
-      break;
-    }
-  assert(Index != -1);
-  Register ThunkReg = SLSBLRThunkRegs[Index];
+  Register ThunkReg = getThunkRegisterFromName(MF.getName());
 
   const TargetInstrInfo *TII =
       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
-  assert (MF.size() == 1);
+  assert(MF.size() == 1);
   MachineBasicBlock *Entry = &MF.front();
   Entry->clear();
 
@@ -319,8 +335,8 @@
   // for the future when LLVM can start producing BLRA* instructions.
   MachineFunction &MF = *MBBI->getMF();
   MCContext &Context = MBB.getParent()->getContext();
-  MCSymbol *Sym = Context.getOrCreateSymbol("__llvm_slsblr_thunk_x" +
-                                            utostr(Reg - AArch64::X0));
+  const char *ThunkName = getThunkNameFromRegister(Reg);
+  MCSymbol *Sym = Context.getOrCreateSymbol(ThunkName);
 
   MachineInstr *BL = BuildMI(MBB, MBBI, DL, TII->get(BLOpcode)).addSym(Sym);
 
Index: llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
===================================================================
--- llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
+++ llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mattr=harden-sls-retbr,harden-sls-blr -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,ISBDSB
-; RUN: llc -mattr=harden-sls-retbr,harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,SB
+; RUN: llc -mattr=harden-sls-retbr,harden-sls-blr -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,ISBDSB,ISBDSBDAGISEL
+; RUN: llc -mattr=harden-sls-retbr,harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,SB,SBDAGISEL
 ; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,NOHARDEN
 ; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr,harden-sls-blr -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,ISBDSB
 ; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr,harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,HARDEN,SB
@@ -167,6 +167,41 @@
 ; CHECK: .Lfunc_end
 }
 
+; Verify that the transformation works correctly for x29 when it is not
+; reserved to be used as a frame pointer.
+; Since this is sensitive to register allocation choices, only check this with
+; DAGIsel to avoid too much accidental breaking of this test that is a bit
+; brittle.
+define i64 @check_x29(i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** nocapture readonly %fp,
+                      i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** nocapture readonly %fp2,
+                      i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** nocapture readonly %fp3)
+"target-features"="+neon,+reserve-x10,+reserve-x11,+reserve-x12,+reserve-x13,+reserve-x14,+reserve-x15,+reserve-x18,+reserve-x20,+reserve-x21,+reserve-x22,+reserve-x23,+reserve-x24,+reserve-x25,+reserve-x26,+reserve-x27,+reserve-x28,+reserve-x9"
+"frame-pointer"="none"
+{
+entry:
+; CHECK-LABEL: check_x29:
+  %0 = load i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)*, i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp, align 8
+  %1 = bitcast i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp2 to i8**
+  %2 = load i8*, i8** %1, align 8
+  %3 = load i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)*, i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp2, align 8
+  %4 = bitcast i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp3 to i8**
+  %5 = load i8*, i8** %4, align 8
+  %6 = load i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)*, i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp3, align 8
+  %7 = bitcast i64 (i8*, i8*, i64, i64, i64, i64, i64, i64)** %fp to i8**
+  %8 = load i8*, i8** %7, align 8
+  %call = call i64 %0(i8* %2, i8* %5, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
+  %call1 = call i64 %3(i8* %2, i8* %5, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
+; NOHARDEN:      blr x29
+; ISBDSBDAGISEL: bl __llvm_slsblr_thunk_x29
+; SBDAGISEL:     bl __llvm_slsblr_thunk_x29
+; CHECK
+  %call2 = call i64 %6(i8* %2, i8* %8, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
+  %add = add nsw i64 %call1, %call
+  %add1 = add nsw i64 %call2, %add
+  ret i64 %add1
+; CHECK: .Lfunc_end
+}
+
 ; HARDEN-label: __llvm_slsblr_thunk_x0:
 ; HARDEN:    mov x16, x0
 ; HARDEN:    br x16