Index: llvm/lib/TableGen/Record.cpp =================================================================== --- llvm/lib/TableGen/Record.cpp +++ llvm/lib/TableGen/Record.cpp @@ -1030,7 +1030,7 @@ case MUL: Result = LHSv * RHSv; break; case AND: Result = LHSv & RHSv; break; case OR: Result = LHSv | RHSv; break; - case SHL: Result = LHSv << RHSv; break; + case SHL: Result = (uint64_t)LHSv << (uint64_t)RHSv; break; case SRA: Result = LHSv >> RHSv; break; case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break; } Index: llvm/lib/Target/AMDGPU/SMInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/SMInstructions.td +++ llvm/lib/Target/AMDGPU/SMInstructions.td @@ -860,7 +860,7 @@ def : GCNPat < (i64 (readcyclecounter)), (REG_SEQUENCE SReg_64, - (S_GETREG_B32 -26595), sub0, + (S_GETREG_B32 getHwRegImm.ret), sub0, (S_MOV_B32 (i32 0)), sub1) >; } // let OtherPredicates = [HasNoSMemTimeInst]