Index: lib/Analysis/BranchProbabilityInfo.cpp
===================================================================
--- lib/Analysis/BranchProbabilityInfo.cpp
+++ lib/Analysis/BranchProbabilityInfo.cpp
@@ -382,6 +382,11 @@
   if (CV->isZero()) {
     switch (CI->getPredicate()) {
     case CmpInst::ICMP_EQ:
+      {
+        Instruction *LHS = dyn_cast<Instruction>(CI->getOperand(0));
+        if (LHS && LHS->getOpcode() == Instruction::And)
+          return false;
+      }
       // X == 0   ->  Unlikely
       isProb = false;
       break;
Index: test/CodeGen/AArch64/arm64-call-tailcalls.ll
===================================================================
--- test/CodeGen/AArch64/arm64-call-tailcalls.ll
+++ test/CodeGen/AArch64/arm64-call-tailcalls.ll
@@ -53,9 +53,9 @@
 
 define i32 @t8(i32 %x) nounwind ssp {
 ; CHECK-LABEL: t8:
+; CHECK: b	_c
 ; CHECK: b	_a
 ; CHECK: b	_b
-; CHECK: b	_c
   %and = and i32 %x, 1
   %tobool = icmp eq i32 %and, 0
   br i1 %tobool, label %if.end, label %if.then
Index: test/CodeGen/Mips/octeon.ll
===================================================================
--- test/CodeGen/Mips/octeon.ll
+++ test/CodeGen/Mips/octeon.ll
@@ -93,7 +93,7 @@
 ; ALL-LABEL: bbit0:
 ; OCTEON: bbit0   $4, 3, $[[BB0:BB[0-9_]+]]
 ; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
-; MIPS64: beqz  $[[T0]], $[[BB0:BB[0-9_]+]]
+; MIPS64: bnez  $[[T0]], $[[BB0:BB[0-9_]+]]
   %bit = and i64 %a, 8
   %res = icmp eq i64 %bit, 0
   br i1 %res, label %endif, label %if
@@ -111,7 +111,7 @@
 ; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
 ; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
 ; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]
-; MIPS64: beqz    $[[T2]], $[[BB0:BB[0-9_]+]]
+; MIPS64: bnez    $[[T2]], $[[BB0:BB[0-9_]+]]
   %bit = and i64 %a, 34359738368
   %res = icmp eq i64 %bit, 0
   br i1 %res, label %endif, label %if
Index: test/CodeGen/X86/atom-bypass-slow-division-64.ll
===================================================================
--- test/CodeGen/X86/atom-bypass-slow-division-64.ll
+++ test/CodeGen/X86/atom-bypass-slow-division-64.ll
@@ -9,11 +9,11 @@
 ; CHECK: movq %rdi, %rax
 ; CHECK: orq %rsi, %rax
 ; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
-; CHECK: idivq
-; CHECK: ret
+; CHECK-NEXT: jne
 ; CHECK: divw
 ; CHECK: ret
+; CHECK: idivq
+; CHECK: ret
   %result = sdiv i64 %a, %b
   ret i64 %result
 }
@@ -23,11 +23,11 @@
 ; CHECK: movq %rdi, %rax
 ; CHECK: orq %rsi, %rax
 ; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
-; CHECK: idivq
-; CHECK: ret
+; CHECK-NEXT: jne
 ; CHECK: divw
 ; CHECK: ret
+; CHECK: idivq
+; CHECK: ret
   %result = srem i64 %a, %b
   ret i64 %result
 }
@@ -37,9 +37,9 @@
 ; CHECK: movq %rdi, %rax
 ; CHECK: orq %rsi, %rax
 ; CHECK-NEXT: testq $-65536, %rax
-; CHECK-NEXT: je
-; CHECK: idivq
+; CHECK-NEXT: jne
 ; CHECK: divw
+; CHECK: idivq
 ; CHECK: addq
 ; CHECK: ret
 ; CHECK-NOT: idivq
Index: test/CodeGen/X86/atom-bypass-slow-division.ll
===================================================================
--- test/CodeGen/X86/atom-bypass-slow-division.ll
+++ test/CodeGen/X86/atom-bypass-slow-division.ll
@@ -4,11 +4,11 @@
 ; CHECK-LABEL: Test_get_quotient:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
-; CHECK-NEXT: je
-; CHECK: idivl
-; CHECK: ret
+; CHECK-NEXT: jne
 ; CHECK: divb
 ; CHECK: ret
+; CHECK: idivl
+; CHECK: ret
   %result = sdiv i32 %a, %b
   ret i32 %result
 }
@@ -17,11 +17,11 @@
 ; CHECK-LABEL: Test_get_remainder:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
-; CHECK-NEXT: je
-; CHECK: idivl
-; CHECK: ret
+; CHECK-NEXT: jne
 ; CHECK: divb
 ; CHECK: ret
+; CHECK: idivl
+; CHECK: ret
   %result = srem i32 %a, %b
   ret i32 %result
 }
@@ -30,9 +30,9 @@
 ; CHECK-LABEL: Test_get_quotient_and_remainder:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
-; CHECK-NEXT: je
-; CHECK: idivl
+; CHECK-NEXT: jne
 ; CHECK: divb
+; CHECK: idivl
 ; CHECK: addl
 ; CHECK: ret
 ; CHECK-NOT: idivl
@@ -45,10 +45,10 @@
 
 define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: Test_use_div_and_idiv:
+; CHECK: divb
 ; CHECK: idivl
 ; CHECK: divb
 ; CHECK: divl
-; CHECK: divb
 ; CHECK: addl
 ; CHECK: ret
   %resultidiv = sdiv i32 %a, %b
@@ -96,8 +96,8 @@
 define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
 ; CHECK-LABEL: Test_use_div_imm_reg:
 ; CHECK: test
-; CHECK: idiv
 ; CHECK: divb
+; CHECK: idiv
   %resultdiv = sdiv i32 4, %a
   ret i32 %resultdiv
 }
@@ -105,8 +105,8 @@
 define i32 @Test_use_rem_imm_reg(i32 %a) nounwind {
 ; CHECK-LABEL: Test_use_rem_imm_reg:
 ; CHECK: test
-; CHECK: idiv
 ; CHECK: divb
+; CHECK: idiv
   %resultdiv = sdiv i32 4, %a
   ret i32 %resultdiv
 }
Index: test/CodeGen/X86/peep-test-4.ll
===================================================================
--- test/CodeGen/X86/peep-test-4.ll
+++ test/CodeGen/X86/peep-test-4.ll
@@ -136,9 +136,9 @@
 
 ; CHECK-LABEL: andn:
 ; CHECK: andnl   %esi, %edi, %edi
-; CHECK-NEXT: je
-; CHECK: jmp foo
+; CHECK-NEXT: jne
 ; CHECK: ret
+; CHECK: jmp foo
 define void @andn(i32 %x, i32 %y) nounwind {
   %not = xor i32 %x, -1
   %andn = and i32 %y, %not