Index: llvm/lib/Target/AMDGPU/AMDGPU.td
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPU.td
+++ llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1053,6 +1053,11 @@
             "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
   AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
 
+def isGFX7GFX8 :
+  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
+            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS">,
+  AssemblerPredicate<(all_of FeatureSouthernIslands, FeatureCIInsts)>;
+
 def isGFX7GFX8GFX9 :
   Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
             "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
Index: llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -485,6 +485,11 @@
 defm atomic_load_fadd : ret_noret_binary_atomic_op<atomic_load_fadd, 0>;
 defm AMDGPUatomic_cmp_swap : ret_noret_binary_atomic_op<AMDGPUatomic_cmp_swap>;
 
+def load_align4_local : PatFrag <(ops node:$ptr), (load_local node:$ptr)> {
+  let IsLoad = 1;
+  let IsNonExtLoad = 1;
+  let MinAlignment = 4;
+}
 
 def load_align8_local : PatFrag <(ops node:$ptr), (load_local node:$ptr)> {
   let IsLoad = 1;
@@ -498,6 +503,12 @@
   let MinAlignment = 16;
 }
 
+def store_align4_local: PatFrag<(ops node:$val, node:$ptr),
+                                (store_local node:$val, node:$ptr)>, Aligned<4> {
+  let IsStore = 1;
+  let IsTruncStore = 0;
+}
+
 def store_align8_local: PatFrag<(ops node:$val, node:$ptr),
                                 (store_local node:$val, node:$ptr)>, Aligned<8> {
   let IsStore = 1;
Index: llvm/lib/Target/AMDGPU/DSInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/DSInstructions.td
+++ llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -680,7 +680,29 @@
 defm : DSReadPat_mc <DS_READ_B64, vt, "load_align8_local">;
 }
 
-defm : DSReadPat_mc <DS_READ_B128, v4i32, "load_align16_local">;
+let SubtargetPredicate = isGFX7GFX8 in {
+
+foreach vt = VReg_96.RegTypes in {
+defm : DSReadPat_mc <DS_READ_B96, vt, "load_align16_local">;
+}
+
+foreach vt = VReg_128.RegTypes in {
+defm : DSReadPat_mc <DS_READ_B128, vt, "load_align16_local">;
+}
+
+}
+
+let SubtargetPredicate = isGFX9Plus in {
+
+foreach vt = VReg_96.RegTypes in {
+defm : DSReadPat_mc <DS_READ_B96, vt, "load_align4_local">;
+}
+
+foreach vt = VReg_128.RegTypes in {
+defm : DSReadPat_mc <DS_READ_B128, vt, "load_align4_local">;
+}
+
+}
 
 } // End AddedComplexity = 100
 
@@ -785,7 +807,29 @@
 defm : DSWritePat_mc <DS_WRITE_B64, vt, "store_align8_local">;
 }
 
-defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;
+let SubtargetPredicate = isGFX7GFX8 in {
+
+foreach vt = VReg_96.RegTypes in {
+defm : DSWritePat_mc <DS_WRITE_B96, vt, "store_align16_local">;
+}
+
+foreach vt = VReg_128.RegTypes in {
+defm : DSWritePat_mc <DS_WRITE_B128, vt, "store_align16_local">;
+}
+
+}
+
+let SubtargetPredicate = isGFX9Plus in {
+
+foreach vt = VReg_96.RegTypes in {
+defm : DSWritePat_mc <DS_WRITE_B96, vt, "store_align4_local">;
+}
+
+foreach vt = VReg_128.RegTypes in {
+defm : DSWritePat_mc <DS_WRITE_B128, vt, "store_align4_local">;
+}
+
+}
 
 } // End AddedComplexity = 100
 class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1362,14 +1362,26 @@
 
   if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
       AddrSpace == AMDGPUAS::REGION_ADDRESS) {
-    // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
-    // aligned, 8 byte access in a single operation using ds_read2/write2_b32
-    // with adjacent offsets.
-    bool AlignedBy4 = (Align % 4 == 0);
-    if (IsFast)
-      *IsFast = AlignedBy4;
-
-    return AlignedBy4;
+    if (Size == 64) {
+      // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
+      // aligned, 8 byte access in a single operation using ds_read2/write2_b32
+      // with adjacent offsets.
+      bool AlignedBy4 = (Align % 4 == 0);
+      if (IsFast)
+        *IsFast = AlignedBy4;
+
+      return AlignedBy4;
+    }
+    else if (Size == 96 || Size == 128) {
+      // ds_read/write_b96/128 require 16-byte alignment, gfx9 and onward has
+      // unaligned access support.
+      bool IsGFX9Plus = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9;
+      bool Aligned = Align % (IsGFX9Plus ? 4 : 16) == 0;
+      if (IsFast)
+        *IsFast = Aligned;
+
+      return Aligned;
+    }
   }
 
   // FIXME: We have to be conservative here and assume that flat operations
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -449,6 +449,12 @@
 def zextloadi16_local_m0 : PatFrag<(ops node:$ptr), (zextloadi16_glue node:$ptr)>;
 }
 
+def load_align4_local_m0 : PatFrag<(ops node:$ptr),
+                                   (load_local_m0 node:$ptr)> {
+  let IsLoad = 1;
+  let IsNonExtLoad = 1;
+  let MinAlignment = 4;
+}
 def load_align8_local_m0 : PatFrag<(ops node:$ptr),
                                    (load_local_m0 node:$ptr)> {
   let IsLoad = 1;
@@ -551,6 +557,14 @@
   let MinAlignment = 8;
 }
 
+def store_align4_local_m0 : PatFrag <
+  (ops node:$value, node:$ptr),
+  (store_local_m0 node:$value, node:$ptr)> {
+  let IsStore = 1;
+  let IsTruncStore = 0;
+  let MinAlignment = 4;
+}
+
 let AddressSpaces = StoreAddress_local.AddrSpaces in {
 
 def atomic_store_local_32_m0 : PatFrag <
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
@@ -62,8 +62,7 @@
     ; GFX7-DS128-LABEL: name: load_local_v4s32_align_4
     ; GFX7-DS128: liveins: $vgpr0
     ; GFX7-DS128: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
-    ; GFX7-DS128: $m0 = S_MOV_B32 -1
-    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vreg_128(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
+    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
     ; GFX7-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
     ; GFX9-LABEL: name: load_local_v4s32_align_4
     ; GFX9: liveins: $vgpr0
@@ -100,8 +99,7 @@
     ; GFX7-DS128-LABEL: name: load_local_v2s64
     ; GFX7-DS128: liveins: $vgpr0
     ; GFX7-DS128: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
-    ; GFX7-DS128: $m0 = S_MOV_B32 -1
-    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vreg_128(<2 x s64>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
+    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
     ; GFX7-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
     ; GFX9-LABEL: name: load_local_v2s64
     ; GFX9: liveins: $vgpr0
@@ -138,8 +136,7 @@
     ; GFX7-DS128-LABEL: name: load_local_v2p1
     ; GFX7-DS128: liveins: $vgpr0
     ; GFX7-DS128: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
-    ; GFX7-DS128: $m0 = S_MOV_B32 -1
-    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vreg_128(<2 x p1>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
+    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vgpr(<2 x p1>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
     ; GFX7-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x p1>)
     ; GFX9-LABEL: name: load_local_v2p1
     ; GFX9: liveins: $vgpr0
@@ -176,8 +173,7 @@
     ; GFX7-DS128-LABEL: name: load_local_s128
     ; GFX7-DS128: liveins: $vgpr0
     ; GFX7-DS128: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
-    ; GFX7-DS128: $m0 = S_MOV_B32 -1
-    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vreg_128(s128) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
+    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vgpr(s128) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
     ; GFX7-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](s128)
     ; GFX9-LABEL: name: load_local_s128
     ; GFX9: liveins: $vgpr0
@@ -214,8 +210,7 @@
     ; GFX7-DS128-LABEL: name: load_local_v8s16
     ; GFX7-DS128: liveins: $vgpr0
     ; GFX7-DS128: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
-    ; GFX7-DS128: $m0 = S_MOV_B32 -1
-    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vreg_128(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
+    ; GFX7-DS128: [[LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
     ; GFX7-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<8 x s16>)
     ; GFX9-LABEL: name: load_local_v8s16
     ; GFX9: liveins: $vgpr0
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
@@ -1669,13 +1669,25 @@
     ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
     ; CI-DS128-LABEL: name: test_load_local_s96_align8
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 8, addrspace 3)
-    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load 8, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 8, align 8, addrspace 3)
+    ; CI-DS128: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; CI-DS128: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
+    ; CI-DS128: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT1]](<3 x s32>)
     ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
     ; VI-LABEL: name: test_load_local_s96_align8
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 8, addrspace 3)
-    ; VI: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
+    ; VI: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load 8, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 8, align 8, addrspace 3)
+    ; VI: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; VI: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
+    ; VI: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; VI: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT1]](<3 x s32>)
     ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
     ; GFX9-LABEL: name: test_load_local_s96_align8
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -1717,13 +1729,25 @@
     ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
     ; CI-DS128-LABEL: name: test_load_local_s96_align4
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 4, addrspace 3)
-    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 8, addrspace 3)
+    ; CI-DS128: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; CI-DS128: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
+    ; CI-DS128: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT1]](<3 x s32>)
     ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
     ; VI-LABEL: name: test_load_local_s96_align4
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 4, addrspace 3)
-    ; VI: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
+    ; VI: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 8, addrspace 3)
+    ; VI: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; VI: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
+    ; VI: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; VI: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT1]](<3 x s32>)
     ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[BITCAST]](s96)
     ; GFX9-LABEL: name: test_load_local_s96_align4
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -2916,13 +2940,33 @@
     ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
     ; CI-DS128-LABEL: name: test_load_local_s128_align8
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 8, addrspace 3)
-    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, align 8, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 4, addrspace 3)
+    ; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 8, align 8, addrspace 3)
+    ; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
+    ; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 12, addrspace 3)
+    ; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
+    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
     ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
     ; VI-LABEL: name: test_load_local_s128_align8
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 8, addrspace 3)
-    ; VI: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
+    ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, align 8, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 4, addrspace 3)
+    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 8, align 8, addrspace 3)
+    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
+    ; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 12, addrspace 3)
+    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
+    ; VI: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
     ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
     ; GFX9-LABEL: name: test_load_local_s128_align8
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -2960,13 +3004,33 @@
     ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
     ; CI-DS128-LABEL: name: test_load_local_s128_align4
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
-    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 4, addrspace 3)
+    ; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 8, addrspace 3)
+    ; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
+    ; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 12, addrspace 3)
+    ; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
+    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
     ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
     ; VI-LABEL: name: test_load_local_s128_align4
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
-    ; VI: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[LOAD]](<4 x s32>)
+    ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 4, addrspace 3)
+    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 8, addrspace 3)
+    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
+    ; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 12, addrspace 3)
+    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
+    ; VI: [[BITCAST:%[0-9]+]]:_(s128) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
     ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BITCAST]](s128)
     ; GFX9-LABEL: name: test_load_local_s128_align4
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -7832,12 +7896,24 @@
     ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](<3 x s32>)
     ; CI-DS128-LABEL: name: test_load_local_v3s32_align4
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 4, addrspace 3)
-    ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 8, addrspace 3)
+    ; CI-DS128: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; CI-DS128: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
+    ; CI-DS128: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](<3 x s32>)
     ; VI-LABEL: name: test_load_local_v3s32_align4
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 4, addrspace 3)
-    ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](<3 x s32>)
+    ; VI: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 8, addrspace 3)
+    ; VI: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; VI: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
+    ; VI: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](<3 x s32>)
     ; GFX9-LABEL: name: test_load_local_v3s32_align4
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
     ; GFX9: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 4, addrspace 3)
@@ -7910,12 +7986,32 @@
     ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
     ; CI-DS128-LABEL: name: test_load_local_v4s32_align8
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 8, addrspace 3)
-    ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, align 8, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 4, addrspace 3)
+    ; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 8, align 8, addrspace 3)
+    ; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
+    ; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 12, addrspace 3)
+    ; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
+    ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
     ; VI-LABEL: name: test_load_local_v4s32_align8
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 8, addrspace 3)
-    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
+    ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, align 8, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 4, addrspace 3)
+    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 8, align 8, addrspace 3)
+    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
+    ; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 12, addrspace 3)
+    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
+    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
     ; GFX9-LABEL: name: test_load_local_v4s32_align8
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
     ; GFX9: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 8, addrspace 3)
@@ -7949,12 +8045,32 @@
     ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<4 x s32>)
     ; CI-DS128-LABEL: name: test_load_local_v4s32_align4
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
-    ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 4, addrspace 3)
+    ; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 8, addrspace 3)
+    ; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
+    ; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 12, addrspace 3)
+    ; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
+    ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
     ; VI-LABEL: name: test_load_local_v4s32_align4
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
-    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<4 x s32>)
+    ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 4, addrspace 3)
+    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 8, addrspace 3)
+    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
+    ; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 12, addrspace 3)
+    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
+    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
     ; GFX9-LABEL: name: test_load_local_v4s32_align4
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
     ; GFX9: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
@@ -8856,12 +8972,20 @@
     ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
     ; CI-DS128-LABEL: name: test_load_local_v2s64_align4
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
-    ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load 8 + 8, align 4, addrspace 3)
+    ; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
+    ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
     ; VI-LABEL: name: test_load_local_v2s64_align4
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
-    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x s64>)
+    ; VI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p3) :: (load 8 + 8, align 4, addrspace 3)
+    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
+    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
     ; GFX9-LABEL: name: test_load_local_v2s64_align4
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
     ; GFX9: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
@@ -9652,12 +9776,20 @@
     ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p1>)
     ; CI-DS128-LABEL: name: test_load_local_v2p1_align4
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
-    ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x p1>)
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p3) :: (load 8 + 8, align 4, addrspace 3)
+    ; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[LOAD]](p1), [[LOAD1]](p1)
+    ; CI-DS128: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p1>)
     ; VI-LABEL: name: test_load_local_v2p1_align4
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
-    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[LOAD]](<2 x p1>)
+    ; VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
+    ; VI: [[LOAD1:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p3) :: (load 8 + 8, align 4, addrspace 3)
+    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[LOAD]](p1), [[LOAD1]](p1)
+    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p1>)
     ; GFX9-LABEL: name: test_load_local_v2p1_align4
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
     ; GFX9: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[COPY]](p3) :: (load 16, align 4, addrspace 3)
@@ -11369,28 +11501,50 @@
     ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY3]](s96)
     ; CI-DS128-LABEL: name: test_extload_local_v2s96_from_24_align4
     ; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 4, addrspace 3)
-    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
-    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CI-DS128: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
     ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
-    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load 12 + 12, align 4, addrspace 3)
-    ; CI-DS128: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD1]](<3 x s32>)
-    ; CI-DS128: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
-    ; CI-DS128: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
-    ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
-    ; CI-DS128: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 8, addrspace 3)
+    ; CI-DS128: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; CI-DS128: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF]](<3 x s32>)
+    ; CI-DS128: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[COPY1]], [[LOAD]](<2 x s32>), 0
+    ; CI-DS128: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT1]](<3 x s32>)
+    ; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CI-DS128: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; CI-DS128: [[LOAD2:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD1]](p3) :: (load 8 + 12, align 4, addrspace 3)
+    ; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
+    ; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 20, addrspace 3)
+    ; CI-DS128: [[INSERT2:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD2]](<2 x s32>), 0
+    ; CI-DS128: [[INSERT3:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT2]], [[LOAD3]](s32), 64
+    ; CI-DS128: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT3]](<3 x s32>)
+    ; CI-DS128: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+    ; CI-DS128: [[COPY3:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+    ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[COPY2]](s96)
+    ; CI-DS128: $vgpr3_vgpr4_vgpr5 = COPY [[COPY3]](s96)
     ; VI-LABEL: name: test_extload_local_v2s96_from_24_align4
     ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
-    ; VI: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 4, addrspace 3)
-    ; VI: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
-    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; VI: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p3) :: (load 8, align 4, addrspace 3)
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
     ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
-    ; VI: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load 12 + 12, align 4, addrspace 3)
-    ; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD1]](<3 x s32>)
-    ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
-    ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
-    ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
-    ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
+    ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load 4 + 8, addrspace 3)
+    ; VI: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF]](<3 x s32>)
+    ; VI: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[COPY1]], [[LOAD]](<2 x s32>), 0
+    ; VI: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; VI: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT1]](<3 x s32>)
+    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; VI: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C1]](s32)
+    ; VI: [[LOAD2:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD1]](p3) :: (load 8 + 12, align 4, addrspace 3)
+    ; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
+    ; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load 4 + 20, addrspace 3)
+    ; VI: [[INSERT2:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD2]](<2 x s32>), 0
+    ; VI: [[INSERT3:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT2]], [[LOAD3]](s32), 64
+    ; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT3]](<3 x s32>)
+    ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+    ; VI: [[COPY3:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+    ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY2]](s96)
+    ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY3]](s96)
     ; GFX9-LABEL: name: test_extload_local_v2s96_from_24_align4
     ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
     ; GFX9: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load 12, align 4, addrspace 3)
@@ -11469,8 +11623,14 @@
     ; CI-DS128: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
     ; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
     ; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
-    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load 12 + 12, align 4, addrspace 3)
-    ; CI-DS128: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD1]](<3 x s32>)
+    ; CI-DS128: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load 8 + 12, align 4, addrspace 3)
+    ; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CI-DS128: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD]], [[C1]](s32)
+    ; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 20, addrspace 3)
+    ; CI-DS128: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; CI-DS128: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD1]](<2 x s32>), 0
+    ; CI-DS128: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD2]](s32), 64
+    ; CI-DS128: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT1]](<3 x s32>)
     ; CI-DS128: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
     ; CI-DS128: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
     ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
@@ -11481,8 +11641,14 @@
     ; VI: [[BITCAST:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD]](<3 x s32>)
     ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
     ; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
-    ; VI: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load 12 + 12, align 4, addrspace 3)
-    ; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[LOAD1]](<3 x s32>)
+    ; VI: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD]](p3) :: (load 8 + 12, align 4, addrspace 3)
+    ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; VI: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD]], [[C1]](s32)
+    ; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load 4 + 20, addrspace 3)
+    ; VI: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
+    ; VI: [[INSERT:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[DEF]], [[LOAD1]](<2 x s32>), 0
+    ; VI: [[INSERT1:%[0-9]+]]:_(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD2]](s32), 64
+    ; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[INSERT1]](<3 x s32>)
     ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
     ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
     ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
@@ -0,0 +1,344 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-UNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-NOUNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-UNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-NOUNALIGNED %s
+
+; FIXME:
+; XUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
+
+define <4 x i32> @v_load_lds_v3i32(<4 x i32> addrspace(3)* %ptr) {
+; GFX9-LABEL: v_load_lds_v3i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    ds_read_b128 v[0:3], v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_load_lds_v3i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    ds_read_b128 v[0:3], v0
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr
+  ret <4 x i32> %load
+}
+
+define <4 x i32> @v_load_lds_v3i32_align1(<4 x i32> addrspace(3)* %ptr) {
+; GFX9-UNALIGNED-LABEL: v_load_lds_v3i32_align1:
+; GFX9-UNALIGNED:       ; %bb.0:
+; GFX9-UNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-UNALIGNED-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX9-UNALIGNED-NEXT:    ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
+; GFX9-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-NOUNALIGNED-LABEL: v_load_lds_v3i32_align1:
+; GFX9-NOUNALIGNED:       ; %bb.0:
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v2, v0 offset:1
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v4, v0 offset:2
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v5, v0 offset:3
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v6, v0 offset:4
+; GFX9-NOUNALIGNED-NEXT:    s_mov_b32 s5, 8
+; GFX9-NOUNALIGNED-NEXT:    s_movk_i32 s4, 0xff
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v2, s5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v1, v1, s4, v2
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v4
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, s4, v5
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 24, v4
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v4, v1, v2, v4
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v1, v0 offset:5
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v2, v0 offset:6
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v5, v0 offset:7
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v7, v0 offset:8
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v8, v0 offset:9
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v3, 0xff
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v2, v3
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, v5, v3
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v1, v6, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v5, 24, v5
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v1, v1, v2, v5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v5, 8
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v2, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v2, v7, v3, v2
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v6, v0 offset:10
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v7, v0 offset:11
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v8, v0 offset:12
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v9, v0 offset:13
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v10, v0 offset:14
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v0, v0 offset:15
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(5)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v6, v6, v3
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v7, v7, v3
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v7, 24, v7
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v5, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v0, v0, v3
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v2, v2, v6, v7
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v6, v10, v3
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v5, v8, v3, v5
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v3, v5, v6, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, v4
+; GFX9-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-UNALIGNED-LABEL: v_load_lds_v3i32_align1:
+; GFX7-UNALIGNED:       ; %bb.0:
+; GFX7-UNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-UNALIGNED-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX7-UNALIGNED-NEXT:    ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
+; GFX7-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-NOUNALIGNED-LABEL: v_load_lds_v3i32_align1:
+; GFX7-NOUNALIGNED:       ; %bb.0:
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v2, v0 offset:1
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v4, v0 offset:2
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v5, v0 offset:3
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v6, v0 offset:4
+; GFX7-NOUNALIGNED-NEXT:    s_movk_i32 s4, 0xff
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v2
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v4
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v5
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v4, v1, v2
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v6
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v3, 0xff
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v2, v0 offset:5
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v5, v0 offset:6
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v6, v0 offset:7
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v7, v0 offset:8
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v8, v0 offset:9
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v2, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v5, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v6, v3
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, v8, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v7, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v5, 8, v5
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v5, v0 offset:10
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v6, v0 offset:11
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v7, v0 offset:12
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v8, v0 offset:13
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v9, v0 offset:14
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, v5, v3
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v0, v0 offset:15
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, v6, v3
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v6, v8, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v5, 24, v5
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, v7, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v6, v9, v3
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v0, v0, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v0, 24, v0
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v3, v5, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, v4
+; GFX7-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 1
+  ret <4 x i32> %load
+}
+
+define <4 x i32> @v_load_lds_v3i32_align2(<4 x i32> addrspace(3)* %ptr) {
+; GFX9-UNALIGNED-LABEL: v_load_lds_v3i32_align2:
+; GFX9-UNALIGNED:       ; %bb.0:
+; GFX9-UNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-UNALIGNED-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX9-UNALIGNED-NEXT:    ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
+; GFX9-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-NOUNALIGNED-LABEL: v_load_lds_v3i32_align2:
+; GFX9-NOUNALIGNED:       ; %bb.0:
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v2, v0 offset:2
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v3, v0 offset:4
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v5, v0 offset:6
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v6, v0 offset:8
+; GFX9-NOUNALIGNED-NEXT:    s_mov_b32 s4, 0xffff
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v2
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v4, v1, s4, v2
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v5
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v1, v3, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v2, v0 offset:10
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v3, v0 offset:12
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v0, v0 offset:14
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v2
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v3, v3, s4, v0
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v2, v6, s4, v2
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, v4
+; GFX9-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-UNALIGNED-LABEL: v_load_lds_v3i32_align2:
+; GFX7-UNALIGNED:       ; %bb.0:
+; GFX7-UNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-UNALIGNED-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX7-UNALIGNED-NEXT:    ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
+; GFX7-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-NOUNALIGNED-LABEL: v_load_lds_v3i32_align2:
+; GFX7-NOUNALIGNED:       ; %bb.0:
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v2, v0 offset:2
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v3, v0 offset:4
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v5, v0 offset:6
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v6, v0 offset:8
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 s4, 0xffff
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v2
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v4, v1, v2
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v5
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v3
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v3, v0 offset:10
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v5, v0 offset:12
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v0, v0 offset:14
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v3, s4, v3
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v6
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v3, s4, v5
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v3, v3, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, v4
+; GFX7-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 2
+  ret <4 x i32> %load
+}
+
+define <4 x i32> @v_load_lds_v3i32_align4(<4 x i32> addrspace(3)* %ptr) {
+; GFX9-LABEL: v_load_lds_v3i32_align4:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    ds_read_b128 v[0:3], v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_load_lds_v3i32_align4:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX7-NEXT:    ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 4
+  ret <4 x i32> %load
+}
+
+define <4 x i32> @v_load_lds_v3i32_align8(<4 x i32> addrspace(3)* %ptr) {
+; GFX9-LABEL: v_load_lds_v3i32_align8:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    ds_read_b128 v[0:3], v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_load_lds_v3i32_align8:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX7-NEXT:    ds_read2_b32 v[2:3], v2 offset0:2 offset1:3
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 8
+  ret <4 x i32> %load
+}
+
+define <4 x i32> @v_load_lds_v3i32_align16(<4 x i32> addrspace(3)* %ptr) {
+; GFX9-LABEL: v_load_lds_v3i32_align16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    ds_read_b128 v[0:3], v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_load_lds_v3i32_align16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    ds_read_b128 v[0:3], v0
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <4 x i32>, <4 x i32> addrspace(3)* %ptr, align 16
+  ret <4 x i32> %load
+}
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll
@@ -0,0 +1,302 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-UNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-NOUNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-UNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-NOUNALIGNED %s
+
+; FIXME:
+; XUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
+
+define <3 x i32> @load_lds_v3i32(<3 x i32> addrspace(3)* %ptr) {
+; GFX9-LABEL: load_lds_v3i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    ds_read_b96 v[0:2], v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: load_lds_v3i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    ds_read_b96 v[0:2], v0
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr
+  ret <3 x i32> %load
+}
+
+define <3 x i32> @load_lds_v3i32_align1(<3 x i32> addrspace(3)* %ptr) {
+; GFX9-UNALIGNED-LABEL: load_lds_v3i32_align1:
+; GFX9-UNALIGNED:       ; %bb.0:
+; GFX9-UNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-UNALIGNED-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX9-UNALIGNED-NEXT:    ds_read_b32 v2, v2 offset:8
+; GFX9-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-NOUNALIGNED-LABEL: load_lds_v3i32_align1:
+; GFX9-NOUNALIGNED:       ; %bb.0:
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v0, v0
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v1, v2 offset:1
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v4, v2 offset:2
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v5, v2 offset:3
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v6, v2 offset:4
+; GFX9-NOUNALIGNED-NEXT:    s_mov_b32 s5, 8
+; GFX9-NOUNALIGNED-NEXT:    s_movk_i32 s4, 0xff
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v0, v0, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v4
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, s4, v5
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 24, v4
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v0, v0, v1, v4
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v1, v2 offset:5
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v4, v2 offset:6
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v5, v2 offset:7
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v7, v2 offset:8
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v8, v2 offset:9
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v3, 0xff
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, v4, v3
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, v5, v3
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v1, v6, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v5, 24, v5
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v1, v1, v4, v5
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v4, v2 offset:10
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u8 v2, v2 offset:11
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v5, 8
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v5, v7, v3, v5
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, v4, v3
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v2, v3
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v2, v5, v4, v2
+; GFX9-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-UNALIGNED-LABEL: load_lds_v3i32_align1:
+; GFX7-UNALIGNED:       ; %bb.0:
+; GFX7-UNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-UNALIGNED-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX7-UNALIGNED-NEXT:    ds_read_b32 v2, v2 offset:8
+; GFX7-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-NOUNALIGNED-LABEL: load_lds_v3i32_align1:
+; GFX7-NOUNALIGNED:       ; %bb.0:
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v0, v0
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v1, v2 offset:1
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v4, v2 offset:2
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v5, v2 offset:3
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v6, v2 offset:4
+; GFX7-NOUNALIGNED-NEXT:    s_movk_i32 s4, 0xff
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v4
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v5
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 24, v1
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v6
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v3, 0xff
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v4, v2 offset:5
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v5, v2 offset:6
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v6, v2 offset:7
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v7, v2 offset:8
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v8, v2 offset:9
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, v4, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 8, v4
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, v5, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, v6, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 24, v4
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v4
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v4, v2 offset:10
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u8 v2, v2 offset:11
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v6, v8, v3
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, v7, v3
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v6, 8, v6
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, v4, v3
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v2, v3
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v5, v5, v6
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v4, v5, v4
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v2, v4, v2
+; GFX7-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 1
+  ret <3 x i32> %load
+}
+
+define <3 x i32> @load_lds_v3i32_align2(<3 x i32> addrspace(3)* %ptr) {
+; GFX9-UNALIGNED-LABEL: load_lds_v3i32_align2:
+; GFX9-UNALIGNED:       ; %bb.0:
+; GFX9-UNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-UNALIGNED-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX9-UNALIGNED-NEXT:    ds_read_b32 v2, v2 offset:8
+; GFX9-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-NOUNALIGNED-LABEL: load_lds_v3i32_align2:
+; GFX9-NOUNALIGNED:       ; %bb.0:
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v0, v0
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v1, v2 offset:2
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v3, v2 offset:4
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v4, v2 offset:6
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v5, v2 offset:8
+; GFX9-NOUNALIGNED-NEXT:    ds_read_u16 v2, v2 offset:10
+; GFX9-NOUNALIGNED-NEXT:    s_mov_b32 s4, 0xffff
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v0, v0, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v4
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v2
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v1, v3, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v2, v5, s4, v2
+; GFX9-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-UNALIGNED-LABEL: load_lds_v3i32_align2:
+; GFX7-UNALIGNED:       ; %bb.0:
+; GFX7-UNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-UNALIGNED-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX7-UNALIGNED-NEXT:    ds_read_b32 v2, v2 offset:8
+; GFX7-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-NOUNALIGNED-LABEL: load_lds_v3i32_align2:
+; GFX7-NOUNALIGNED:       ; %bb.0:
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v0, v0
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v1, v2 offset:2
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v3, v2 offset:4
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v4, v2 offset:6
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v5, v2 offset:8
+; GFX7-NOUNALIGNED-NEXT:    ds_read_u16 v2, v2 offset:10
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 s4, 0xffff
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(4)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(3)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v3
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(2)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v3, s4, v4
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, s4, v2
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX7-NOUNALIGNED-NEXT:    v_and_b32_e32 v3, s4, v5
+; GFX7-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX7-NOUNALIGNED-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX7-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 2
+  ret <3 x i32> %load
+}
+
+define <3 x i32> @load_lds_v3i32_align4(<3 x i32> addrspace(3)* %ptr) {
+; GFX9-LABEL: load_lds_v3i32_align4:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    ds_read_b96 v[0:2], v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: load_lds_v3i32_align4:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    ds_read2_b32 v[0:1], v0 offset1:1
+; GFX7-NEXT:    ds_read_b32 v2, v2 offset:8
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 4
+  ret <3 x i32> %load
+}
+
+define <3 x i32> @load_lds_v3i32_align8(<3 x i32> addrspace(3)* %ptr) {
+; GFX9-LABEL: load_lds_v3i32_align8:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    ds_read_b96 v[0:2], v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: load_lds_v3i32_align8:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v2, v0
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    ds_read_b64 v[0:1], v0
+; GFX7-NEXT:    ds_read_b32 v2, v2 offset:8
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 8
+  ret <3 x i32> %load
+}
+
+define <3 x i32> @load_lds_v3i32_align16(<3 x i32> addrspace(3)* %ptr) {
+; GFX9-LABEL: load_lds_v3i32_align16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    ds_read_b96 v[0:2], v0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: load_lds_v3i32_align16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    ds_read_b96 v[0:2], v0
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+  %load = load <3 x i32>, <3 x i32> addrspace(3)* %ptr, align 16
+  ret <3 x i32> %load
+}
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
@@ -0,0 +1,498 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-UNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-NOUNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-UNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-NOUNALIGNED %s
+
+; FIXME:
+; XUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
+
+define amdgpu_kernel void @store_lds_v3i32(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
+; GFX9-LABEL: store_lds_v3i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v4, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    ds_write_b128 v4, v[0:3]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX7-LABEL: store_lds_v3i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v4, s4
+; GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s1
+; GFX7-NEXT:    v_mov_b32_e32 v2, s2
+; GFX7-NEXT:    v_mov_b32_e32 v3, s3
+; GFX7-NEXT:    ds_write_b128 v4, v[0:3]
+; GFX7-NEXT:    s_endpgm
+  store <4 x i32> %x, <4 x i32> addrspace(3)* %out
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align1(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
+; GFX9-UNALIGNED-LABEL: store_lds_v3i32_align1:
+; GFX9-UNALIGNED:       ; %bb.0:
+; GFX9-UNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-UNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v2, s1
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v0, v2
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 12
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    s_endpgm
+;
+; GFX9-NOUNALIGNED-LABEL: store_lds_v3i32_align1:
+; GFX9-NOUNALIGNED:       ; %bb.0:
+; GFX9-NOUNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NOUNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s0, 8
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s0, 16
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s7, s0, 24
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 1
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 2
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 3
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s7
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s1, 8
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 5
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s1, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 6
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s7, s1, 24
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 7
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s7
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s2, 8
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 9
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s2, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 10
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s2, 24
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 11
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 12
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s3, 8
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 13
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s2, s3, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 14
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s3, 24
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 15
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    s_endpgm
+;
+; GFX7-UNALIGNED-LABEL: store_lds_v3i32_align1:
+; GFX7-UNALIGNED:       ; %bb.0:
+; GFX7-UNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-UNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 12
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    s_endpgm
+;
+; GFX7-NOUNALIGNED-LABEL: store_lds_v3i32_align1:
+; GFX7-NOUNALIGNED:       ; %bb.0:
+; GFX7-NOUNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NOUNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s0, 8
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s0, 16
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s7, s0, 24
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 1
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 2
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 3
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s7
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s1, 8
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 5
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s1, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 6
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s7, s1, 24
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 7
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s7
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s2, 8
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 9
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s2, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 10
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s2, 24
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 11
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 12
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s3, 8
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 13
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s2, s3, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 14
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s3, 24
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 15
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    s_endpgm
+  store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 1
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align2(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
+; GFX9-UNALIGNED-LABEL: store_lds_v3i32_align2:
+; GFX9-UNALIGNED:       ; %bb.0:
+; GFX9-UNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-UNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v2, s1
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v0, v2
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 12
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    s_endpgm
+;
+; GFX9-NOUNALIGNED-LABEL: store_lds_v3i32_align2:
+; GFX9-NOUNALIGNED:       ; %bb.0:
+; GFX9-NOUNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NOUNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s0, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 2
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s1, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 6
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s2, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 10
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 12
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s3, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 14
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    s_endpgm
+;
+; GFX7-UNALIGNED-LABEL: store_lds_v3i32_align2:
+; GFX7-UNALIGNED:       ; %bb.0:
+; GFX7-UNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-UNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 12
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    s_endpgm
+;
+; GFX7-NOUNALIGNED-LABEL: store_lds_v3i32_align2:
+; GFX7-NOUNALIGNED:       ; %bb.0:
+; GFX7-NOUNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NOUNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s0, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 2
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s1, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 6
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s2, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 10
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 12
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s3, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 14
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    s_endpgm
+  store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 2
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align4(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
+; GFX9-LABEL: store_lds_v3i32_align4:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v4, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    ds_write_b128 v4, v[0:3]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX7-LABEL: store_lds_v3i32_align4:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NEXT:    s_add_u32 s0, s4, 12
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    s_endpgm
+  store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align8(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
+; GFX9-LABEL: store_lds_v3i32_align8:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v4, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    ds_write_b128 v4, v[0:3]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX7-LABEL: store_lds_v3i32_align8:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NEXT:    s_add_u32 s0, s4, 12
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    s_endpgm
+  store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 8
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align16(<4 x i32> addrspace(3)* %out, <4 x i32> %x) {
+; GFX9-LABEL: store_lds_v3i32_align16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v4, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    ds_write_b128 v4, v[0:3]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX7-LABEL: store_lds_v3i32_align16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v4, s4
+; GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s1
+; GFX7-NEXT:    v_mov_b32_e32 v2, s2
+; GFX7-NEXT:    v_mov_b32_e32 v3, s3
+; GFX7-NEXT:    ds_write_b128 v4, v[0:3]
+; GFX7-NEXT:    s_endpgm
+  store <4 x i32> %x, <4 x i32> addrspace(3)* %out, align 16
+  ret void
+}
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
@@ -0,0 +1,406 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-UNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-NOUNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-UNALIGNED %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7,GFX7-NOUNALIGNED %s
+
+; FIXME:
+; XUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
+
+define amdgpu_kernel void @store_lds_v3i32(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
+; GFX9-LABEL: store_lds_v3i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v3, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    ds_write_b96 v3, v[0:2]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX7-LABEL: store_lds_v3i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v3, s4
+; GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s1
+; GFX7-NEXT:    v_mov_b32_e32 v2, s2
+; GFX7-NEXT:    ds_write_b96 v3, v[0:2]
+; GFX7-NEXT:    s_endpgm
+  store <3 x i32> %x, <3 x i32> addrspace(3)* %out
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align1(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
+; GFX9-UNALIGNED-LABEL: store_lds_v3i32_align1:
+; GFX9-UNALIGNED:       ; %bb.0:
+; GFX9-UNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-UNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v2, s1
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v0, v2
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    s_endpgm
+;
+; GFX9-NOUNALIGNED-LABEL: store_lds_v3i32_align1:
+; GFX9-NOUNALIGNED:       ; %bb.0:
+; GFX9-NOUNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NOUNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s0, 8
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s0, 16
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s0, 24
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 1
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 2
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 3
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s1, 8
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 5
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s1, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 6
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s1, 24
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 7
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s2, 8
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 9
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 10
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s2, 24
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 11
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    s_endpgm
+;
+; GFX7-UNALIGNED-LABEL: store_lds_v3i32_align1:
+; GFX7-UNALIGNED:       ; %bb.0:
+; GFX7-UNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-UNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    s_endpgm
+;
+; GFX7-NOUNALIGNED-LABEL: store_lds_v3i32_align1:
+; GFX7-NOUNALIGNED:       ; %bb.0:
+; GFX7-NOUNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NOUNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s0, 8
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s0, 16
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s0, 24
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 1
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 2
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 3
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s1, 8
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 5
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s1, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 6
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s1, 24
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 7
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s6
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s2, 8
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 9
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 10
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s2, 24
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 11
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s5
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b8 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    s_endpgm
+  store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 1
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align2(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
+; GFX9-UNALIGNED-LABEL: store_lds_v3i32_align2:
+; GFX9-UNALIGNED:       ; %bb.0:
+; GFX9-UNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-UNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v2, s1
+; GFX9-UNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v0, v2
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX9-UNALIGNED-NEXT:    s_endpgm
+;
+; GFX9-NOUNALIGNED-LABEL: store_lds_v3i32_align2:
+; GFX9-NOUNALIGNED:       ; %bb.0:
+; GFX9-NOUNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NOUNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s0, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 2
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s1, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 6
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s2, 16
+; GFX9-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 10
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX9-NOUNALIGNED-NEXT:    s_endpgm
+;
+; GFX7-UNALIGNED-LABEL: store_lds_v3i32_align2:
+; GFX7-UNALIGNED:       ; %bb.0:
+; GFX7-UNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-UNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-UNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-UNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-UNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-UNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-UNALIGNED-NEXT:    ds_write_b32 v1, v0
+; GFX7-UNALIGNED-NEXT:    s_endpgm
+;
+; GFX7-NOUNALIGNED-LABEL: store_lds_v3i32_align2:
+; GFX7-NOUNALIGNED:       ; %bb.0:
+; GFX7-NOUNALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NOUNALIGNED-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NOUNALIGNED-NEXT:    s_mov_b32 m0, -1
+; GFX7-NOUNALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s0, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 2
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 4
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s1, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 6
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s3
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NOUNALIGNED-NEXT:    s_lshr_b32 s1, s2, 16
+; GFX7-NOUNALIGNED-NEXT:    s_add_u32 s0, s4, 10
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v0, s1
+; GFX7-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NOUNALIGNED-NEXT:    ds_write_b16 v1, v0
+; GFX7-NOUNALIGNED-NEXT:    s_endpgm
+  store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 2
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align4(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
+; GFX9-LABEL: store_lds_v3i32_align4:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v3, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    ds_write_b96 v3, v[0:2]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX7-LABEL: store_lds_v3i32_align4:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v2, s4
+; GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s1
+; GFX7-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-NEXT:    ds_write2_b32 v2, v0, v1 offset1:1
+; GFX7-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    s_endpgm
+  store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align8(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
+; GFX9-LABEL: store_lds_v3i32_align8:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v3, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    ds_write_b96 v3, v[0:2]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX7-LABEL: store_lds_v3i32_align8:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v2, s4
+; GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s1
+; GFX7-NEXT:    s_add_u32 s0, s4, 8
+; GFX7-NEXT:    ds_write_b64 v2, v[0:1]
+; GFX7-NEXT:    v_mov_b32_e32 v0, s2
+; GFX7-NEXT:    v_mov_b32_e32 v1, s0
+; GFX7-NEXT:    ds_write_b32 v1, v0
+; GFX7-NEXT:    s_endpgm
+  store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 8
+  ret void
+}
+
+define amdgpu_kernel void @store_lds_v3i32_align16(<3 x i32> addrspace(3)* %out, <3 x i32> %x) {
+; GFX9-LABEL: store_lds_v3i32_align16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x24
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v3, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    ds_write_b96 v3, v[0:2]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX7-LABEL: store_lds_v3i32_align16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x9
+; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
+; GFX7-NEXT:    s_mov_b32 m0, -1
+; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX7-NEXT:    v_mov_b32_e32 v3, s4
+; GFX7-NEXT:    v_mov_b32_e32 v0, s0
+; GFX7-NEXT:    v_mov_b32_e32 v1, s1
+; GFX7-NEXT:    v_mov_b32_e32 v2, s2
+; GFX7-NEXT:    ds_write_b96 v3, v[0:2]
+; GFX7-NEXT:    s_endpgm
+  store <3 x i32> %x, <3 x i32> addrspace(3)* %out, align 16
+  ret void
+}