diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp --- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp +++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp @@ -87,6 +87,7 @@ const TargetMachine &TM; const PPCSubtarget *PPCSubTarget; + const PPCSubtarget *Subtarget; PPCFunctionInfo *PPCFuncInfo; const TargetInstrInfo &TII; const TargetLowering &TLI; @@ -97,12 +98,12 @@ const TargetLibraryInfo *LibInfo) : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()), PPCSubTarget(&FuncInfo.MF->getSubtarget()), + Subtarget(&FuncInfo.MF->getSubtarget()), PPCFuncInfo(FuncInfo.MF->getInfo()), - TII(*PPCSubTarget->getInstrInfo()), - TLI(*PPCSubTarget->getTargetLowering()), + TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()), Context(&FuncInfo.Fn->getContext()) {} - // Backend specific FastISel code. + // Backend specific FastISel code. private: bool fastSelectInstruction(const Instruction *I) override; unsigned fastMaterializeConstant(const Constant *C) override; @@ -456,7 +457,7 @@ bool IsZExt, unsigned FP64LoadOpc) { unsigned Opc; bool UseOffset = true; - bool HasSPE = PPCSubTarget->hasSPE(); + bool HasSPE = Subtarget->hasSPE(); // If ResultReg is given, it determines the register class of the load. // Otherwise, RC is the register class to use. If the result of the @@ -498,7 +499,7 @@ UseOffset = ((Addr.Offset & 3) == 0); break; case MVT::f32: - Opc = PPCSubTarget->hasSPE() ? PPC::SPELWZ : PPC::LFS; + Opc = Subtarget->hasSPE() ? PPC::SPELWZ : PPC::LFS; break; case MVT::f64: Opc = FP64LoadOpc; @@ -614,7 +615,7 @@ Register ResultReg = 0; if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true, - PPCSubTarget->hasSPE() ? PPC::EVLDD : PPC::LFD)) + Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD)) return false; updateValueMap(I, ResultReg); return true; @@ -647,10 +648,10 @@ UseOffset = ((Addr.Offset & 3) == 0); break; case MVT::f32: - Opc = PPCSubTarget->hasSPE() ? PPC::SPESTW : PPC::STFS; + Opc = Subtarget->hasSPE() ? PPC::SPESTW : PPC::STFS; break; case MVT::f64: - Opc = PPCSubTarget->hasSPE() ? PPC::EVSTDD : PPC::STFD; + Opc = Subtarget->hasSPE() ? PPC::EVSTDD : PPC::STFD; break; } @@ -794,8 +795,9 @@ return false; BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC)) - .addImm(PPCSubTarget->hasSPE() ? PPC::PRED_SPE : PPCPred) - .addReg(CondReg).addMBB(TBB); + .addImm(Subtarget->hasSPE() ? PPC::PRED_SPE : PPCPred) + .addReg(CondReg) + .addMBB(TBB); finishCondBranch(BI->getParent(), TBB, FBB); return true; } @@ -827,7 +829,7 @@ return false; MVT SrcVT = SrcEVT.getSimpleVT(); - if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) + if (SrcVT == MVT::i1 && Subtarget->useCRBits()) return false; // See if operand 2 is an immediate encodeable in the compare. @@ -836,7 +838,7 @@ // similar to ARM in this regard. long Imm = 0; bool UseImm = false; - const bool HasSPE = PPCSubTarget->hasSPE(); + const bool HasSPE = Subtarget->hasSPE(); // Only 16-bit integer constants can be represented in compares for // PowerPC. Others will be materialized into a register. @@ -988,7 +990,7 @@ // Round the result to single precision. unsigned DestReg; auto RC = MRI.getRegClass(SrcReg); - if (PPCSubTarget->hasSPE()) { + if (Subtarget->hasSPE()) { DestReg = createResultReg(&PPC::GPRCRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::EFSCFD), DestReg) @@ -1043,10 +1045,10 @@ if (SrcVT == MVT::i32) { if (!IsSigned) { LoadOpc = PPC::LFIWZX; - Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4; - } else if (PPCSubTarget->hasLFIWAX()) { + Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4; + } else if (Subtarget->hasLFIWAX()) { LoadOpc = PPC::LFIWAX; - Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4; + Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4; } } @@ -1086,7 +1088,7 @@ return false; // Shortcut for SPE. Doesn't need to store/load, since it's all in the GPRs - if (PPCSubTarget->hasSPE()) { + if (Subtarget->hasSPE()) { unsigned Opc; if (DstVT == MVT::f32) Opc = IsSigned ? PPC::EFSCFSI : PPC::EFSCFUI; @@ -1103,7 +1105,7 @@ // We can only lower an unsigned convert if we have the newer // floating-point conversion operations. - if (!IsSigned && !PPCSubTarget->hasFPCVT()) + if (!IsSigned && !Subtarget->hasFPCVT()) return false; // FIXME: For now we require the newer floating-point conversion operations @@ -1111,7 +1113,7 @@ // to single-precision float. Otherwise we have to generate a lot of // fiddly code to avoid double rounding. If necessary, the fiddly code // can be found in PPCTargetLowering::LowerINT_TO_FP(). - if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT()) + if (DstVT == MVT::f32 && !Subtarget->hasFPCVT()) return false; // Extend the input if necessary. @@ -1168,7 +1170,7 @@ // Reload it into a GPR. If we want an i32 on big endian, modify the // address to have a 4-byte offset so we load from the right place. if (VT == MVT::i32) - Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4; + Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4; // Look at the currently assigned register for this instruction // to determine the required register class. @@ -1196,8 +1198,8 @@ return false; // If we don't have FCTIDUZ, or SPE, and we need it, punt to SelectionDAG. - if (DstVT == MVT::i64 && !IsSigned && - !PPCSubTarget->hasFPCVT() && !PPCSubTarget->hasSPE()) + if (DstVT == MVT::i64 && !IsSigned && !Subtarget->hasFPCVT() && + !Subtarget->hasSPE()) return false; Value *Src = I->getOperand(0); @@ -1226,7 +1228,7 @@ unsigned Opc; auto RC = MRI.getRegClass(SrcReg); - if (PPCSubTarget->hasSPE()) { + if (Subtarget->hasSPE()) { DestReg = createResultReg(&PPC::GPRCRegClass); if (IsSigned) Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ; @@ -1234,7 +1236,7 @@ Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ; } else if (isVSFRCRegClass(RC)) { DestReg = createResultReg(&PPC::VSFRCRegClass); - if (DstVT == MVT::i32) + if (DstVT == MVT::i32) Opc = IsSigned ? PPC::XSCVDPSXWS : PPC::XSCVDPUXWS; else Opc = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS; @@ -1244,7 +1246,7 @@ if (IsSigned) Opc = PPC::FCTIWZ; else - Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ; + Opc = Subtarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ; else Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ; } @@ -1254,8 +1256,9 @@ .addReg(SrcReg); // Now move the integer value from a float register to an integer register. - unsigned IntReg = PPCSubTarget->hasSPE() ? DestReg : - PPCMoveToIntReg(I, DstVT, DestReg, IsSigned); + unsigned IntReg = Subtarget->hasSPE() + ? DestReg + : PPCMoveToIntReg(I, DstVT, DestReg, IsSigned); if (IntReg == 0) return false; @@ -1383,7 +1386,7 @@ CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context); // Reserve space for the linkage area on the stack. - unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize(); + unsigned LinkageSize = Subtarget->getFrameLowering()->getLinkageSize(); CCInfo.AllocateStack(LinkageSize, Align(8)); CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS); @@ -1573,7 +1576,7 @@ else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 && RetVT != MVT::i8) return false; - else if (RetVT == MVT::i1 && PPCSubTarget->useCRBits()) + else if (RetVT == MVT::i1 && Subtarget->useCRBits()) // We can't handle boolean returns when CR bits are in use. return false; @@ -1995,7 +1998,7 @@ // All FP constants are loaded from the constant pool. Align Alignment = DL.getPrefTypeAlign(CFP->getType()); unsigned Idx = MCP.getConstantPoolIndex(cast(CFP), Alignment); - const bool HasSPE = PPCSubTarget->hasSPE(); + const bool HasSPE = Subtarget->hasSPE(); const TargetRegisterClass *RC; if (HasSPE) RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass); @@ -2089,7 +2092,7 @@ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8), HighPartReg).addReg(PPC::X2).addGlobalAddress(GV); - if (PPCSubTarget->isGVIndirectSymbol(GV)) { + if (Subtarget->isGVIndirectSymbol(GV)) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL), DestReg).addGlobalAddress(GV).addReg(HighPartReg); } else { @@ -2196,7 +2199,7 @@ bool UseSExt) { // If we're using CR bit registers for i1 values, handle that as a special // case first. - if (VT == MVT::i1 && PPCSubTarget->useCRBits()) { + if (VT == MVT::i1 && Subtarget->useCRBits()) { unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg); @@ -2351,7 +2354,7 @@ Register ResultReg = MI->getOperand(0).getReg(); if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt, - PPCSubTarget->hasSPE() ? PPC::EVLDD : PPC::LFD)) + Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD)) return false; MachineBasicBlock::iterator I(MI); @@ -2378,7 +2381,7 @@ // If we're using CR bit registers for i1 values, handle that as a special // case first. - if (VT == MVT::i1 && PPCSubTarget->useCRBits()) { + if (VT == MVT::i1 && Subtarget->useCRBits()) { unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg); diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -139,6 +139,7 @@ class PPCDAGToDAGISel : public SelectionDAGISel { const PPCTargetMachine &TM; const PPCSubtarget *PPCSubTarget = nullptr; + const PPCSubtarget *Subtarget = nullptr; const PPCTargetLowering *PPCLowering = nullptr; unsigned GlobalBaseReg = 0; @@ -150,10 +151,11 @@ // Make sure we re-emit a set of the global base reg if necessary GlobalBaseReg = 0; PPCSubTarget = &MF.getSubtarget(); - PPCLowering = PPCSubTarget->getTargetLowering(); + Subtarget = &MF.getSubtarget(); + PPCLowering = Subtarget->getTargetLowering(); SelectionDAGISel::runOnMachineFunction(MF); - if (!PPCSubTarget->isSVR4ABI()) + if (!Subtarget->isSVR4ABI()) InsertVRSaveCode(MF); return true; @@ -266,7 +268,7 @@ bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) { return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG); } - + /// SelectAddrImm - Returns true if the address N can be represented by /// a base register plus a signed 16-bit displacement [r+imm]. /// The last parameter \p 0 means D form has no requirment for 16 bit signed @@ -320,7 +322,7 @@ case InlineAsm::Constraint_Zy: // We need to make sure that this one operand does not end up in r0 // (because we might end up lowering this as 0(%op)). - const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo(); + const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo(); const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1); SDLoc dl(Op); SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); @@ -404,7 +406,7 @@ Register InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); Register UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); - const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); MachineBasicBlock &EntryBB = *Fn.begin(); DebugLoc dl; // Emit the following code into the entry block: @@ -439,7 +441,7 @@ /// SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { if (!GlobalBaseReg) { - const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = MF->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); @@ -447,9 +449,9 @@ DebugLoc dl; if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) == MVT::i32) { - if (PPCSubTarget->isTargetELF()) { + if (Subtarget->isTargetELF()) { GlobalBaseReg = PPC::R30; - if (!PPCSubTarget->isSecurePlt() && + if (!Subtarget->isSecurePlt() && M->getPICLevel() == PICLevel::SmallPIC) { BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR)); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); @@ -3798,7 +3800,7 @@ Opc = PPC::CMPD; } } else if (LHS.getValueType() == MVT::f32) { - if (PPCSubTarget->hasSPE()) { + if (Subtarget->hasSPE()) { switch (CC) { default: case ISD::SETEQ: @@ -3825,7 +3827,7 @@ } else Opc = PPC::FCMPUS; } else if (LHS.getValueType() == MVT::f64) { - if (PPCSubTarget->hasSPE()) { + if (Subtarget->hasSPE()) { switch (CC) { default: case ISD::SETEQ: @@ -3850,10 +3852,10 @@ break; } } else - Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD; + Opc = Subtarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD; } else { assert(LHS.getValueType() == MVT::f128 && "Unknown vt!"); - assert(PPCSubTarget->hasVSX() && "__float128 requires VSX"); + assert(Subtarget->hasVSX() && "__float128 requires VSX"); Opc = PPC::XSCMPUQP; } return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0); @@ -4048,8 +4050,7 @@ CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout()); bool isPPC64 = (PtrVT == MVT::i64); - if (!PPCSubTarget->useCRBits() && - isInt32Immediate(N->getOperand(1), Imm)) { + if (!Subtarget->useCRBits() && isInt32Immediate(N->getOperand(1), Imm)) { // We can codegen setcc op, imm very efficiently compared to a brcond. // Check for those cases here. // setcc op, 0 @@ -4138,20 +4139,20 @@ // Altivec Vector compare instructions do not set any CR register by default and // vector compare operations return the same type as the operands. if (LHS.getValueType().isVector()) { - if (PPCSubTarget->hasQPX() || PPCSubTarget->hasSPE()) + if (Subtarget->hasQPX() || Subtarget->hasSPE()) return false; EVT VecVT = LHS.getValueType(); bool Swap, Negate; - unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC, - PPCSubTarget->hasVSX(), Swap, Negate); + unsigned int VCmpInst = + getVCmpInst(VecVT.getSimpleVT(), CC, Subtarget->hasVSX(), Swap, Negate); if (Swap) std::swap(LHS, RHS); EVT ResVT = VecVT.changeVectorElementTypeToInteger(); if (Negate) { SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); - CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR, + CurDAG->SelectNodeTo(N, Subtarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR, ResVT, VCmp, VCmp); return true; } @@ -4160,7 +4161,7 @@ return true; } - if (PPCSubTarget->useCRBits()) + if (Subtarget->useCRBits()) return false; bool Inv; @@ -4170,7 +4171,7 @@ // SPE e*cmp* instructions only set the 'gt' bit, so hard-code that // The correct compare instruction is already set by SelectCC() - if (PPCSubTarget->hasSPE() && LHS.getValueType().isFloatingPoint()) { + if (Subtarget->hasSPE() && LHS.getValueType().isFloatingPoint()) { Idx = 1; } @@ -4667,7 +4668,7 @@ case PPCISD::ADDI_TLSGD_L_ADDR: { const Module *Mod = MF->getFunction().getParent(); if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) != MVT::i32 || - !PPCSubTarget->isSecurePlt() || !PPCSubTarget->isTargetELF() || + !Subtarget->isSecurePlt() || !Subtarget->isTargetELF() || Mod->getPICLevel() == PICLevel::SmallPIC) break; // Attach global base pointer on GETtlsADDR32 node in order to @@ -4676,8 +4677,8 @@ } break; case PPCISD::CALL: { if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) != MVT::i32 || - !TM.isPositionIndependent() || !PPCSubTarget->isSecurePlt() || - !PPCSubTarget->isTargetELF()) + !TM.isPositionIndependent() || !Subtarget->isSecurePlt() || + !Subtarget->isTargetELF()) break; SDValue Op = N->getOperand(1); @@ -4741,7 +4742,7 @@ case ISD::STORE: { // Change TLS initial-exec D-form stores to X-form stores. StoreSDNode *ST = cast(N); - if (EnableTLSOpt && PPCSubTarget->isELFv2ABI() && + if (EnableTLSOpt && Subtarget->isELFv2ABI() && ST->getAddressingMode() != ISD::PRE_INC) if (tryTLSXFormStore(ST)) return; @@ -4755,7 +4756,7 @@ // Normal loads are handled by code generated from the .td file. if (LD->getAddressingMode() != ISD::PRE_INC) { // Change TLS initial-exec D-form loads to X-form loads. - if (EnableTLSOpt && PPCSubTarget->isELFv2ABI()) + if (EnableTLSOpt && Subtarget->isELFv2ABI()) if (tryTLSXFormLoad(LD)) return; break; @@ -4878,7 +4879,7 @@ // OR with a 32-bit immediate can be handled by ori + oris // without creating an immediate in a GPR. uint64_t Imm64 = 0; - bool IsPPC64 = PPCSubTarget->isPPC64(); + bool IsPPC64 = Subtarget->isPPC64(); if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) && (Imm64 & ~0xFFFFFFFFuLL) == 0) { // If ImmHi (ImmHi) is zero, only one ori (oris) is generated later. @@ -4901,7 +4902,7 @@ // XOR with a 32-bit immediate can be handled by xori + xoris // without creating an immediate in a GPR. uint64_t Imm64 = 0; - bool IsPPC64 = PPCSubTarget->isPPC64(); + bool IsPPC64 = Subtarget->isPPC64(); if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) && (Imm64 & ~0xFFFFFFFFuLL) == 0) { // If ImmHi (ImmHi) is zero, only one xori (xoris) is generated later. @@ -4988,11 +4989,10 @@ bool isPPC64 = (PtrVT == MVT::i64); // If this is a select of i1 operands, we'll pattern match it. - if (PPCSubTarget->useCRBits() && - N->getOperand(0).getValueType() == MVT::i1) + if (Subtarget->useCRBits() && N->getOperand(0).getValueType() == MVT::i1) break; - if (PPCSubTarget->isISA3_0() && PPCSubTarget->isPPC64()) { + if (Subtarget->isISA3_0() && Subtarget->isPPC64()) { bool NeedSwapOps = false; bool IsUnCmp = false; if (mayUseP9Setb(N, CC, CurDAG, NeedSwapOps, IsUnCmp)) { @@ -5067,7 +5067,7 @@ } unsigned BROpc = - getPredicateForSetCC(CC, N->getOperand(0).getValueType(), PPCSubTarget); + getPredicateForSetCC(CC, N->getOperand(0).getValueType(), Subtarget); unsigned SelectCCOp; if (N->getValueType(0) == MVT::i32) @@ -5075,28 +5075,28 @@ else if (N->getValueType(0) == MVT::i64) SelectCCOp = PPC::SELECT_CC_I8; else if (N->getValueType(0) == MVT::f32) { - if (PPCSubTarget->hasP8Vector()) + if (Subtarget->hasP8Vector()) SelectCCOp = PPC::SELECT_CC_VSSRC; - else if (PPCSubTarget->hasSPE()) + else if (Subtarget->hasSPE()) SelectCCOp = PPC::SELECT_CC_SPE4; else SelectCCOp = PPC::SELECT_CC_F4; } else if (N->getValueType(0) == MVT::f64) { - if (PPCSubTarget->hasVSX()) + if (Subtarget->hasVSX()) SelectCCOp = PPC::SELECT_CC_VSFRC; - else if (PPCSubTarget->hasSPE()) + else if (Subtarget->hasSPE()) SelectCCOp = PPC::SELECT_CC_SPE; else SelectCCOp = PPC::SELECT_CC_F8; } else if (N->getValueType(0) == MVT::f128) SelectCCOp = PPC::SELECT_CC_F16; - else if (PPCSubTarget->hasSPE()) + else if (Subtarget->hasSPE()) SelectCCOp = PPC::SELECT_CC_SPE; - else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64) + else if (Subtarget->hasQPX() && N->getValueType(0) == MVT::v4f64) SelectCCOp = PPC::SELECT_CC_QFRC; - else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32) + else if (Subtarget->hasQPX() && N->getValueType(0) == MVT::v4f32) SelectCCOp = PPC::SELECT_CC_QSRC; - else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1) + else if (Subtarget->hasQPX() && N->getValueType(0) == MVT::v4i1) SelectCCOp = PPC::SELECT_CC_QBRC; else if (N->getValueType(0) == MVT::v2f64 || N->getValueType(0) == MVT::v2i64) @@ -5110,8 +5110,8 @@ return; } case ISD::VECTOR_SHUFFLE: - if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 || - N->getValueType(0) == MVT::v2i64)) { + if (Subtarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 || + N->getValueType(0) == MVT::v2i64)) { ShuffleVectorSDNode *SVN = cast(N); SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1), @@ -5146,7 +5146,7 @@ // For little endian, we must swap the input operands and adjust // the mask elements (reverse and invert them). - if (PPCSubTarget->isLittleEndian()) { + if (Subtarget->isLittleEndian()) { std::swap(Op1, Op2); unsigned tmp = DM[0]; DM[0] = 1 - DM[1]; @@ -5163,7 +5163,7 @@ break; case PPCISD::BDNZ: case PPCISD::BDZ: { - bool IsPPC64 = PPCSubTarget->isPPC64(); + bool IsPPC64 = Subtarget->isPPC64(); SDValue Ops[] = { N->getOperand(1), N->getOperand(0) }; CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ? (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) @@ -5191,7 +5191,7 @@ case ISD::BR_CC: { ISD::CondCode CC = cast(N->getOperand(1))->get(); unsigned PCC = - getPredicateForSetCC(CC, N->getOperand(2).getValueType(), PPCSubTarget); + getPredicateForSetCC(CC, N->getOperand(2).getValueType(), Subtarget); if (N->getOperand(2).getValueType() == MVT::i1) { unsigned Opc; @@ -5244,9 +5244,9 @@ return; } case PPCISD::TOC_ENTRY: { - const bool isPPC64 = PPCSubTarget->isPPC64(); - const bool isELFABI = PPCSubTarget->isSVR4ABI(); - const bool isAIXABI = PPCSubTarget->isAIXABI(); + const bool isPPC64 = Subtarget->isPPC64(); + const bool isELFABI = Subtarget->isSVR4ABI(); + const bool isAIXABI = Subtarget->isAIXABI(); // PowerPC only support small, medium and large code model. const CodeModel::Model CModel = TM.getCodeModel(); @@ -5297,7 +5297,7 @@ // or 64-bit medium (ELF-only) or large (ELF and AIX) code model code. We // generate two instructions as described below. The first source operand // is a symbol reference. If it must be toc-referenced according to - // PPCSubTarget, we generate: + // Subtarget, we generate: // [32-bit AIX] // LWZtocL(@sym, ADDIStocHA(%r2, @sym)) // [64-bit ELF/AIX] @@ -5329,7 +5329,7 @@ } case PPCISD::PPC32_PICGOT: // Generate a PIC-safe GOT reference. - assert(PPCSubTarget->is32BitELFABI() && + assert(Subtarget->is32BitELFABI() && "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4"); CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(CurDAG->getDataLayout()), @@ -5426,7 +5426,7 @@ "Only OR nodes are supported for CMPB"); SDValue Res; - if (!PPCSubTarget->hasCMPB()) + if (!Subtarget->hasCMPB()) return Res; if (N->getValueType(0) != MVT::i32 && @@ -5637,7 +5637,7 @@ // only one instruction (like a zero or one), then we should fold in those // operations with the select. void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) { - if (!PPCSubTarget->useCRBits()) + if (!Subtarget->useCRBits()) return; if (N->getOpcode() != ISD::ZERO_EXTEND && @@ -6378,7 +6378,7 @@ } void PPCDAGToDAGISel::PeepholePPC64ZExt() { - if (!PPCSubTarget->isPPC64()) + if (!Subtarget->isPPC64()) return; // When we zero-extend from i32 to i64, we use a pattern like this: diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -341,7 +341,7 @@ //===----------------------------------------------------------------------===// // Instruction Definitions. -def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; +def HasAltivec : Predicate<"Subtarget->hasAltivec()">; let Predicates = [HasAltivec] in { def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), @@ -491,7 +491,7 @@ def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vaddfp $vD, $vA, $vB", IIC_VecFP, [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; - + def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vaddubm $vD, $vA, $vB", IIC_VecGeneral, [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; @@ -501,7 +501,7 @@ def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vadduwm $vD, $vA, $vB", IIC_VecGeneral, [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; - + def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; @@ -635,7 +635,7 @@ def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, v4i32, v8i16>; } // isCommutable - + def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; @@ -657,7 +657,7 @@ def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; - + def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; @@ -1022,7 +1022,7 @@ def : Pat<(fmul v4f32:$vA, v4f32:$vB), (VMADDFP $vA, $vB, - (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; + (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C), (VNMSUBFP $A, $B, $C)>; @@ -1136,8 +1136,8 @@ } // end HasAltivec -def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">; -def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">; +def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">; +def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">; let Predicates = [HasP8Altivec] in { let isCommutable = 1 in { @@ -1158,7 +1158,7 @@ def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; } // isCommutable -// Vector merge +// Vector merge def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vmrgew $vD, $vA, $vB", IIC_VecFP, [(set v16i8:$vD, @@ -1266,16 +1266,16 @@ [(set v2i64:$vD, (ctpop v2i64:$vB))]>; let isCommutable = 1 in { -// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the +// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the // VSX equivalents. We need to fix this up at some point. Two possible // solutions for this problem: // 1. Disable Altivec patterns that compete with VSX patterns using the -// !HasVSX predicate. This essentially favours VSX over Altivec, in -// hopes of reducing register pressure (larger register set using VSX +// !HasVSX predicate. This essentially favours VSX over Altivec, in +// hopes of reducing register pressure (larger register set using VSX // instructions than VMX instructions) // 2. Employ a more disciplined use of AddedComplexity, which would provide // more fine-grained control than option 1. This would be beneficial -// if we find situations where Altivec is really preferred over VSX. +// if we find situations where Altivec is really preferred over VSX. def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "veqv $vD, $vA, $vB", IIC_VecGeneral, [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; @@ -1354,7 +1354,7 @@ } // HasP8Crypto // The following altivec instructions were introduced in Power ISA 3.0 -def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">; +def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">; let Predicates = [HasP9Altivec] in { // Vector Multiply-Sum diff --git a/llvm/lib/Target/PowerPC/PPCInstrHTM.td b/llvm/lib/Target/PowerPC/PPCInstrHTM.td --- a/llvm/lib/Target/PowerPC/PPCInstrHTM.td +++ b/llvm/lib/Target/PowerPC/PPCInstrHTM.td @@ -13,7 +13,7 @@ -def HasHTM : Predicate<"PPCSubTarget->hasHTM()">; +def HasHTM : Predicate<"Subtarget->hasHTM()">; def HTM_get_imm : SDNodeXFormgetZExtValue(), SDLoc(N)); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -158,9 +158,9 @@ def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; -def PPCfsel : SDNode<"PPCISD::FSEL", +def PPCfsel : SDNode<"PPCISD::FSEL", // Type constraint for fsel. - SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, + SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; def PPCxsmaxc : SDNode<"PPCISD::XSMAXCDP", SDT_PPCFPMinMax, []>; def PPCxsminc : SDNode<"PPCISD::XSMINCDP", SDT_PPCFPMinMax, []>; @@ -389,7 +389,7 @@ // field. Used by instructions like 'ori'. return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); }], LO16>; -def immNonAllOneAnyExt8 : ImmLeaf(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); }]>; def immSExt5NonZero : ImmLeaf(Imm); }]>; @@ -407,7 +407,7 @@ def imm16ShiftedSExt : PatLeaf<(imm), [{ // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the - // immediate are set. Used by instructions like 'addis'. Identical to + // immediate are set. Used by instructions like 'addis'. Identical to // imm16ShiftedZExt in 32-bit mode. if (N->getZExtValue() & 0xFFFF) return false; if (N->getValueType(0) == MVT::i32) @@ -986,25 +986,25 @@ //===----------------------------------------------------------------------===// // PowerPC Instruction Predicate Definitions. -def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">; -def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">; -def IsBookE : Predicate<"PPCSubTarget->isBookE()">; -def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">; -def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">; -def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">; -def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">; -def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">; -def IsE500 : Predicate<"PPCSubTarget->isE500()">; -def HasSPE : Predicate<"PPCSubTarget->hasSPE()">; -def HasICBT : Predicate<"PPCSubTarget->hasICBT()">; -def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">; +def In32BitMode : Predicate<"!Subtarget->isPPC64()">; +def In64BitMode : Predicate<"Subtarget->isPPC64()">; +def IsBookE : Predicate<"Subtarget->isBookE()">; +def IsNotBookE : Predicate<"!Subtarget->isBookE()">; +def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; +def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; +def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; +def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; +def IsE500 : Predicate<"Subtarget->isE500()">; +def HasSPE : Predicate<"Subtarget->hasSPE()">; +def HasICBT : Predicate<"Subtarget->hasICBT()">; +def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">; -def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">; -def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">; -def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">; -def HasFPU : Predicate<"PPCSubTarget->hasFPU()">; -def PCRelativeMemops : Predicate<"PPCSubTarget->hasPCRelativeMemops()">; +def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; +def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; +def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; +def HasFPU : Predicate<"Subtarget->hasFPU()">; +def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; //===----------------------------------------------------------------------===// // PowerPC Multiclass Definitions. @@ -1374,7 +1374,7 @@ (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; - + // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after // instruction selection into a branch sequence. let PPC970_Single = 1 in { @@ -1468,7 +1468,7 @@ } // Set the float rounding mode. -let Uses = [RM], Defs = [RM] in { +let Uses = [RM], Defs = [RM] in { def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; @@ -2027,7 +2027,7 @@ // PPC32 Load Instructions. // -// Unindexed (r+i) Loads. +// Unindexed (r+i) Loads. let PPC970_Unit = 2 in { def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), "lbz $rD, $src", IIC_LdStLoad, @@ -2170,7 +2170,7 @@ } // Load Multiple -let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in +let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), "lmw $rD, $src", IIC_LdStLMW, []>; @@ -2871,7 +2871,7 @@ // The above pseudo gets expanded to make use of the following instructions // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. -let Uses = [RM], Defs = [RM] in { +let Uses = [RM], Defs = [RM] in { def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), "mtfsb0 $FM", IIC_IntMTFSB0, []>, PPC970_DGroup_Single, PPC970_Unit_FPU; @@ -3018,7 +3018,7 @@ let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. let Uses = [RM] in { let isCommutable = 1 in { - defm FMADD : AForm_1r<63, 29, + defm FMADD : AForm_1r<63, 29, (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; @@ -3239,13 +3239,13 @@ (ADDIS $in, tblockaddress:$g)>; // Support for thread-local storage. -def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", +def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", [(set i32:$rD, (PPCppc32GOT))]>; // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. // This uses two output registers, the first as the real output, the second as a // temporary register, used internally in code generation. -def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", +def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", []>, NoEncode<"$rT">; def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), @@ -3599,7 +3599,7 @@ (RLWINM (CNTLZW $in), 27, 31, 31)>, OutPatFrag<(ops node:$in), (RLDICL (CNTLZD $in), 58, 63)> >; - + defm : ExtSetCCPat, @@ -3607,7 +3607,7 @@ (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, OutPatFrag<(ops node:$in), (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; - + defm : ExtSetCCPat, diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -190,8 +190,8 @@ isPCRel; } -def PrefixInstrs : Predicate<"PPCSubTarget->hasPrefixInstrs()">; -def IsISA3_1 : Predicate<"PPCSubTarget->isISA3_1()">; +def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; +def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; let Predicates = [PrefixInstrs] in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { diff --git a/llvm/lib/Target/PowerPC/PPCInstrQPX.td b/llvm/lib/Target/PowerPC/PPCInstrQPX.td --- a/llvm/lib/Target/PowerPC/PPCInstrQPX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrQPX.td @@ -1,9 +1,9 @@ //===- PPCInstrQPX.td - The PowerPC QPX Extension --*- tablegen -*-===// -// +// // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// +// //===----------------------------------------------------------------------===// // // This file describes the QPX extension to the PowerPC instruction set. @@ -101,7 +101,7 @@ //===----------------------------------------------------------------------===// // Instruction Definitions. -def HasQPX : Predicate<"PPCSubTarget->hasQPX()">; +def HasQPX : Predicate<"Subtarget->hasQPX()">; let Predicates = [HasQPX] in { let DecoderNamespace = "QPX" in { let hasSideEffects = 0 in { // QPX instructions don't have side effects. @@ -1210,4 +1210,3 @@ (QVFTSTNANbs $FRB, $FRB), (i32 7)), $FRB, $FRA)>; } - diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -1,9 +1,9 @@ //===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===// -// +// // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// +// //===----------------------------------------------------------------------===// // // This file describes the VSX extension to the PowerPC instruction set. @@ -142,15 +142,15 @@ SDTypeProfile<1, 1, []>, []>; //-------------------------- Predicate definitions ---------------------------// -def HasVSX : Predicate<"PPCSubTarget->hasVSX()">; -def IsLittleEndian : Predicate<"PPCSubTarget->isLittleEndian()">; -def IsBigEndian : Predicate<"!PPCSubTarget->isLittleEndian()">; -def HasOnlySwappingMemOps : Predicate<"!PPCSubTarget->hasP9Vector()">; -def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">; -def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">; -def NoP9Vector : Predicate<"!PPCSubTarget->hasP9Vector()">; -def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">; -def NoP9Altivec : Predicate<"!PPCSubTarget->hasP9Altivec()">; +def HasVSX : Predicate<"Subtarget->hasVSX()">; +def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">; +def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">; +def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">; +def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">; +def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">; +def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">; +def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">; +def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">; //--------------------- VSX-specific instruction formats ---------------------// // By default, all VSX instructions are to be selected over their Altivec