diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -111,6 +111,16 @@
     VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
     VE::SF63};
 
+static const MCPhysReg MISCRegs[31] = {
+    VE::USRCC,      VE::PSW,        VE::SAR,        VE::NoRegister,
+    VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
+    VE::PMCR0,      VE::PMCR1,      VE::PMCR2,      VE::PMCR3,
+    VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
+    VE::PMC0,       VE::PMC1,       VE::PMC2,       VE::PMC3,
+    VE::PMC4,       VE::PMC5,       VE::PMC6,       VE::PMC7,
+    VE::PMC8,       VE::PMC9,       VE::PMC10,      VE::PMC11,
+    VE::PMC12,      VE::PMC13,      VE::PMC14};
+
 namespace {
 
 /// VEOperand - Instances of this class represent a parsed VE machine
@@ -191,12 +201,45 @@
   bool isMEMri() const { return Kind == k_MemoryRegImm; }
   bool isMEMzi() const { return Kind == k_MemoryZeroImm; }
   bool isCCOp() const { return Kind == k_CCOp; }
+  bool isZero() {
+    if (!isImm())
+      return false;
+
+    // Constant case
+    if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+      int64_t Value = ConstExpr->getValue();
+      return Value == 0;
+    }
+    return false;
+  }
+  bool isUImm3() {
+    if (!isImm())
+      return false;
+
+    // Constant case
+    if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+      int64_t Value = ConstExpr->getValue();
+      return isUInt<3>(Value);
+    }
+    return false;
+  }
+  bool isUImm6() {
+    if (!isImm())
+      return false;
+
+    // Constant case
+    if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+      int64_t Value = ConstExpr->getValue();
+      return isUInt<6>(Value);
+    }
+    return false;
+  }
   bool isUImm7() {
     if (!isImm())
       return false;
 
     // Constant case
-    if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+    if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
       int64_t Value = ConstExpr->getValue();
       return isUInt<7>(Value);
     }
@@ -207,7 +250,7 @@
       return false;
 
     // Constant case
-    if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+    if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
       int64_t Value = ConstExpr->getValue();
       return isInt<7>(Value);
     }
@@ -218,7 +261,7 @@
       return false;
 
     // Constant case
-    if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(MImm.Val)) {
+    if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(MImm.Val)) {
       int64_t Value = ConstExpr->getValue();
       return isUInt<6>(Value);
     }
@@ -351,10 +394,21 @@
     addExpr(Inst, Expr);
   }
 
-  void addUImm7Operands(MCInst &Inst, unsigned N) const {
+  void addZeroOperands(MCInst &Inst, unsigned N) const {
+    addImmOperands(Inst, N);
+  }
+
+  void addUImm3Operands(MCInst &Inst, unsigned N) const {
+    addImmOperands(Inst, N);
+  }
+
+  void addUImm6Operands(MCInst &Inst, unsigned N) const {
     addImmOperands(Inst, N);
   }
 
+  void addUImm7Operands(MCInst &Inst, unsigned N) const {
+    addImmOperands(Inst, N);
+  }
   void addSImm7Operands(MCInst &Inst, unsigned N) const {
     addImmOperands(Inst, N);
   }
@@ -363,7 +417,7 @@
     // Add as immediate when possible.  Null MCExpr = 0.
     if (!Expr)
       Inst.addOperand(MCOperand::createImm(0));
-    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
+    else if (const auto *CE = dyn_cast<MCConstantExpr>(Expr))
       Inst.addOperand(MCOperand::createImm(CE->getValue()));
     else
       Inst.addOperand(MCOperand::createExpr(Expr));
@@ -495,6 +549,18 @@
     return true;
   }
 
+  static bool MorphToMISCReg(VEOperand &Op) {
+    const auto *ConstExpr = dyn_cast<MCConstantExpr>(Op.getImm());
+    if (!ConstExpr)
+      return false;
+    unsigned regIdx = ConstExpr->getValue();
+    if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)
+      return false;
+    Op.Kind = k_Register;
+    Op.Reg.RegNum = MISCRegs[regIdx];
+    return true;
+  }
+
   static std::unique_ptr<VEOperand>
   MorphToMEMri(unsigned Base, std::unique_ptr<VEOperand> Op) {
     const MCExpr *Imm = Op->getImm();
@@ -1097,6 +1163,10 @@
     if (Op.isReg() && VEOperand::MorphToI32Reg(Op))
       return MCTargetAsmParser::Match_Success;
     break;
+  case MCK_MISC:
+    if (Op.isImm() && VEOperand::MorphToMISCReg(Op))
+      return MCTargetAsmParser::Match_Success;
+    break;
   }
   return Match_InvalidOperand;
 }
diff --git a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
--- a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
+++ b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
@@ -89,6 +89,16 @@
     VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
     VE::SF63};
 
+static const unsigned MiscRegDecoderTable[] = {
+    VE::USRCC,      VE::PSW,        VE::SAR,        VE::NoRegister,
+    VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
+    VE::PMCR0,      VE::PMCR1,      VE::PMCR2,      VE::PMCR3,
+    VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
+    VE::PMC0,       VE::PMC1,       VE::PMC2,       VE::PMC3,
+    VE::PMC4,       VE::PMC5,       VE::PMC6,       VE::PMC7,
+    VE::PMC8,       VE::PMC9,       VE::PMC10,      VE::PMC11,
+    VE::PMC12,      VE::PMC13,      VE::PMC14};
+
 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
                                            const void *Decoder) {
@@ -119,6 +129,18 @@
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if (RegNo > 30)
+    return MCDisassembler::Fail;
+  unsigned Reg = MiscRegDecoderTable[RegNo];
+  if (Reg == VE::NoRegister)
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
--- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
@@ -38,6 +38,9 @@
 void VEInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   // Generic registers have identical register name among register classes.
   unsigned AltIdx = VE::AsmName;
+  // Misc registers have each own name, so no use alt-names.
+  if (MRI.getRegClass(VE::MISCRegClassID).contains(RegNo))
+    AltIdx = VE::NoRegAltName;
   OS << '%' << getRegisterName(RegNo, AltIdx);
 }
 
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -112,13 +112,36 @@
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
 
+// zero
+def ZeroAsmOperand : AsmOperandClass {
+  let Name = "Zero";
+}
+def zero : Operand<i32>, PatLeaf<(imm), [{
+    return N->getSExtValue() == 0; }]> {
+  let ParserMatchClass = ZeroAsmOperand;
+}
+
 // uimm1 - Generic immediate value.
 def uimm1 : Operand<i32>, PatLeaf<(imm), [{
     return isUInt<1>(N->getZExtValue()); }]>;
 
+// uimm3 - Generic immediate value.
+def UImm3AsmOperand : AsmOperandClass {
+  let Name = "UImm3";
+}
+def uimm3 : Operand<i32>, PatLeaf<(imm), [{
+    return isUInt<3>(N->getZExtValue()); }], ULO7> {
+  let ParserMatchClass = UImm3AsmOperand;
+}
+
 // uimm6 - Generic immediate value.
+def UImm6AsmOperand : AsmOperandClass {
+  let Name = "UImm6";
+}
 def uimm6 : Operand<i32>, PatLeaf<(imm), [{
-    return isUInt<6>(N->getZExtValue()); }]>;
+    return isUInt<6>(N->getZExtValue()); }], ULO7> {
+  let ParserMatchClass = UImm6AsmOperand;
+}
 
 // uimm7 - Generic immediate value.
 def UImm7AsmOperand : AsmOperandClass {
@@ -700,6 +723,46 @@
   defm na : BCRbpfm<opcStrAf, "", opc, (ins)>;
 }
 
+// Multiclass for communication register instructions.
+//   e.g. LCR
+let hasSideEffects = 1 in
+multiclass LOADCRm<string opcStr, bits<8>opc, RegisterClass RC> {
+  def rr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$sy),
+              !strconcat(opcStr, " $sx, $sy, $sz")>;
+  let cy = 0 in def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, simm7:$sy),
+                            !strconcat(opcStr, " $sx, $sy, $sz")>;
+  let cz = 0 in def zr : RR<opc, (outs RC:$sx), (ins zero:$sz, RC:$sy),
+                            !strconcat(opcStr, " $sx, $sy, $sz")>;
+  let cy = 0, cz = 0 in
+  def zi : RR<opc, (outs RC:$sx), (ins zero:$sz, simm7:$sy),
+              !strconcat(opcStr, " $sx, $sy, $sz")>;
+}
+
+// Multiclass for communication register instructions.
+//   e.g. SCR
+let hasSideEffects = 1 in
+multiclass STORECRm<string opcStr, bits<8>opc, RegisterClass RC> {
+  def rr : RR<opc, (outs), (ins RC:$sz, RC:$sy, RC:$sx),
+              !strconcat(opcStr, " $sx, $sy, $sz")>;
+  let cy = 0 in def ri : RR<opc, (outs), (ins RC:$sz, simm7:$sy, RC:$sx),
+                            !strconcat(opcStr, " $sx, $sy, $sz")>;
+  let cz = 0 in def zr : RR<opc, (outs), (ins zero:$sz, RC:$sy, RC:$sx),
+                            !strconcat(opcStr, " $sx, $sy, $sz")>;
+  let cy = 0, cz = 0 in
+  def zi : RR<opc, (outs), (ins zero:$sz, simm7:$sy, RC:$sx),
+              !strconcat(opcStr, " $sx, $sy, $sz")>;
+}
+
+// Multiclass for communication register instructions.
+//   e.g. FIDCR
+let cz = 0, hasSideEffects = 1 in
+multiclass FIDCRm<string opcStr, bits<8>opc, RegisterClass RC> {
+  def ri : RR<opc, (outs RC:$sx), (ins RC:$sy, uimm3:$sz),
+              !strconcat(opcStr, " $sx, $sy, $sz")>;
+  let cy = 0 in def ii : RR<opc, (outs RC:$sx), (ins simm7:$sy, uimm3:$sz),
+                            !strconcat(opcStr, " $sx, $sy, $sz")>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //
@@ -1143,6 +1206,59 @@
 def CALLr : RM<0x08, (outs), (ins I64:$sz, variable_ops),
                "bsic %s10, (, $sz)", [(call i64:$sz)]>;
 
+//-----------------------------------------------------------------------------
+// Section 8.19 - Control Instructions
+//-----------------------------------------------------------------------------
+
+// Section 8.19.1 - SIC (Save Instruction Counter)
+let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [IC] in
+def SIC : RR<0x28, (outs I32:$sx), (ins), "sic $sx">;
+
+// Section 8.19.2 - LPM (Load Program Mode Flags)
+let sx = 0, cz = 0, sz = 0, hasSideEffects = 1, Defs = [PSW] in
+def LPM : RR<0x3a, (outs), (ins I64:$sy), "lpm $sy">;
+
+// Section 8.19.3 - SPM (Save Program Mode Flags)
+let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [PSW] in
+def SPM : RR<0x2a, (outs I64:$sx), (ins), "spm $sx">;
+
+// Section 8.19.4 - LFR (Load Flag Register)
+let sx = 0, cz = 0, sz = 0, hasSideEffects = 1, Defs = [PSW] in {
+  def LFRr : RR<0x69, (outs), (ins I64:$sy), "lfr $sy">;
+  let cy = 0 in def LFRi : RR<0x69, (outs), (ins uimm6:$sy), "lfr $sy">;
+}
+
+// Section 8.19.5 - SFR (Save Flag Register)
+let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1, Uses = [PSW] in
+def SFR : RR<0x29, (outs I64:$sx), (ins), "sfr $sx">;
+
+// Section 8.19.6 - SMIR (Save Miscellaneous Register)
+let cy = 0, cz = 0, sz = 0, hasSideEffects = 1 in {
+  def SMIR : RR<0x22, (outs I64:$sx), (ins MISC:$sy), "smir $sx, $sy">;
+}
+
+// Section 8.19.7 - NOP (No Operation)
+let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in
+def NOP : RR<0x79, (outs), (ins), "nop">;
+
+// Section 8.19.8 - MONC (Monitor Call)
+let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in {
+  def MONC : RR<0x3F, (outs), (ins), "monc">;
+  let cx = 1, isTrap = 1 in def MONCHDB : RR<0x3F, (outs), (ins), "monc.hdb">;
+}
+
+// Section 8.19.9 - LCR (Load Communication Register)
+defm LCR : LOADCRm<"lcr", 0x40, I64>;
+
+// Section 8.19.10 - SCR (Save Communication Register)
+defm SCR : STORECRm<"scr", 0x50, I64>;
+
+// Section 8.19.11 - TSCR (Test & Set Communication Register)
+defm TSCR : LOADCRm<"tscr", 0x41, I64>;
+
+// Section 8.19.12 - FIDCR (Fetch & Increment/Decrement CR)
+defm FIDCR : FIDCRm<"fidcr", 0x51, I64>;
+
 let cx = 0, cy = 0, cz = 1, hasSideEffects = 0 in {
 let sy = 3 in
 def SHMri : RM<
@@ -1150,16 +1266,6 @@
     "shm.l $sx, $addr">;
 }
 
-let cx = 0, sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in
-def MONC : RR<
-    0x3F, (outs), (ins),
-    "monc">;
-
-// Save Instruction Counter
-
-let cx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 /* , Uses = [IC] */ in
-def SIC : RR<0x28, (outs I32:$sx), (ins), "sic $sx">;
-
 //===----------------------------------------------------------------------===//
 // Instructions for CodeGenOnly
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/VE/VERegisterInfo.td b/llvm/lib/Target/VE/VERegisterInfo.td
--- a/llvm/lib/Target/VE/VERegisterInfo.td
+++ b/llvm/lib/Target/VE/VERegisterInfo.td
@@ -20,6 +20,12 @@
   let Aliases = aliases;
 }
 
+class VEMiscReg<bits<6> enc, string n>: Register<n> {
+  let HWEncoding{15-6} = 0;
+  let HWEncoding{5-0} = enc;
+  let Namespace = "VE";
+}
+
 let Namespace = "VE" in {
   def sub_i8      : SubRegIndex<8, 56>;         // Low 8 bit (56..63)
   def sub_i16     : SubRegIndex<16, 48>;        // Low 16 bit (48..63)
@@ -29,6 +35,35 @@
 }
 
 //-----------------------------------------------------------------------------
+// Miscellaneous Registers
+//-----------------------------------------------------------------------------
+
+def USRCC : VEMiscReg<0, "usrcc">;      // User clock counter
+def PSW : VEMiscReg<1, "psw">;          // Program status word
+def SAR : VEMiscReg<2, "sar">;          // Store address register
+def PMMR : VEMiscReg<7, "pmmr">;        // Performance monitor mode register
+
+// Performance monitor configuration registers
+foreach I = 0-3 in
+  def PMCR#I : VEMiscReg<!add(8,I), "pmcr"#I>;
+
+// Performance monitor counter
+foreach I = 0-14 in
+  def PMC#I : VEMiscReg<!add(16,I), "pmc"#I>;
+
+// Register classes.
+def MISC : RegisterClass<"VE", [i64], 64,
+                         (add USRCC, PSW, SAR, PMMR,
+                              (sequence "PMCR%u", 0, 3),
+                              (sequence "PMC%u", 0, 14))>;
+
+//-----------------------------------------------------------------------------
+// Instruction Counter Register
+//-----------------------------------------------------------------------------
+
+def IC : VEMiscReg<62, "ic">;
+
+//-----------------------------------------------------------------------------
 // Gneric Registers
 //-----------------------------------------------------------------------------
 
diff --git a/llvm/test/MC/VE/FIDCR.s b/llvm/test/MC/VE/FIDCR.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/FIDCR.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: fidcr %s11, %s20, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x94,0x0b,0x51]
+fidcr %s11, %s20, 0
+
+# CHECK-INST: fidcr %s11, 22, 3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x03,0x16,0x0b,0x51]
+fidcr %s11, 22, 3
+
+# CHECK-INST: fidcr %s11, 22, 7
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x07,0x16,0x0b,0x51]
+fidcr %s11, 22, 7
diff --git a/llvm/test/MC/VE/LCR.s b/llvm/test/MC/VE/LCR.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/LCR.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: lcr %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x40]
+lcr %s11, %s20, %s22
+
+# CHECK-INST: lcr %s11, %s20, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x94,0x0b,0x40]
+lcr %s11, %s20, 0
+
+# CHECK-INST: lcr %s11, 22, %s15
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8f,0x16,0x0b,0x40]
+lcr %s11, 22, %s15
+
+# CHECK-INST: lcr %s11, 22, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x16,0x0b,0x40]
+lcr %s11, 22, 0
diff --git a/llvm/test/MC/VE/LFRSFR.s b/llvm/test/MC/VE/LFRSFR.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/LFRSFR.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: lfr %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8b,0x00,0x69]
+lfr %s11
+
+# CHECK-INST: lfr 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x00,0x69]
+lfr 63
+
+# CHECK-INST: sfr %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0x29]
+sfr %s63
diff --git a/llvm/test/MC/VE/LPMSPM.s b/llvm/test/MC/VE/LPMSPM.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/LPMSPM.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: lpm %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8b,0x00,0x3a]
+lpm %s11
+
+# CHECK-INST: spm %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0x2a]
+spm %s63
diff --git a/llvm/test/MC/VE/MONC.s b/llvm/test/MC/VE/MONC.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/MONC.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: monc
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f]
+monc
+
+# CHECK-INST: monc.hdb
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x3f]
+monc.hdb
diff --git a/llvm/test/MC/VE/NOP.s b/llvm/test/MC/VE/NOP.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/NOP.s
@@ -0,0 +1,8 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: nop
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x79]
+nop
diff --git a/llvm/test/MC/VE/SCR.s b/llvm/test/MC/VE/SCR.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/SCR.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: scr %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x50]
+scr %s11, %s20, %s22
+
+# CHECK-INST: scr %s11, %s20, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x94,0x0b,0x50]
+scr %s11, %s20, 0
+
+# CHECK-INST: scr %s11, 22, %s15
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8f,0x16,0x0b,0x50]
+scr %s11, 22, %s15
+
+# CHECK-INST: scr %s11, 22, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x16,0x0b,0x50]
+scr %s11, 22, 0
diff --git a/llvm/test/MC/VE/SIC.s b/llvm/test/MC/VE/SIC.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/SIC.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sic %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x0b,0x28]
+sic %s11
+
+# CHECK-INST: sic %s63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0x28]
+sic %s63
diff --git a/llvm/test/MC/VE/SMIR.s b/llvm/test/MC/VE/SMIR.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/SMIR.s
@@ -0,0 +1,188 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: smir %s11, %usrcc
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x0b,0x22]
+smir %s11, 0
+
+# CHECK-INST: smir %s11, %usrcc
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x0b,0x22]
+smir %s11, %usrcc
+
+# CHECK-INST: smir %s11, %psw
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x01,0x0b,0x22]
+smir %s11, 1
+
+# CHECK-INST: smir %s11, %psw
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x01,0x0b,0x22]
+smir %s11, %psw
+
+# CHECK-INST: smir %s11, %sar
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x02,0x0b,0x22]
+smir %s11, 2
+
+# CHECK-INST: smir %s11, %sar
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x02,0x0b,0x22]
+smir %s11, %sar
+
+# CHECK-INST: smir %s11, %pmmr
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x07,0x0b,0x22]
+smir %s11, 7
+
+# CHECK-INST: smir %s11, %pmmr
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x07,0x0b,0x22]
+smir %s11, %pmmr
+
+# CHECK-INST: smir %s11, %pmcr0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x08,0x0b,0x22]
+smir %s11, 8
+
+# CHECK-INST: smir %s11, %pmcr0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x08,0x0b,0x22]
+smir %s11, %pmcr0
+
+# CHECK-INST: smir %s11, %pmcr1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x09,0x0b,0x22]
+smir %s11, 9
+
+# CHECK-INST: smir %s11, %pmcr1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x09,0x0b,0x22]
+smir %s11, %pmcr1
+
+# CHECK-INST: smir %s11, %pmcr2
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x0a,0x0b,0x22]
+smir %s11, 10
+
+# CHECK-INST: smir %s11, %pmcr2
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x0a,0x0b,0x22]
+smir %s11, %pmcr2
+
+# CHECK-INST: smir %s11, %pmcr3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x0b,0x0b,0x22]
+smir %s11, 11
+
+# CHECK-INST: smir %s11, %pmcr3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x0b,0x0b,0x22]
+smir %s11, %pmcr3
+
+# CHECK-INST: smir %s11, %pmc0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x10,0x0b,0x22]
+smir %s11, 16
+
+# CHECK-INST: smir %s11, %pmc0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x10,0x0b,0x22]
+smir %s11, %pmc0
+
+# CHECK-INST: smir %s11, %pmc1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x11,0x0b,0x22]
+smir %s11, 17
+
+# CHECK-INST: smir %s11, %pmc1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x11,0x0b,0x22]
+smir %s11, %pmc1
+
+# CHECK-INST: smir %s11, %pmc2
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x12,0x0b,0x22]
+smir %s11, 18
+
+# CHECK-INST: smir %s11, %pmc2
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x12,0x0b,0x22]
+smir %s11, %pmc2
+
+# CHECK-INST: smir %s11, %pmc3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x13,0x0b,0x22]
+smir %s11, 19
+
+# CHECK-INST: smir %s11, %pmc3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x13,0x0b,0x22]
+smir %s11, %pmc3
+
+# CHECK-INST: smir %s11, %pmc4
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x14,0x0b,0x22]
+smir %s11, 20
+
+# CHECK-INST: smir %s11, %pmc4
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x14,0x0b,0x22]
+smir %s11, %pmc4
+
+# CHECK-INST: smir %s11, %pmc5
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x15,0x0b,0x22]
+smir %s11, 21
+
+# CHECK-INST: smir %s11, %pmc5
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x15,0x0b,0x22]
+smir %s11, %pmc5
+
+# CHECK-INST: smir %s11, %pmc6
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x16,0x0b,0x22]
+smir %s11, 22
+
+# CHECK-INST: smir %s11, %pmc6
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x16,0x0b,0x22]
+smir %s11, %pmc6
+
+# CHECK-INST: smir %s11, %pmc7
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x17,0x0b,0x22]
+smir %s11, 23
+
+# CHECK-INST: smir %s11, %pmc7
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x17,0x0b,0x22]
+smir %s11, %pmc7
+
+# CHECK-INST: smir %s11, %pmc8
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x18,0x0b,0x22]
+smir %s11, 24
+
+# CHECK-INST: smir %s11, %pmc8
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x18,0x0b,0x22]
+smir %s11, %pmc8
+
+# CHECK-INST: smir %s11, %pmc9
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x19,0x0b,0x22]
+smir %s11, 25
+
+# CHECK-INST: smir %s11, %pmc9
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x19,0x0b,0x22]
+smir %s11, %pmc9
+
+# CHECK-INST: smir %s11, %pmc10
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1a,0x0b,0x22]
+smir %s11, 26
+
+# CHECK-INST: smir %s11, %pmc10
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1a,0x0b,0x22]
+smir %s11, %pmc10
+
+# CHECK-INST: smir %s11, %pmc11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1b,0x0b,0x22]
+smir %s11, 27
+
+# CHECK-INST: smir %s11, %pmc11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1b,0x0b,0x22]
+smir %s11, %pmc11
+
+# CHECK-INST: smir %s11, %pmc12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1c,0x0b,0x22]
+smir %s11, 28
+
+# CHECK-INST: smir %s11, %pmc12
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1c,0x0b,0x22]
+smir %s11, %pmc12
+
+# CHECK-INST: smir %s11, %pmc13
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1d,0x0b,0x22]
+smir %s11, 29
+
+# CHECK-INST: smir %s11, %pmc13
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1d,0x0b,0x22]
+smir %s11, %pmc13
+
+# CHECK-INST: smir %s11, %pmc14
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1e,0x0b,0x22]
+smir %s11, 30
+
+# CHECK-INST: smir %s11, %pmc14
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x1e,0x0b,0x22]
+smir %s11, %pmc14
diff --git a/llvm/test/MC/VE/TSCR.s b/llvm/test/MC/VE/TSCR.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/TSCR.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: tscr %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x41]
+tscr %s11, %s20, %s22
+
+# CHECK-INST: tscr %s11, %s20, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x94,0x0b,0x41]
+tscr %s11, %s20, 0
+
+# CHECK-INST: tscr %s11, 22, %s15
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8f,0x16,0x0b,0x41]
+tscr %s11, 22, %s15
+
+# CHECK-INST: tscr %s11, 22, 0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x16,0x0b,0x41]
+tscr %s11, 22, 0