[ARM][XO] Execute-only miscompiles double literals for big-endian

[simonwallis2]

Summary

With -mbig-endian -mexecute-only and targeting an fpu,
an incorrect sequence of movw/movt was generated to construct a double literal.
The test suite was hardwired to check these wrong values.

The fault was caused by the explicit word swap in LowerConstantFP().

With -mbig-endian -mexecute-only -mfpu=none, a correct sequence of
movw/movt is generated to construct a double literal.
The test suite did not test this no fpu case.

The test suite expected values have been corrected.
The test file is updated to add testing of fpu=none case

[dmgreen]

Yeah, I agree. Top bits should go into top bits. LGTM

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (ST->genExecuteOnly()) {
     SDLoc DL(CFP);
     switch (VT.getSimpleVT().SimpleTy) {
       default:
         llvm_unreachable("Unknown floating point type!");
         break;
       case MVT::f64: {
         SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
         SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
-        if (!ST->isLittle())
-          std::swap(Lo, Hi);
         return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi);
       }
       case MVT::f32:
           return DAG.getNode(ARMISD::VMOVSR, DL, VT,
               DAG.getConstant(INTVal, DL, MVT::i32));
     }
   }
 

llvm/test/CodeGen/ARM/constantfp.ll

 ; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s
 ; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s
 ; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s
 
 ; RUN: llc -mtriple=thumbv7m -mcpu=cortex-m4 %s -o - \
 ; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s
 
 ; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 %s -o - \
 ; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s
 
 ; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m4 %s -o - \
-; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s
+; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE  --check-prefix=CHECK-XO-DOUBLE-BE-FPREGS %s
+
+; RUN: llc -mtriple=thumbv7meb -mattr=+execute-only -mcpu=cortex-m3 %s -o - \
+; RUN: | FileCheck --check-prefix=CHECK-XO-DOUBLE-BE %s
 
 ; RUN: llc -mtriple=thumbv7m -mattr=+execute-only -mcpu=cortex-m4 -relocation-model=ropi %s -o - \
 ; RUN: | FileCheck --check-prefix=CHECK-XO-ROPI %s
 
 ; RUN: llc -mtriple=thumbv8m.main -mattr=fp-armv8 %s -o - \
 ; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s
 
 ; RUN: llc -mtriple=thumbv8m.main -mattr=+execute-only -mattr=fp-armv8 %s -o - \

 ; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
 
 ; CHECK-XO-DOUBLE-LABEL: test_vmov_double_imm:
 ; CHECK-XO-DOUBLE: movs [[REG:r[0-9]+]], #0
 ; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
 ; CHECK-XO-DOUBLE-NOT: vldr
 
 ; CHECK-XO-DOUBLE-BE-LABEL: test_vmov_double_imm:
-; CHECK-XO-DOUBLE-BE: movs [[REG:r[0-9]+]], #0
-; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
+; CHECK-XO-DOUBLE-BE-FPREGS: movs [[REG:r[0-9]+]], #0
+; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG]], [[REG]]
 ; CHECK-XO-DOUBLE-NOT: vldr
   ret double 0.0
 }
 
 define arm_aapcs_vfpcc double @test_vmvn_double_imm() {
 ; CHECK-LABEL: test_vmvn_double_imm:
 ; CHECK: vmvn.i32 d0, #0xb0000000
 
 ; CHECK-NONEON-LABEL: test_vmvn_double_imm:
 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
 
 ; CHECK-NO-XO-LABEL: test_vmvn_double_imm:
 ; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
 
 ; CHECK-XO-DOUBLE-LABEL: test_vmvn_double_imm:
 ; CHECK-XO-DOUBLE: mvn [[REG:r[0-9]+]], #-1342177280
 ; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
 ; CHECK-XO-DOUBLE-NOT: vldr
 
 ; CHECK-XO-DOUBLE-BE-LABEL: test_vmvn_double_imm:
-; CHECK-XO-DOUBLE-BE: mvn [[REG:r[0-9]+]], #-1342177280
-; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]]
+; CHECK-XO-DOUBLE-BE-FPREGS: mvn [[REG:r[0-9]+]], #-1342177280
+; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG]], [[REG]]
 ; CHECK-XO-DOUBLE-BE-NOT: vldr
   ret double 0x4fffffff4fffffff
 }
 
 ; Make sure we don't ignore the high half of 64-bit values when deciding whether
 ; a vmov/vmvn is possible.
 define arm_aapcs_vfpcc double @test_notvmvn_double_imm() {
 ; CHECK-LABEL: test_notvmvn_double_imm:
 ; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
 
 ; CHECK-NONEON-LABEL: test_notvmvn_double_imm:
 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
 
 ; CHECK-NO-XO-LABEL: test_notvmvn_double_imm:
 ; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
 
 ; CHECK-XO-DOUBLE-LABEL: test_notvmvn_double_imm:
 ; CHECK-XO-DOUBLE: mvn [[REG1:r[0-9]+]], #-1342177280
 ; CHECK-XO-DOUBLE: mov.w [[REG2:r[0-9]+]], #-1
 ; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
 ; CHECK-XO-DOUBLE-NOT: vldr
 
 ; CHECK-XO-DOUBLE-BE-LABEL: test_notvmvn_double_imm:
-; CHECK-XO-DOUBLE-BE: mov.w [[REG1:r[0-9]+]], #-1
-; CHECK-XO-DOUBLE-BE: mvn [[REG2:r[0-9]+]], #-1342177280
-; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK-XO-DOUBLE-BE: mvn [[REG1:r[0-9]+]], #-1342177280
+; CHECK-XO-DOUBLE-BE: mov.w [[REG2:r[0-9]+]], #-1
+; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
 ; CHECK-XO-DOUBLE-BE-NOT: vldr
   ret double 0x4fffffffffffffff
 }
 
 define arm_aapcs_vfpcc float @lower_const_f32_xo() {
 ; CHECK-NO-XO-LABEL: lower_const_f32_xo
 ; CHECK-NO-XO: vldr {{s[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}}
 

 ; CHECK-XO-DOUBLE: movw [[REG1:r[0-9]+]], #6291
 ; CHECK-XO-DOUBLE: movw [[REG2:r[0-9]+]], #27263
 ; CHECK-XO-DOUBLE: movt [[REG1]], #16340
 ; CHECK-XO-DOUBLE: movt [[REG2]], #29884
 ; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
 ; CHECK-XO-DOUBLE-NOT: vldr
 
 ; CHECK-XO-DOUBLE-BE-LABEL: lower_const_f64_xo
-; CHECK-XO-DOUBLE-BE: movw [[REG1:r[0-9]+]], #27263
-; CHECK-XO-DOUBLE-BE: movw [[REG2:r[0-9]+]], #6291
-; CHECK-XO-DOUBLE-BE: movt [[REG1]], #29884
-; CHECK-XO-DOUBLE-BE: movt [[REG2]], #16340
-; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK-XO-DOUBLE-BE: movw [[REG1:r[0-9]+]], #6291
+; CHECK-XO-DOUBLE-BE: movw [[REG2:r[0-9]+]], #27263
+; CHECK-XO-DOUBLE-BE: movt [[REG1]], #16340
+; CHECK-XO-DOUBLE-BE: movt [[REG2]], #29884
+; CHECK-XO-DOUBLE-BE-FPREGS: vmov {{d[0-9]+}}, [[REG2]], [[REG1]]
 ; CHECK-XO-DOUBLE-BE-NOT: vldr
   ret double 3.140000e-01
 }
 
 ; This is a target independent optimization, performed by the
 ; DAG Combiner, which promotes floating point literals into
 ; constant pools:
 ;