Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -4694,25 +4694,62 @@ static bool isFunctionGlobalAddress(SDValue Callee); -static bool -callsShareTOCBase(const Function *Caller, SDValue Callee, - const TargetMachine &TM) { - // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols - // don't have enough information to determine if the caller and calle share - // the same TOC base, so we have to pessimistically assume they don't for - // correctness. - GlobalAddressSDNode *G = dyn_cast(Callee); - if (!G) - return false; - - const GlobalValue *GV = G->getGlobal(); +static bool callsShareTOCBase(const Function *Caller, SDValue Callee, + const TargetMachine &TM) { + // It does not make sense to call callsShareTOCBase() with a caller that + // is PC Relative since PC Relative callers do not have a TOC. + const PPCSubtarget *STICaller = &TM.getSubtarget(*Caller); + assert(!STICaller->isUsingPCRelativeCalls() && + "PC Relative callers do not have a TOC and cannot share a TOC Base"); + + // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols + // don't have enough information to determine if the caller and calle share + // the same TOC base, so we have to pessimistically assume they don't for + // correctness. + GlobalAddressSDNode *G = dyn_cast(Callee); + if (!G) + return false; + + const GlobalValue *GV = G->getGlobal(); // The medium and large code models are expected to provide a sufficiently // large TOC to provide all data addressing needs of a module with a // single TOC. Since each module will be addressed with a single TOC then we // only need to check that caller and callee don't cross dso boundaries. + // In the case of PC Relative addressing this assumption is not always true. + // Functions with PC Relative enabled may clobber the TOC in the same DSO. + // We may need a TOC restore in the situation where the caller requires a + // valid TOC but the callee is PC Relative and does not. if (CodeModel::Medium == TM.getCodeModel() || - CodeModel::Large == TM.getCodeModel()) - return TM.shouldAssumeDSOLocal(*Caller->getParent(), GV); + CodeModel::Large == TM.getCodeModel()) { + if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV)) + return false; + + const Function *F = dyn_cast(GV); + const GlobalIndirectSymbol *Sym = dyn_cast(GV); + + // Either the function or the symbol needs to have a valid pointer. + // Ohterwise, there is no way to check the subtarget info for the callee. + if (!F && !Sym) + return false; + + if (Sym) { + const GlobalObject *GlobalObj = Sym->getBaseObject(); + F = dyn_cast(GlobalObj); + } + + if (!F) + return false; + + const PPCSubtarget *STICallee = &TM.getSubtarget(*F); + + // If the callee uses PC Relative we cannot guarantee that the callee won't + // clobber the TOC of the caller and so we must assume that the two + // functions do not share a TOC base. + if (STICallee->isUsingPCRelativeCalls()) + return false; + + return true; + } // Otherwise we need to ensure callee and caller are in the same section, // since the linker may allocate multiple TOCs, and we don't know which @@ -5271,8 +5308,8 @@ // will rewrite the nop to be a load of the TOC pointer from the linkage area // into gpr2. if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI()) - return callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL - : PPCISD::CALL_NOP; + return callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL + : PPCISD::CALL_NOP; return PPCISD::CALL; } Index: llvm/test/CodeGen/PowerPC/pcrel-local-caller-toc.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/PowerPC/pcrel-local-caller-toc.ll @@ -0,0 +1,98 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s + +; The purpose of this test is to check the call protocols for the situation +; where the caller has PC Relative disabled, the callee has PC Relative +; enabled and both functions are in the same file. +; Note that the callee does not know if it clobbers the TOC because it +; contains an external call to @externalFunc. + +@global = external local_unnamed_addr global i32, align 4 + +define dso_local signext i32 @callee(i32 signext %a) local_unnamed_addr #0 { +; CHECK-LABEL: callee: +; CHECK: .localentry callee, 1 +; CHECK-NEXT: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -48(r1) +; CHECK-NEXT: mr r30, r3 +; CHECK-NEXT: bl externalFunc@notoc +; CHECK-NEXT: add r3, r3, r30 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: addi r1, r1, 48 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + %call = tail call signext i32 @externalFunc(i32 signext %a) #3 + %add = add nsw i32 %call, %a + ret i32 %add +} + +declare signext i32 @externalFunc(i32 signext) local_unnamed_addr #1 + +define dso_local void @caller(i32 signext %a) local_unnamed_addr #2 { +; CHECK-LABEL: caller: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -48(r1) +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: ld r30, .LC0@toc@l(r4) +; CHECK-NEXT: lwz r4, 0(r30) +; CHECK-NEXT: add r3, r4, r3 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: bl callee +; CHECK-NEXT: nop +; CHECK-NEXT: mullw r3, r3, r3 +; CHECK-NEXT: stw r3, 0(r30) +; CHECK-NEXT: addi r1, r1, 48 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + %0 = load i32, i32* @global, align 4 + %add = add nsw i32 %0, %a + %call = tail call signext i32 @callee(i32 signext %add) + %mul = mul nsw i32 %call, %call + store i32 %mul, i32* @global, align 4 + ret void +} + +define dso_local signext i32 @tail_caller(i32 signext %a) local_unnamed_addr #2 { +; CHECK-LABEL: tail_caller: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -32(r1) +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: lwz r4, 0(r4) +; CHECK-NEXT: add r3, r4, r3 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: bl callee +; CHECK-NEXT: nop +; CHECK-NEXT: addi r1, r1, 32 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + %0 = load i32, i32* @global, align 4 + %add = add nsw i32 %0, %a + %call = tail call signext i32 @callee(i32 signext %add) + ret i32 %call +} + + +; Left the target features in this test because it is important that caller has +; -pcrelative-memops while callee has +pcrelative-memops +attributes #0 = { nounwind "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+pcrelative-memops,+power8-vector,+power9-vector,+vsx,-htm,-qpx,-spe" } +attributes #1 = { "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+pcrelative-memops,+power8-vector,+power9-vector,+vsx,-htm,-qpx,-spe" } +attributes #2 = { nounwind "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+power9-vector,+vsx,-htm,-pcrelative-memops,-qpx,-spe" } +attributes #3 = { nounwind }