diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -219,7 +219,8 @@ Fixups.push_back( MCFixup::create(0, Expr, static_cast(PPC::fixup_ppc_pcrel34))); - // There is no offset to return so just return 0. + // Put zero in the location of the immediate. The linker will fill in the + // correct value based on the relocation. return 0; } case MCExpr::Binary: { @@ -242,6 +243,7 @@ const MCSymbolRefExpr *SRE = cast(LHS); (void)SRE; const MCConstantExpr *CE = cast(RHS); + assert(isInt<34>(CE->getValue()) && "Value must fit in 34 bits."); // Currently these are the only valid PCRelative Relocations. assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL || @@ -251,9 +253,9 @@ Fixups.push_back( MCFixup::create(0, Expr, static_cast(PPC::fixup_ppc_pcrel34))); - assert(isInt<34>(CE->getValue()) && "Value must fit in 34 bits."); - // Return the offset that should be added to the relocation by the linker. - return (CE->getValue() & 0x3FFFFFFFFUL) | RegBits; + // Put zero in the location of the immediate. The linker will fill in the + // correct value based on the relocation. + return 0; } } } diff --git a/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll b/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll --- a/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll +++ b/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll @@ -16,7 +16,7 @@ ; CHECK-S-NEXT: plwa r3, array2@PCREL+28(0), 1 ; CHECK-S-NEXT: blr ; CHECK-O-LABEL: : -; CHECK-O: 00 00 10 04 1c 00 60 a4 plwa 3, 28(0), 1 +; CHECK-O: 00 00 10 04 00 00 60 a4 plwa 3, 0(0), 1 ; CHECK-O-NEXT: 0000000000000000: R_PPC64_PCREL34 array2+0x1c ; CHECK-O-NEXT: 20 00 80 4e blr entry: @@ -30,7 +30,7 @@ ; CHECK-S-NEXT: plwa r3, array2@PCREL-8(0), 1 ; CHECK-S-NEXT: blr ; CHECK-O-LABEL: : -; CHECK-O: ff ff 13 04 f8 ff 60 a4 plwa 3, -8(0), 1 +; CHECK-O: 00 00 10 04 00 00 60 a4 plwa 3, 0(0), 1 ; CHECK-O-NEXT: 0000000000000020: R_PPC64_PCREL34 array2-0x8 ; CHECK-O-NEXT: 20 00 80 4e blr entry: