diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -145,9 +145,9 @@
       // it does use R2 then it is just a caller saved register. Therefore it is
       // safe to emit only the bl and not the nop for this instruction. The
       // linker will not try to restore R2 after the call.
-      def BL8_NOTOC : IForm_and_DForm_4_zero<18, 0, 1, 24, (outs),
-                                             (ins calltarget:$func),
-                                             "bl $func", IIC_BrB, []>;
+      def BL8_NOTOC : IForm<18, 0, 1, (outs),
+                            (ins calltarget:$func),
+                            "bl $func", IIC_BrB, []>;
     }
   }
   let Uses = [CTR8, RM] in {
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-simple.ll b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-simple.ll
--- a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-simple.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-simple.ll
@@ -36,3 +36,27 @@
 
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
 
+
+; CHECK-S-LABEL: callerNoTail
+; CHECK-S:     bl callee@notoc
+; CHECK-S-NOT: nop
+; CHECK-S:     bl callee@notoc
+; CHECK-S-NOT: nop
+; CHECK-S:     blr
+
+; CHECK-O-LABEL: callerNoTail
+; CHECK-O:      bl
+; CHECK-O-NEXT: R_PPC64_REL24_NOTOC callee
+; CHECK-O-NOT:  nop
+; CHECK-O:      bl
+; CHECK-O-NEXT: R_PPC64_REL24_NOTOC callee
+; CHECK-O-NOT:  nop
+; CHECK-O:      blr
+define dso_local signext i32 @callerNoTail() local_unnamed_addr {
+entry:
+  %call1 = tail call signext i32 bitcast (i32 (...)* @callee to i32 ()*)()
+  %call2 = tail call signext i32 bitcast (i32 (...)* @callee to i32 ()*)()
+  %add = add i32 %call1, %call2
+  ret i32 %add
+}
+