diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -1096,6 +1096,7 @@
     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
 
     SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -762,6 +762,8 @@
     if (!Subtarget.hasP8Altivec())
       setOperationAction(ISD::ABS, MVT::v2i64, Expand);
 
+    // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
+    setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
     // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
     if (Subtarget.hasAltivec())
       for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
@@ -9611,6 +9613,36 @@
   return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins);
 }
 
+/// LowerROTL - Custom lowering for ROTL(v1i128) to vector_shuffle(v16i8).
+/// We lower ROTL(v1i128) to vector_shuffle(v16i8) only if shift amount is
+/// a multiple of 8. Otherwise convert it to a scalar rotation(i128)
+/// i.e (or (shl x, C1), (srl x, 128-C1)).
+SDValue PPCTargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const {
+  if (Op.getValueType() != MVT::v1i128)
+    return SDValue();
+  SDLoc dl(Op);
+  SDValue N0 = Op.getOperand(0);
+  SDValue N1 = peekThroughBitcasts(Op.getOperand(1));
+  unsigned SHLAmt = N1.getConstantOperandVal(0);
+  if (SHLAmt % 8 == 0) {
+    SmallVector<int, 16> Mask(16, 0);
+    std::iota(Mask.begin(), Mask.end(), 0);
+    std::rotate(Mask.begin(), Mask.begin() + SHLAmt / 8, Mask.end());
+    SDValue Shuffle =
+        DAG.getVectorShuffle(MVT::v16i8, dl, DAG.getBitcast(MVT::v16i8, N0),
+                             DAG.getUNDEF(MVT::v16i8), Mask);
+    if (Shuffle)
+      return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, Shuffle);
+  }
+  SDValue ArgVal = DAG.getBitcast(MVT::i128, N0);
+  SDValue SHLOp = DAG.getNode(ISD::SHL, dl, MVT::i128, ArgVal,
+                              DAG.getConstant(SHLAmt, dl, MVT::i32));
+  SDValue SRLOp = DAG.getNode(ISD::SRL, dl, MVT::i128, ArgVal,
+                              DAG.getConstant(128 - SHLAmt, dl, MVT::i32));
+  SDValue OROp = DAG.getNode(ISD::OR, dl, MVT::i128, SHLOp, SRLOp);
+  return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, OROp);
+}
+
 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE.  If this
 /// is a shuffle we can handle in a single instruction, return it.  Otherwise,
 /// return the code it can be lowered into.  Worst case, it can always be
@@ -10892,7 +10924,7 @@
   case ISD::MUL:                return LowerMUL(Op, DAG);
   case ISD::ABS:                return LowerABS(Op, DAG);
   case ISD::FP_EXTEND:          return LowerFP_EXTEND(Op, DAG);
-
+  case ISD::ROTL:               return LowerROTL(Op, DAG);
   // For counter-based loop handling.
   case ISD::INTRINSIC_W_CHAIN:  return SDValue();
 
diff --git a/llvm/test/CodeGen/PowerPC/pr45628.ll b/llvm/test/CodeGen/PowerPC/pr45628.ll
--- a/llvm/test/CodeGen/PowerPC/pr45628.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45628.ll
@@ -9,28 +9,12 @@
 define <1 x i128> @rotl_64(<1 x i128> %num) {
 ; CHECK-VSX-LABEL: rotl_64:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-VSX-NEXT:    lxvx v3, 0, r3
-; CHECK-VSX-NEXT:    vslo v4, v2, v3
-; CHECK-VSX-NEXT:    vspltb v5, v3, 15
-; CHECK-VSX-NEXT:    vsro v2, v2, v3
-; CHECK-VSX-NEXT:    vsl v4, v4, v5
-; CHECK-VSX-NEXT:    vsr v2, v2, v5
-; CHECK-VSX-NEXT:    xxlor v2, v4, v2
+; CHECK-VSX-NEXT:    xxswapd v2, v2
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: rotl_64:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v5, v3, 15
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v3
-; CHECK-NOVSX-NEXT:    vsl v4, v4, v5
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v5
-; CHECK-NOVSX-NEXT:    vor v2, v4, v2
+; CHECK-NOVSX-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shl = shl <1 x i128> %num, <i128 64>
@@ -42,36 +26,12 @@
 define <1 x i128> @rotl_32(<1 x i128> %num) {
 ; CHECK-VSX-LABEL: rotl_32:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-VSX-NEXT:    lxvx v3, 0, r3
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI1_1@toc@l
-; CHECK-VSX-NEXT:    vslo v4, v2, v3
-; CHECK-VSX-NEXT:    vspltb v3, v3, 15
-; CHECK-VSX-NEXT:    vsl v3, v4, v3
-; CHECK-VSX-NEXT:    lxvx v4, 0, r3
-; CHECK-VSX-NEXT:    vsro v2, v2, v4
-; CHECK-VSX-NEXT:    vspltb v4, v4, 15
-; CHECK-VSX-NEXT:    vsr v2, v2, v4
-; CHECK-VSX-NEXT:    xxlor v2, v3, v2
+; CHECK-VSX-NEXT:    xxsldwi v2, v2, v2, 3
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: rotl_32:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI1_1@toc@l
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v3, v3, 15
-; CHECK-NOVSX-NEXT:    vsl v3, v4, v3
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v4
-; CHECK-NOVSX-NEXT:    vspltb v4, v4, 15
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v4
-; CHECK-NOVSX-NEXT:    vor v2, v3, v2
+; CHECK-NOVSX-NEXT:    vsldoi v2, v2, v2, 12
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shl = shl <1 x i128> %num, <i128 32>
@@ -83,36 +43,12 @@
 define <1 x i128> @rotl_96(<1 x i128> %num) {
 ; CHECK-VSX-LABEL: rotl_96:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-VSX-NEXT:    lxvx v3, 0, r3
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI2_1@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI2_1@toc@l
-; CHECK-VSX-NEXT:    vslo v4, v2, v3
-; CHECK-VSX-NEXT:    vspltb v3, v3, 15
-; CHECK-VSX-NEXT:    vsl v3, v4, v3
-; CHECK-VSX-NEXT:    lxvx v4, 0, r3
-; CHECK-VSX-NEXT:    vsro v2, v2, v4
-; CHECK-VSX-NEXT:    vspltb v4, v4, 15
-; CHECK-VSX-NEXT:    vsr v2, v2, v4
-; CHECK-VSX-NEXT:    xxlor v2, v3, v2
+; CHECK-VSX-NEXT:    xxsldwi v2, v2, v2, 1
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: rotl_96:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI2_1@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI2_1@toc@l
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v3, v3, 15
-; CHECK-NOVSX-NEXT:    vsl v3, v4, v3
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v4
-; CHECK-NOVSX-NEXT:    vspltb v4, v4, 15
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v4
-; CHECK-NOVSX-NEXT:    vor v2, v3, v2
+; CHECK-NOVSX-NEXT:    vsldoi v2, v2, v2, 4
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shl = shl <1 x i128> %num, <i128 96>
@@ -124,36 +60,12 @@
 define <1 x i128> @rotl_16(<1 x i128> %num) {
 ; CHECK-VSX-LABEL: rotl_16:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-VSX-NEXT:    lxvx v3, 0, r3
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI3_1@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI3_1@toc@l
-; CHECK-VSX-NEXT:    vslo v4, v2, v3
-; CHECK-VSX-NEXT:    vspltb v3, v3, 15
-; CHECK-VSX-NEXT:    vsl v3, v4, v3
-; CHECK-VSX-NEXT:    lxvx v4, 0, r3
-; CHECK-VSX-NEXT:    vsro v2, v2, v4
-; CHECK-VSX-NEXT:    vspltb v4, v4, 15
-; CHECK-VSX-NEXT:    vsr v2, v2, v4
-; CHECK-VSX-NEXT:    xxlor v2, v3, v2
+; CHECK-VSX-NEXT:    vsldoi v2, v2, v2, 14
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: rotl_16:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI3_1@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI3_1@toc@l
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v3, v3, 15
-; CHECK-NOVSX-NEXT:    vsl v3, v4, v3
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v4
-; CHECK-NOVSX-NEXT:    vspltb v4, v4, 15
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v4
-; CHECK-NOVSX-NEXT:    vor v2, v3, v2
+; CHECK-NOVSX-NEXT:    vsldoi v2, v2, v2, 14
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shl = shl <1 x i128> %num, <i128 16>
@@ -165,36 +77,12 @@
 define <1 x i128> @rotl_112(<1 x i128> %num) {
 ; CHECK-VSX-LABEL: rotl_112:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-VSX-NEXT:    lxvx v3, 0, r3
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI4_1@toc@l
-; CHECK-VSX-NEXT:    vslo v4, v2, v3
-; CHECK-VSX-NEXT:    vspltb v3, v3, 15
-; CHECK-VSX-NEXT:    vsl v3, v4, v3
-; CHECK-VSX-NEXT:    lxvx v4, 0, r3
-; CHECK-VSX-NEXT:    vsro v2, v2, v4
-; CHECK-VSX-NEXT:    vspltb v4, v4, 15
-; CHECK-VSX-NEXT:    vsr v2, v2, v4
-; CHECK-VSX-NEXT:    xxlor v2, v3, v2
+; CHECK-VSX-NEXT:    vsldoi v2, v2, v2, 2
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: rotl_112:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI4_1@toc@l
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v3, v3, 15
-; CHECK-NOVSX-NEXT:    vsl v3, v4, v3
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v4
-; CHECK-NOVSX-NEXT:    vspltb v4, v4, 15
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v4
-; CHECK-NOVSX-NEXT:    vor v2, v3, v2
+; CHECK-NOVSX-NEXT:    vsldoi v2, v2, v2, 2
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shl = shl <1 x i128> %num, <i128 112>
@@ -206,36 +94,12 @@
 define <1 x i128> @rotl_8(<1 x i128> %num) {
 ; CHECK-VSX-LABEL: rotl_8:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-VSX-NEXT:    lxvx v3, 0, r3
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI5_1@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI5_1@toc@l
-; CHECK-VSX-NEXT:    vslo v4, v2, v3
-; CHECK-VSX-NEXT:    vspltb v3, v3, 15
-; CHECK-VSX-NEXT:    vsl v3, v4, v3
-; CHECK-VSX-NEXT:    lxvx v4, 0, r3
-; CHECK-VSX-NEXT:    vsro v2, v2, v4
-; CHECK-VSX-NEXT:    vspltb v4, v4, 15
-; CHECK-VSX-NEXT:    vsr v2, v2, v4
-; CHECK-VSX-NEXT:    xxlor v2, v3, v2
+; CHECK-VSX-NEXT:    vsldoi v2, v2, v2, 15
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: rotl_8:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI5_1@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI5_1@toc@l
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v3, v3, 15
-; CHECK-NOVSX-NEXT:    vsl v3, v4, v3
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v4
-; CHECK-NOVSX-NEXT:    vspltb v4, v4, 15
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v4
-; CHECK-NOVSX-NEXT:    vor v2, v3, v2
+; CHECK-NOVSX-NEXT:    vsldoi v2, v2, v2, 15
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shl = shl <1 x i128> %num, <i128 8>
@@ -247,36 +111,12 @@
 define <1 x i128> @rotl_120(<1 x i128> %num) {
 ; CHECK-VSX-LABEL: rotl_120:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-VSX-NEXT:    lxvx v3, 0, r3
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI6_1@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI6_1@toc@l
-; CHECK-VSX-NEXT:    vslo v4, v2, v3
-; CHECK-VSX-NEXT:    vspltb v3, v3, 15
-; CHECK-VSX-NEXT:    vsl v3, v4, v3
-; CHECK-VSX-NEXT:    lxvx v4, 0, r3
-; CHECK-VSX-NEXT:    vsro v2, v2, v4
-; CHECK-VSX-NEXT:    vspltb v4, v4, 15
-; CHECK-VSX-NEXT:    vsr v2, v2, v4
-; CHECK-VSX-NEXT:    xxlor v2, v3, v2
+; CHECK-VSX-NEXT:    vsldoi v2, v2, v2, 1
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: rotl_120:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI6_1@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI6_1@toc@l
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v3, v3, 15
-; CHECK-NOVSX-NEXT:    vsl v3, v4, v3
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v4
-; CHECK-NOVSX-NEXT:    vspltb v4, v4, 15
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v4
-; CHECK-NOVSX-NEXT:    vor v2, v3, v2
+; CHECK-NOVSX-NEXT:    vsldoi v2, v2, v2, 1
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shl = shl <1 x i128> %num, <i128 120>
@@ -288,36 +128,29 @@
 define <1 x i128> @rotl_28(<1 x i128> %num) {
 ; CHECK-VSX-LABEL: rotl_28:
 ; CHECK-VSX:       # %bb.0: # %entry
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; CHECK-VSX-NEXT:    lxvx v3, 0, r3
-; CHECK-VSX-NEXT:    addis r3, r2, .LCPI7_1@toc@ha
-; CHECK-VSX-NEXT:    addi r3, r3, .LCPI7_1@toc@l
-; CHECK-VSX-NEXT:    vslo v4, v2, v3
-; CHECK-VSX-NEXT:    vspltb v3, v3, 15
-; CHECK-VSX-NEXT:    vsl v3, v4, v3
-; CHECK-VSX-NEXT:    lxvx v4, 0, r3
-; CHECK-VSX-NEXT:    vsro v2, v2, v4
-; CHECK-VSX-NEXT:    vspltb v4, v4, 15
-; CHECK-VSX-NEXT:    vsr v2, v2, v4
-; CHECK-VSX-NEXT:    xxlor v2, v3, v2
+; CHECK-VSX-NEXT:    mfvsrld r4, v2
+; CHECK-VSX-NEXT:    mfvsrd r3, v2
+; CHECK-VSX-NEXT:    rotldi r5, r4, 28
+; CHECK-VSX-NEXT:    rldimi r5, r3, 28, 0
+; CHECK-VSX-NEXT:    rotldi r3, r3, 28
+; CHECK-VSX-NEXT:    rldimi r3, r4, 28, 0
+; CHECK-VSX-NEXT:    mtvsrdd v2, r5, r3
 ; CHECK-VSX-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: rotl_28:
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI7_1@toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI7_1@toc@l
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v3, v3, 15
-; CHECK-NOVSX-NEXT:    vsl v3, v4, v3
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v4
-; CHECK-NOVSX-NEXT:    vspltb v4, v4, 15
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v4
-; CHECK-NOVSX-NEXT:    vor v2, v3, v2
+; CHECK-NOVSX-NEXT:    addi r3, r1, -32
+; CHECK-NOVSX-NEXT:    stvx v2, 0, r3
+; CHECK-NOVSX-NEXT:    ld r4, -32(r1)
+; CHECK-NOVSX-NEXT:    ld r3, -24(r1)
+; CHECK-NOVSX-NEXT:    rotldi r5, r4, 28
+; CHECK-NOVSX-NEXT:    rldimi r5, r3, 28, 0
+; CHECK-NOVSX-NEXT:    rotldi r3, r3, 28
+; CHECK-NOVSX-NEXT:    rldimi r3, r4, 28, 0
+; CHECK-NOVSX-NEXT:    std r3, -16(r1)
+; CHECK-NOVSX-NEXT:    addi r3, r1, -16
+; CHECK-NOVSX-NEXT:    std r5, -8(r1)
+; CHECK-NOVSX-NEXT:    lvx v2, 0, r3
 ; CHECK-NOVSX-NEXT:    blr
 entry:
   %shl = shl <1 x i128> %num, <i128 28>