Index: llvm/lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- llvm/lib/Target/PowerPC/PPCISelLowering.h +++ llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -1096,6 +1096,7 @@ SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const; Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -762,6 +762,8 @@ if (!Subtarget.hasP8Altivec()) setOperationAction(ISD::ABS, MVT::v2i64, Expand); + // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8. + setOperationAction(ISD::ROTL, MVT::v1i128, Custom); // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w). if (Subtarget.hasAltivec()) for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8}) @@ -9611,6 +9613,36 @@ return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); } +/// LowerROTL - Custom lowering for ROTL(v1i128) to vector_shuffle(v16i8). +/// We lower ROTL(v1i128) to vector_shuffle(v16i8) only if shift amount is +/// a multiple of 8. Otherwise convert it to a scalar rotation(i128) +/// i.e (or (shl x, C1), (srl x, 128-C1)). +SDValue PPCTargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const { + if (Op.getValueType() != MVT::v1i128) + return SDValue(); + SDLoc dl(Op); + SDValue N0 = Op.getOperand(0); + SDValue N1 = peekThroughBitcasts(Op.getOperand(1)); + unsigned SHLAmt = N1.getConstantOperandVal(0); + if (SHLAmt % 8 == 0) { + SmallVector Mask(16, 0); + std::iota(Mask.begin(), Mask.end(), 0); + std::rotate(Mask.begin(), Mask.begin() + SHLAmt / 8, Mask.end()); + SDValue Shuffle = + DAG.getVectorShuffle(MVT::v16i8, dl, DAG.getBitcast(MVT::v16i8, N0), + DAG.getUNDEF(MVT::v16i8), Mask); + if (Shuffle) + return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, Shuffle); + } + SDValue ArgVal = DAG.getBitcast(MVT::i128, N0); + SDValue SHLOp = DAG.getNode(ISD::SHL, dl, MVT::i128, ArgVal, + DAG.getConstant(SHLAmt, dl, MVT::i32)); + SDValue SRLOp = DAG.getNode(ISD::SRL, dl, MVT::i128, ArgVal, + DAG.getConstant(128 - SHLAmt, dl, MVT::i32)); + SDValue OROp = DAG.getNode(ISD::OR, dl, MVT::i128, SHLOp, SRLOp); + return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, OROp); +} + /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this /// is a shuffle we can handle in a single instruction, return it. Otherwise, /// return the code it can be lowered into. Worst case, it can always be @@ -10892,6 +10924,7 @@ case ISD::MUL: return LowerMUL(Op, DAG); case ISD::ABS: return LowerABS(Op, DAG); case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); + case ISD::ROTL: return LowerROTL(Op, DAG); // For counter-based loop handling. case ISD::INTRINSIC_W_CHAIN: return SDValue(); Index: llvm/test/CodeGen/PowerPC/pr45628.ll =================================================================== --- llvm/test/CodeGen/PowerPC/pr45628.ll +++ llvm/test/CodeGen/PowerPC/pr45628.ll @@ -0,0 +1,219 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s \ +; RUN: -check-prefix=CHECK-VSX +; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -mattr=-vsx < %s | FileCheck %s \ +; RUN: -check-prefix=CHECK-NOVSX + +define <1 x i128> @rotl_64(<1 x i128> %num) { +; CHECK-VSX-LABEL: rotl_64: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: xxswapd v2, v2 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: rotl_64: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 8 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} + +define <1 x i128> @rotl_32(<1 x i128> %num) { +; CHECK-VSX-LABEL: rotl_32: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: xxsldwi v2, v2, v2, 3 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: rotl_32: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 12 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} + +define <1 x i128> @rotl_96(<1 x i128> %num) { +; CHECK-VSX-LABEL: rotl_96: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: xxsldwi v2, v2, v2, 1 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: rotl_96: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 4 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} + +define <1 x i128> @rotl_16(<1 x i128> %num) { +; CHECK-VSX-LABEL: rotl_16: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: vsldoi v2, v2, v2, 14 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: rotl_16: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 14 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} + +define <1 x i128> @rotl_112(<1 x i128> %num) { +; CHECK-VSX-LABEL: rotl_112: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: vsldoi v2, v2, v2, 2 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: rotl_112: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 2 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} + +define <1 x i128> @rotl_8(<1 x i128> %num) { +; CHECK-VSX-LABEL: rotl_8: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: vsldoi v2, v2, v2, 15 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: rotl_8: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 15 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} + +define <1 x i128> @rotl_120(<1 x i128> %num) { +; CHECK-VSX-LABEL: rotl_120: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: vsldoi v2, v2, v2, 1 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: rotl_120: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 1 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} + +define <1 x i128> @shufflevector(<1 x i128> %num) { +; CHECK-VSX-LABEL: shufflevector: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: xxswapd v2, v2 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: shufflevector: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 8 +; CHECK-NOVSX-NEXT: blr +entry: + %0 = bitcast <1 x i128> %num to <2 x i64> + %vecins2 = shufflevector <2 x i64> %0, <2 x i64> undef, <2 x i32> + %1 = bitcast <2 x i64> %vecins2 to <1 x i128> + ret <1 x i128> %1 +} + +define <1 x i128> @rotl_28(<1 x i128> %num) { +; CHECK-VSX-LABEL: rotl_28: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: mfvsrld r4, v2 +; CHECK-VSX-NEXT: mfvsrd r3, v2 +; CHECK-VSX-NEXT: rotldi r5, r4, 28 +; CHECK-VSX-NEXT: rldimi r5, r3, 28, 0 +; CHECK-VSX-NEXT: rotldi r3, r3, 28 +; CHECK-VSX-NEXT: rldimi r3, r4, 28, 0 +; CHECK-VSX-NEXT: mtvsrdd v2, r5, r3 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: rotl_28: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: addi r3, r1, -32 +; CHECK-NOVSX-NEXT: stvx v2, 0, r3 +; CHECK-NOVSX-NEXT: ld r4, -32(r1) +; CHECK-NOVSX-NEXT: ld r3, -24(r1) +; CHECK-NOVSX-NEXT: rotldi r5, r4, 28 +; CHECK-NOVSX-NEXT: rldimi r5, r3, 28, 0 +; CHECK-NOVSX-NEXT: rotldi r3, r3, 28 +; CHECK-NOVSX-NEXT: rldimi r3, r4, 28, 0 +; CHECK-NOVSX-NEXT: std r3, -16(r1) +; CHECK-NOVSX-NEXT: addi r3, r1, -16 +; CHECK-NOVSX-NEXT: std r5, -8(r1) +; CHECK-NOVSX-NEXT: lvx v2, 0, r3 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} + +define <1 x i128> @NO_rotl(<1 x i128> %num) { +; CHECK-VSX-LABEL: NO_rotl: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: addis r3, r2, .LCPI9_0@toc@ha +; CHECK-VSX-NEXT: addi r3, r3, .LCPI9_0@toc@l +; CHECK-VSX-NEXT: lxvx v3, 0, r3 +; CHECK-VSX-NEXT: addis r3, r2, .LCPI9_1@toc@ha +; CHECK-VSX-NEXT: addi r3, r3, .LCPI9_1@toc@l +; CHECK-VSX-NEXT: vslo v4, v2, v3 +; CHECK-VSX-NEXT: vspltb v3, v3, 15 +; CHECK-VSX-NEXT: vsl v3, v4, v3 +; CHECK-VSX-NEXT: lxvx v4, 0, r3 +; CHECK-VSX-NEXT: vsro v2, v2, v4 +; CHECK-VSX-NEXT: vspltb v4, v4, 15 +; CHECK-VSX-NEXT: vsr v2, v2, v4 +; CHECK-VSX-NEXT: xxlor v2, v3, v2 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: NO_rotl: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI9_0@toc@ha +; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI9_0@toc@l +; CHECK-NOVSX-NEXT: lvx v3, 0, r3 +; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI9_1@toc@ha +; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI9_1@toc@l +; CHECK-NOVSX-NEXT: vslo v4, v2, v3 +; CHECK-NOVSX-NEXT: vspltb v3, v3, 15 +; CHECK-NOVSX-NEXT: vsl v3, v4, v3 +; CHECK-NOVSX-NEXT: lvx v4, 0, r3 +; CHECK-NOVSX-NEXT: vsro v2, v2, v4 +; CHECK-NOVSX-NEXT: vspltb v4, v4, 15 +; CHECK-NOVSX-NEXT: vsr v2, v2, v4 +; CHECK-NOVSX-NEXT: vor v2, v3, v2 +; CHECK-NOVSX-NEXT: blr +entry: + %shl = shl <1 x i128> %num, + %shr = lshr <1 x i128> %num, + %or = or <1 x i128> %shl, %shr + ret <1 x i128> %or +} +