diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td --- a/llvm/lib/Target/AMDGPU/SISchedule.td +++ b/llvm/lib/Target/AMDGPU/SISchedule.td @@ -199,19 +199,19 @@ // Add 1 stall cycle for VGPR read. def : HWWriteRes; def : HWWriteRes; -def : HWWriteRes; -def : HWWriteRes; -def : HWWriteRes; +def : HWWriteRes; +def : HWWriteRes; +def : HWWriteRes; def : HWWriteRes; -def : HWWriteRes; -def : HWWriteRes; -def : HWWriteRes; -def : HWWriteRes; +def : HWWriteRes; +def : HWWriteRes; +def : HWWriteRes; +def : HWWriteRes; def : HWWriteRes; def : HWWriteRes; def : HWWriteRes; -def : HWWriteRes; +def : HWWriteRes; def : HWWriteRes; def : HWWriteRes; def : HWWriteRes; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll @@ -85,9 +85,9 @@ ; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_mov_b32 s33, s6 -; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) @@ -187,9 +187,9 @@ ; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_mov_b32 s33, s6 -; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) @@ -288,15 +288,15 @@ ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_add_u32 s4, s32, 0x3e0 ; GFX10-NEXT: s_mov_b32 s6, s33 -; GFX10-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_and_b32 s33, s4, 0xfffffc00 ; GFX10-NEXT: s_add_u32 s32, s32, 0x800 ; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_add_u32 s4, s4, gv@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+4 -; GFX10-NEXT: s_mov_b32 s33, s6 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_mov_b32 s33, s6 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll @@ -233,10 +233,10 @@ ; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: v_mov_b32_e32 v16, s7 +; MOVREL-NEXT: v_mov_b32_e32 v15, s6 ; MOVREL-NEXT: v_mov_b32_e32 v14, s5 -; MOVREL-NEXT: v_mov_b32_e32 v12, s3 ; MOVREL-NEXT: v_mov_b32_e32 v13, s4 -; MOVREL-NEXT: v_mov_b32_e32 v15, s6 +; MOVREL-NEXT: v_mov_b32_e32 v12, s3 ; MOVREL-NEXT: v_mov_b32_e32 v11, s2 ; MOVREL-NEXT: v_mov_b32_e32 v10, s1 ; MOVREL-NEXT: v_mov_b32_e32 v9, s0 @@ -400,10 +400,10 @@ ; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: v_mov_b32_e32 v17, s7 +; MOVREL-NEXT: v_mov_b32_e32 v16, s6 ; MOVREL-NEXT: v_mov_b32_e32 v15, s5 -; MOVREL-NEXT: v_mov_b32_e32 v13, s3 ; MOVREL-NEXT: v_mov_b32_e32 v14, s4 -; MOVREL-NEXT: v_mov_b32_e32 v16, s6 +; MOVREL-NEXT: v_mov_b32_e32 v13, s3 ; MOVREL-NEXT: v_mov_b32_e32 v12, s2 ; MOVREL-NEXT: v_mov_b32_e32 v11, s1 ; MOVREL-NEXT: v_mov_b32_e32 v10, s0 @@ -800,10 +800,10 @@ ; MOVREL-NEXT: s_mov_b32 s18, 0 ; MOVREL-NEXT: s_mov_b32 s19, 0x40200000 ; MOVREL-NEXT: s_mov_b32 s17, 0x401c0000 -; MOVREL-NEXT: s_mov_b32 s15, 0x40180000 -; MOVREL-NEXT: s_mov_b32 s13, 0x40140000 ; MOVREL-NEXT: s_mov_b32 s16, s18 +; MOVREL-NEXT: s_mov_b32 s15, 0x40180000 ; MOVREL-NEXT: s_mov_b32 s14, s18 +; MOVREL-NEXT: s_mov_b32 s13, 0x40140000 ; MOVREL-NEXT: s_mov_b32 s12, s18 ; MOVREL-NEXT: s_mov_b64 s[10:11], 4.0 ; MOVREL-NEXT: s_mov_b32 s9, 0x40080000 @@ -834,8 +834,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22 -; MOVREL-NEXT: s_lshl_b32 m0, s5, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s5, v2 +; MOVREL-NEXT: s_lshl_b32 m0, s5, 1 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25 @@ -966,10 +966,10 @@ ; MOVREL-NEXT: s_mov_b32 s12, s14 ; MOVREL-NEXT: s_mov_b32 s14, s16 ; MOVREL-NEXT: v_mov_b32_e32 v32, s15 +; MOVREL-NEXT: v_mov_b32_e32 v31, s14 ; MOVREL-NEXT: v_mov_b32_e32 v30, s13 -; MOVREL-NEXT: v_mov_b32_e32 v28, s11 ; MOVREL-NEXT: v_mov_b32_e32 v29, s12 -; MOVREL-NEXT: v_mov_b32_e32 v31, s14 +; MOVREL-NEXT: v_mov_b32_e32 v28, s11 ; MOVREL-NEXT: v_mov_b32_e32 v27, s10 ; MOVREL-NEXT: v_mov_b32_e32 v26, s9 ; MOVREL-NEXT: v_mov_b32_e32 v25, s8 @@ -989,8 +989,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v2, v18 ; MOVREL-NEXT: v_mov_b32_e32 v3, v19 ; MOVREL-NEXT: v_mov_b32_e32 v4, v20 -; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v0 +; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23 @@ -1095,8 +1095,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v17, s15 ; MOVREL-NEXT: v_mov_b32_e32 v2, s0 ; MOVREL-NEXT: s_lshl_b32 m0, s18, 1 -; MOVREL-NEXT: v_mov_b32_e32 v15, s13 ; MOVREL-NEXT: v_mov_b32_e32 v16, s14 +; MOVREL-NEXT: v_mov_b32_e32 v15, s13 ; MOVREL-NEXT: v_mov_b32_e32 v14, s12 ; MOVREL-NEXT: v_mov_b32_e32 v13, s11 ; MOVREL-NEXT: v_mov_b32_e32 v12, s10 @@ -1260,10 +1260,10 @@ ; MOVREL-NEXT: s_mov_b32 s12, s14 ; MOVREL-NEXT: s_mov_b32 s14, s16 ; MOVREL-NEXT: v_mov_b32_e32 v34, s15 +; MOVREL-NEXT: v_mov_b32_e32 v33, s14 ; MOVREL-NEXT: v_mov_b32_e32 v32, s13 -; MOVREL-NEXT: v_mov_b32_e32 v30, s11 ; MOVREL-NEXT: v_mov_b32_e32 v31, s12 -; MOVREL-NEXT: v_mov_b32_e32 v33, s14 +; MOVREL-NEXT: v_mov_b32_e32 v30, s11 ; MOVREL-NEXT: v_mov_b32_e32 v29, s10 ; MOVREL-NEXT: v_mov_b32_e32 v28, s9 ; MOVREL-NEXT: v_mov_b32_e32 v27, s8 @@ -1283,8 +1283,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22 -; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2 +; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25 @@ -1373,8 +1373,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v17, v0 ; MOVREL-NEXT: v_mov_b32_e32 v31, v14 ; MOVREL-NEXT: v_mov_b32_e32 v30, v13 -; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v16 +; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_mov_b32_e32 v29, v12 ; MOVREL-NEXT: v_mov_b32_e32 v28, v11 ; MOVREL-NEXT: v_mov_b32_e32 v27, v10 @@ -1501,8 +1501,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v19, v0 ; MOVREL-NEXT: v_mov_b32_e32 v33, v14 ; MOVREL-NEXT: v_mov_b32_e32 v32, v13 -; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18 +; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_mov_b32_e32 v31, v12 ; MOVREL-NEXT: v_mov_b32_e32 v30, v11 ; MOVREL-NEXT: v_mov_b32_e32 v29, v10 @@ -1557,8 +1557,8 @@ ; MOVREL-NEXT: s_mov_b32 m0, s6 ; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s2, s4 -; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: s_movreld_b32 s0, s5 +; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; return to shader part epilog entry: %insert = insertelement <3 x i32> %vec, i32 %val, i32 %idx @@ -2135,10 +2135,10 @@ ; MOVREL-NEXT: v_mov_b32_e32 v32, v13 ; MOVREL-NEXT: s_add_i32 s2, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18 +; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: v_mov_b32_e32 v31, v12 ; MOVREL-NEXT: v_mov_b32_e32 v30, v11 ; MOVREL-NEXT: v_mov_b32_e32 v29, v10 -; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: v_mov_b32_e32 v28, v9 ; MOVREL-NEXT: v_mov_b32_e32 v27, v8 ; MOVREL-NEXT: v_mov_b32_e32 v26, v7 @@ -2696,10 +2696,10 @@ ; MOVREL-NEXT: s_mov_b32 s12, s14 ; MOVREL-NEXT: s_mov_b32 s14, s16 ; MOVREL-NEXT: v_mov_b32_e32 v16, s15 -; MOVREL-NEXT: s_mov_b32 m0, s18 ; MOVREL-NEXT: v_mov_b32_e32 v1, s0 -; MOVREL-NEXT: v_mov_b32_e32 v14, s13 +; MOVREL-NEXT: s_mov_b32 m0, s18 ; MOVREL-NEXT: v_mov_b32_e32 v15, s14 +; MOVREL-NEXT: v_mov_b32_e32 v14, s13 ; MOVREL-NEXT: v_mov_b32_e32 v13, s12 ; MOVREL-NEXT: v_mov_b32_e32 v12, s11 ; MOVREL-NEXT: v_mov_b32_e32 v11, s10 @@ -2927,8 +2927,8 @@ ; MOVREL-NEXT: s_mov_b32 s28, s30 ; MOVREL-NEXT: s_mov_b32 s29, s31 ; MOVREL-NEXT: s_mov_b32 s31, s33 -; MOVREL-NEXT: s_mov_b32 s30, s32 ; MOVREL-NEXT: v_mov_b32_e32 v32, v0 +; MOVREL-NEXT: s_mov_b32 s30, s32 ; MOVREL-NEXT: v_mov_b32_e32 v0, s0 ; MOVREL-NEXT: s_mov_b32 m0, s34 ; MOVREL-NEXT: v_mov_b32_e32 v1, s1 @@ -3113,8 +3113,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v33, s31 ; MOVREL-NEXT: v_mov_b32_e32 v2, s0 ; MOVREL-NEXT: s_lshl_b32 m0, s34, 1 -; MOVREL-NEXT: v_mov_b32_e32 v31, s29 ; MOVREL-NEXT: v_mov_b32_e32 v32, s30 +; MOVREL-NEXT: v_mov_b32_e32 v31, s29 ; MOVREL-NEXT: v_mov_b32_e32 v30, s28 ; MOVREL-NEXT: v_mov_b32_e32 v29, s27 ; MOVREL-NEXT: v_mov_b32_e32 v28, s26 @@ -3327,8 +3327,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v33, s31 ; MOVREL-NEXT: v_mov_b32_e32 v2, s0 ; MOVREL-NEXT: s_lshl_b32 m0, s34, 1 -; MOVREL-NEXT: v_mov_b32_e32 v31, s29 ; MOVREL-NEXT: v_mov_b32_e32 v32, s30 +; MOVREL-NEXT: v_mov_b32_e32 v31, s29 ; MOVREL-NEXT: v_mov_b32_e32 v30, s28 ; MOVREL-NEXT: v_mov_b32_e32 v29, s27 ; MOVREL-NEXT: v_mov_b32_e32 v28, s26 @@ -3567,10 +3567,10 @@ ; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: v_mov_b32_e32 v17, s7 -; MOVREL-NEXT: v_mov_b32_e32 v13, s3 -; MOVREL-NEXT: v_mov_b32_e32 v14, s4 -; MOVREL-NEXT: v_mov_b32_e32 v15, s5 ; MOVREL-NEXT: v_mov_b32_e32 v16, s6 +; MOVREL-NEXT: v_mov_b32_e32 v15, s5 +; MOVREL-NEXT: v_mov_b32_e32 v14, s4 +; MOVREL-NEXT: v_mov_b32_e32 v13, s3 ; MOVREL-NEXT: v_mov_b32_e32 v12, s2 ; MOVREL-NEXT: v_mov_b32_e32 v11, s1 ; MOVREL-NEXT: v_mov_b32_e32 v10, s0 @@ -3949,9 +3949,9 @@ ; MOVREL-NEXT: s_mov_b32 s13, s15 ; MOVREL-NEXT: v_mov_b32_e32 v34, s15 ; MOVREL-NEXT: v_mov_b32_e32 v33, s14 -; MOVREL-NEXT: v_mov_b32_e32 v30, s11 -; MOVREL-NEXT: v_mov_b32_e32 v31, s12 ; MOVREL-NEXT: v_mov_b32_e32 v32, s13 +; MOVREL-NEXT: v_mov_b32_e32 v31, s12 +; MOVREL-NEXT: v_mov_b32_e32 v30, s11 ; MOVREL-NEXT: v_mov_b32_e32 v29, s10 ; MOVREL-NEXT: v_mov_b32_e32 v28, s9 ; MOVREL-NEXT: v_mov_b32_e32 v27, s8 @@ -3971,8 +3971,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22 -; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2 +; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25 @@ -4039,8 +4039,8 @@ ; ; MOVREL-LABEL: dyn_insertelement_v7f64_v_v_s: ; MOVREL: ; %bb.0: ; %entry -; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: v_mov_b32_e32 v16, v15 +; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: v_movreld_b32_e32 v0, v14 ; MOVREL-NEXT: v_movreld_b32_e32 v1, v16 @@ -4125,8 +4125,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v17, v0 ; MOVREL-NEXT: v_mov_b32_e32 v31, v14 ; MOVREL-NEXT: v_mov_b32_e32 v30, v13 -; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v16 +; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_mov_b32_e32 v29, v12 ; MOVREL-NEXT: v_mov_b32_e32 v28, v11 ; MOVREL-NEXT: v_mov_b32_e32 v27, v10 @@ -4408,8 +4408,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v4, v20 ; MOVREL-NEXT: v_mov_b32_e32 v5, v21 ; MOVREL-NEXT: v_mov_b32_e32 v6, v22 -; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2 +; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_mov_b32_e32 v7, v23 ; MOVREL-NEXT: v_mov_b32_e32 v8, v24 ; MOVREL-NEXT: v_mov_b32_e32 v9, v25 @@ -4468,8 +4468,8 @@ ; ; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_s: ; MOVREL: ; %bb.0: ; %entry -; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: v_mov_b32_e32 v16, v11 +; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: v_movreld_b32_e32 v0, v10 ; MOVREL-NEXT: v_movreld_b32_e32 v1, v16 @@ -4558,8 +4558,8 @@ ; MOVREL-NEXT: v_mov_b32_e32 v15, v2 ; MOVREL-NEXT: v_mov_b32_e32 v14, v1 ; MOVREL-NEXT: v_mov_b32_e32 v13, v0 -; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v12 +; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_movreld_b32_e32 v13, v10 ; MOVREL-NEXT: v_movreld_b32_e32 v14, v11 ; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll @@ -118,8 +118,8 @@ ; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s1 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s2 -; GFX10_W32-NEXT: ; implicit-def: $vcc_hi ; GFX10_W32-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10_W32-NEXT: ; implicit-def: $vcc_hi ; GFX10_W32-NEXT: s_and_b32 s3, 1, s3 ; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1 @@ -129,8 +129,8 @@ ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s1 -; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2 ; GFX10_W64-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2 ; GFX10_W64-NEXT: s_and_b32 s3, 1, s3 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, s0, v0, v1 @@ -197,12 +197,12 @@ ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_cmp_eq_u32 s6, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 -; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4 -; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3 -; GFX10_W64-NEXT: v_mov_b32_e32 v3, s5 ; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4 ; GFX10_W64-NEXT: s_and_b32 s6, 1, s6 +; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 +; GFX10_W64-NEXT: v_mov_b32_e32 v3, s5 ; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3] ; GFX10_W64-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10_W64-NEXT: v_readfirstlane_b32 s1, v1 @@ -284,8 +284,8 @@ ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s3 -; GFX10_W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; GFX10_W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX10_W64-NEXT: v_div_fmas_f32 v2, s5, v0, v1 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s1 @@ -593,9 +593,9 @@ ; GFX10_W64-NEXT: s_and_b32 s8, 1, s8 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s4 ; GFX10_W64-NEXT: v_mov_b32_e32 v2, s6 +; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s5 ; GFX10_W64-NEXT: v_mov_b32_e32 v3, s7 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8 ; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[2:3], v[0:1], v[2:3] ; GFX10_W64-NEXT: v_mov_b32_e32 v3, s1 ; GFX10_W64-NEXT: v_mov_b32_e32 v2, s0 @@ -672,8 +672,8 @@ ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_cmp_eq_u32 s7, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s5 -; GFX10_W64-NEXT: v_mov_b32_e32 v1, s6 ; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10_W64-NEXT: v_mov_b32_e32 v1, s6 ; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 ; GFX10_W64-NEXT: v_div_fmas_f32 v2, s4, v0, v1 @@ -912,11 +912,11 @@ ; GFX10_W32-NEXT: v_add_co_u32_e64 v1, vcc_lo, v3, v1 ; GFX10_W32-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10_W32-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo -; GFX10_W32-NEXT: v_add_co_u32_e64 v3, vcc_lo, v1, 8 ; GFX10_W32-NEXT: s_and_b32 s2, 1, s2 +; GFX10_W32-NEXT: v_add_co_u32_e64 v3, vcc_lo, v1, 8 +; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s2, 0, s2 ; GFX10_W32-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo ; GFX10_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s2, 0, s2 ; GFX10_W32-NEXT: s_clause 0x2 ; GFX10_W32-NEXT: global_load_dword v1, v[1:2], off ; GFX10_W32-NEXT: global_load_dword v2, v[3:4], off offset:-4 @@ -944,11 +944,11 @@ ; GFX10_W64-NEXT: v_add_co_u32_e64 v1, vcc, v3, v1 ; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0 ; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, v4, v2, vcc -; GFX10_W64-NEXT: v_add_co_u32_e64 v3, vcc, v1, 8 ; GFX10_W64-NEXT: s_and_b32 s2, 1, s2 +; GFX10_W64-NEXT: v_add_co_u32_e64 v3, vcc, v1, 8 +; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 ; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v4, vcc, 0, v2, vcc ; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 ; GFX10_W64-NEXT: s_clause 0x2 ; GFX10_W64-NEXT: global_load_dword v1, v[1:2], off ; GFX10_W64-NEXT: global_load_dword v2, v[3:4], off offset:-4 @@ -1093,7 +1093,7 @@ ; GFX10_W64: ; %bb.0: ; %entry ; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c ; GFX10_W64-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX10_W64-NEXT: s_mov_b32 s4, 0 +; GFX10_W64-NEXT: s_mov_b32 s6, 0 ; GFX10_W64-NEXT: v_lshlrev_b64 v[1:2], 2, v[0:1] ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: v_mov_b32_e32 v4, s3 @@ -1103,7 +1103,7 @@ ; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, v4, v2, vcc ; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10_W64-NEXT: global_load_dwordx3 v[1:3], v[1:2], off -; GFX10_W64-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GFX10_W64-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX10_W64-NEXT: s_cbranch_execz BB13_2 ; GFX10_W64-NEXT: ; %bb.1: ; %bb ; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74 @@ -1111,11 +1111,11 @@ ; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10_W64-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10_W64-NEXT: BB13_2: ; %exit ; GFX10_W64-NEXT: v_nop -; GFX10_W64-NEXT: s_or_b64 exec, exec, s[6:7] -; GFX10_W64-NEXT: s_and_b32 s0, 1, s4 +; GFX10_W64-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX10_W64-NEXT: s_and_b32 s0, 1, s6 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_add_u32 s0, s2, 8 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll @@ -482,11 +482,11 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -519,19 +519,19 @@ ; ; GFX10-LABEL: atomic_add_i32_3d: ; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2 +; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -564,19 +564,19 @@ ; ; GFX10-LABEL: atomic_add_i32_cube: ; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2 +; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -612,11 +612,11 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -649,19 +649,19 @@ ; ; GFX10-LABEL: atomic_add_i32_2darray: ; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2 +; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -694,19 +694,19 @@ ; ; GFX10-LABEL: atomic_add_i32_2dmsaa: ; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2 +; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -745,13 +745,13 @@ ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v2 +; GFX10-NEXT: v_and_or_b32 v2, v3, v5, v4 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v2 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v2, v3, v5, v4 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -1277,11 +1277,11 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -1314,19 +1314,19 @@ ; ; GFX10-LABEL: atomic_add_i64_3d: ; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3 +; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -1359,19 +1359,19 @@ ; ; GFX10-LABEL: atomic_add_i64_cube: ; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3 +; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -1407,11 +1407,11 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -1444,19 +1444,19 @@ ; ; GFX10-LABEL: atomic_add_i64_2darray: ; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3 +; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -1489,19 +1489,19 @@ ; ; GFX10-LABEL: atomic_add_i64_2dmsaa: ; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3 +; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -1540,13 +1540,13 @@ ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: v_and_or_b32 v2, v2, v6, v3 +; GFX10-NEXT: v_and_or_b32 v3, v4, v6, v5 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v2, v2, v6, v3 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v3, v4, v6, v5 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll @@ -588,23 +588,23 @@ ; ; GFX10NSA-LABEL: gather4_l_2d: ; GFX10NSA: ; %bb.0: ; %main_body +; GFX10NSA-NEXT: v_mov_b32_e32 v3, 0xffff +; GFX10NSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10NSA-NEXT: s_mov_b32 s0, s2 ; GFX10NSA-NEXT: s_mov_b32 s2, s4 ; GFX10NSA-NEXT: s_mov_b32 s4, s6 ; GFX10NSA-NEXT: s_mov_b32 s6, s8 ; GFX10NSA-NEXT: s_mov_b32 s8, s10 ; GFX10NSA-NEXT: s_mov_b32 s10, s12 -; GFX10NSA-NEXT: v_mov_b32_e32 v3, 0xffff -; GFX10NSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10NSA-NEXT: s_lshl_b32 s12, s0, 16 +; GFX10NSA-NEXT: v_and_or_b32 v0, v0, v3, v1 +; GFX10NSA-NEXT: v_and_or_b32 v1, v2, v3, s12 ; GFX10NSA-NEXT: s_mov_b32 s1, s3 ; GFX10NSA-NEXT: s_mov_b32 s3, s5 ; GFX10NSA-NEXT: s_mov_b32 s5, s7 ; GFX10NSA-NEXT: s_mov_b32 s7, s9 ; GFX10NSA-NEXT: s_mov_b32 s9, s11 -; GFX10NSA-NEXT: v_and_or_b32 v0, v0, v3, v1 ; GFX10NSA-NEXT: s_mov_b32 s11, s13 -; GFX10NSA-NEXT: v_and_or_b32 v1, v2, v3, s12 ; GFX10NSA-NEXT: ; implicit-def: $vcc_hi ; GFX10NSA-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) @@ -640,23 +640,23 @@ ; ; GFX10NSA-LABEL: gather4_c_l_2d: ; GFX10NSA: ; %bb.0: ; %main_body +; GFX10NSA-NEXT: v_mov_b32_e32 v4, 0xffff +; GFX10NSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10NSA-NEXT: s_mov_b32 s0, s2 ; GFX10NSA-NEXT: s_mov_b32 s2, s4 ; GFX10NSA-NEXT: s_mov_b32 s4, s6 ; GFX10NSA-NEXT: s_mov_b32 s6, s8 ; GFX10NSA-NEXT: s_mov_b32 s8, s10 ; GFX10NSA-NEXT: s_mov_b32 s10, s12 -; GFX10NSA-NEXT: v_mov_b32_e32 v4, 0xffff -; GFX10NSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX10NSA-NEXT: s_lshl_b32 s12, s0, 16 +; GFX10NSA-NEXT: v_and_or_b32 v1, v1, v4, v2 +; GFX10NSA-NEXT: v_and_or_b32 v2, v3, v4, s12 ; GFX10NSA-NEXT: s_mov_b32 s1, s3 ; GFX10NSA-NEXT: s_mov_b32 s3, s5 ; GFX10NSA-NEXT: s_mov_b32 s5, s7 ; GFX10NSA-NEXT: s_mov_b32 s7, s9 ; GFX10NSA-NEXT: s_mov_b32 s9, s11 -; GFX10NSA-NEXT: v_and_or_b32 v1, v1, v4, v2 ; GFX10NSA-NEXT: s_mov_b32 s11, s13 -; GFX10NSA-NEXT: v_and_or_b32 v2, v3, v4, s12 ; GFX10NSA-NEXT: ; implicit-def: $vcc_hi ; GFX10NSA-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) @@ -695,6 +695,7 @@ ; GFX10NSA-NEXT: s_mov_b32 s1, s3 ; GFX10NSA-NEXT: s_mov_b32 s2, s4 ; GFX10NSA-NEXT: s_mov_b32 s3, s5 +; GFX10NSA-NEXT: v_and_or_b32 v0, v0, 0xffff, v1 ; GFX10NSA-NEXT: s_mov_b32 s4, s6 ; GFX10NSA-NEXT: s_mov_b32 s5, s7 ; GFX10NSA-NEXT: s_mov_b32 s6, s8 @@ -703,7 +704,6 @@ ; GFX10NSA-NEXT: s_mov_b32 s9, s11 ; GFX10NSA-NEXT: s_mov_b32 s10, s12 ; GFX10NSA-NEXT: s_mov_b32 s11, s13 -; GFX10NSA-NEXT: v_and_or_b32 v0, v0, 0xffff, v1 ; GFX10NSA-NEXT: ; implicit-def: $vcc_hi ; GFX10NSA-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) @@ -742,6 +742,7 @@ ; GFX10NSA-NEXT: s_mov_b32 s1, s3 ; GFX10NSA-NEXT: s_mov_b32 s2, s4 ; GFX10NSA-NEXT: s_mov_b32 s3, s5 +; GFX10NSA-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10NSA-NEXT: s_mov_b32 s4, s6 ; GFX10NSA-NEXT: s_mov_b32 s5, s7 ; GFX10NSA-NEXT: s_mov_b32 s6, s8 @@ -750,7 +751,6 @@ ; GFX10NSA-NEXT: s_mov_b32 s9, s11 ; GFX10NSA-NEXT: s_mov_b32 s10, s12 ; GFX10NSA-NEXT: s_mov_b32 s11, s13 -; GFX10NSA-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10NSA-NEXT: ; implicit-def: $vcc_hi ; GFX10NSA-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll @@ -67,9 +67,9 @@ ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 @@ -113,9 +113,9 @@ ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe lwe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe lwe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll @@ -30,13 +30,13 @@ ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1 +; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -77,17 +77,17 @@ ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1 +; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 @@ -131,17 +131,17 @@ ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1 +; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1 ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll @@ -67,9 +67,9 @@ ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 @@ -113,9 +113,9 @@ ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe lwe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe lwe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll @@ -24,19 +24,19 @@ ; ; GFX10-LABEL: load_3d_v4f32_xyzw: ; GFX10: ; %bb.0: +; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1 +; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -71,23 +71,23 @@ ; ; GFX10-LABEL: load_3d_v4f32_xyzw_tfe: ; GFX10: ; %bb.0: +; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1 +; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 @@ -125,23 +125,23 @@ ; ; GFX10-LABEL: load_3d_v4f32_xyzw_tfe_lwe: ; GFX10: ; %bb.0: +; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff +; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s6, s8 -; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff -; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX10-NEXT: s_lshl_b32 s8, s0, 16 +; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1 +; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8 ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 -; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1 ; GFX10-NEXT: s_mov_b32 s7, s9 -; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll @@ -67,9 +67,9 @@ ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 @@ -113,9 +113,9 @@ ; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v5, s10 +; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe lwe ; GFX10-NEXT: v_mov_b32_e32 v6, s11 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe lwe ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[5:6], v4, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll @@ -73,6 +73,7 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 @@ -81,7 +82,6 @@ ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -123,12 +123,12 @@ ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_lshl_b32 s12, s0, 16 ; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -167,6 +167,7 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 @@ -175,7 +176,6 @@ ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -217,12 +217,12 @@ ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_lshl_b32 s12, s0, 16 ; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -261,6 +261,7 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 @@ -269,7 +270,6 @@ ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -311,12 +311,12 @@ ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_lshl_b32 s12, s0, 16 ; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, s12 ; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, s12 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -355,6 +355,7 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 @@ -363,7 +364,6 @@ ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -402,6 +402,7 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 @@ -410,7 +411,6 @@ ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -449,6 +449,7 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 @@ -457,7 +458,6 @@ ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -496,6 +496,7 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 @@ -504,7 +505,6 @@ ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_gather4_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -543,6 +543,7 @@ ; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3 ; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s6, s8 @@ -551,7 +552,6 @@ ; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s11, s13 -; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_gather4_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX10-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll @@ -593,9 +593,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 0) call void asm sideeffect "", ""() @@ -614,9 +614,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x1 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 1) call void asm sideeffect "", ""() @@ -635,9 +635,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x2 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 2) call void asm sideeffect "", ""() @@ -656,9 +656,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x4 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 4) call void asm sideeffect "", ""() @@ -677,9 +677,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x8 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 8) call void asm sideeffect "", ""() @@ -698,9 +698,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 1 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 1 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 16) call void asm sideeffect "", ""() @@ -719,9 +719,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 2 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 2 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 32) call void asm sideeffect "", ""() @@ -740,9 +740,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 4 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 4 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 64) call void asm sideeffect "", ""() @@ -761,9 +761,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 8 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 8 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 128) call void asm sideeffect "", ""() @@ -782,9 +782,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0xf ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 15) call void asm sideeffect "", ""() @@ -803,9 +803,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0xf ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 15 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 15 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 255) call void asm sideeffect "", ""() @@ -825,9 +825,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x5 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 5 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 5 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 597) call void asm sideeffect "", ""() diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll @@ -69,8 +69,8 @@ ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_movk_i32 s5, 0xff -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1 ; GFX10-NEXT: v_and_b32_e32 v1, s5, v2 ; GFX10-NEXT: v_and_b32_e32 v2, s5, v3 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll @@ -69,8 +69,8 @@ ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_mov_b32 s4, 8 ; GFX10-NEXT: s_movk_i32 s5, 0xff -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1 ; GFX10-NEXT: v_and_b32_e32 v1, s5, v2 ; GFX10-NEXT: v_and_b32_e32 v2, s5, v3 diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll @@ -105,8 +105,8 @@ ; ; GFX1064-LABEL: add_i32_constant: ; GFX1064: ; %bb.0: ; %entry -; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 @@ -140,8 +140,8 @@ ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_mov_b32 s2, exec_lo ; GFX1032-NEXT: ; implicit-def: $vcc_hi -; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_cbranch_execz BB0_2 @@ -275,10 +275,10 @@ ; ; GFX1064-LABEL: add_i32_uniform: ; GFX1064: ; %bb.0: ; %entry -; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_clause 0x1 ; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 @@ -316,8 +316,8 @@ ; GFX1032-NEXT: s_load_dword s0, s[0:1], 0x2c ; GFX1032-NEXT: s_mov_b32 s2, exec_lo ; GFX1032-NEXT: ; implicit-def: $vcc_hi -; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX1032-NEXT: s_cbranch_execz BB1_2 @@ -1174,8 +1174,8 @@ ; ; GFX1064-LABEL: add_i64_constant: ; GFX1064: ; %bb.0: ; %entry -; GFX1064-NEXT: s_mov_b64 s[4:5], exec ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: s_mov_b64 s[4:5], exec ; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s5, v0 @@ -1211,8 +1211,8 @@ ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: ; implicit-def: $vcc_hi -; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0 +; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_cbranch_execz BB5_2 @@ -1381,8 +1381,8 @@ ; ; GFX1064-LABEL: add_i64_uniform: ; GFX1064: ; %bb.0: ; %entry -; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s7, v0 @@ -1412,13 +1412,13 @@ ; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX1064-NEXT: v_mul_lo_u32 v0, s2, v0 -; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 -; GFX1064-NEXT: v_readfirstlane_b32 s5, v2 +; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s4, v2 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3 -; GFX1064-NEXT: v_add_co_u32_e64 v0, vcc, s4, v0 -; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s5, v1, vcc +; GFX1064-NEXT: v_add_co_u32_e64 v0, vcc, s2, v0 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s4, v1, vcc ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: s_endpgm ; @@ -1427,8 +1427,8 @@ ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: ; implicit-def: $vcc_hi -; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s5, 0 +; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_cbranch_execz BB6_2 @@ -1455,13 +1455,13 @@ ; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 -; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 -; GFX1032-NEXT: v_readfirstlane_b32 s5, v2 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s4, v2 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3 -; GFX1032-NEXT: v_add_co_u32_e64 v0, vcc_lo, s4, v0 -; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo +; GFX1032-NEXT: v_add_co_u32_e64 v0, vcc_lo, s2, v0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: s_endpgm entry: @@ -1656,8 +1656,8 @@ ; ; GFX1064-LABEL: sub_i32_constant: ; GFX1064: ; %bb.0: ; %entry -; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 @@ -1692,8 +1692,8 @@ ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_mov_b32 s2, exec_lo ; GFX1032-NEXT: ; implicit-def: $vcc_hi -; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: s_and_saveexec_b32 s3, vcc_lo ; GFX1032-NEXT: s_cbranch_execz BB8_2 @@ -1828,10 +1828,10 @@ ; ; GFX1064-LABEL: sub_i32_uniform: ; GFX1064: ; %bb.0: ; %entry -; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: s_clause 0x1 ; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX1064-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX1064-NEXT: s_mov_b64 s[2:3], exec ; GFX1064-NEXT: ; implicit-def: $vgpr1 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 @@ -1869,8 +1869,8 @@ ; GFX1032-NEXT: s_load_dword s0, s[0:1], 0x2c ; GFX1032-NEXT: s_mov_b32 s2, exec_lo ; GFX1032-NEXT: ; implicit-def: $vcc_hi -; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: ; implicit-def: $vgpr1 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX1032-NEXT: s_cbranch_execz BB9_2 @@ -2251,8 +2251,8 @@ ; ; GFX1064-LABEL: sub_i64_constant: ; GFX1064: ; %bb.0: ; %entry -; GFX1064-NEXT: s_mov_b64 s[4:5], exec ; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: s_mov_b64 s[4:5], exec ; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s5, v0 @@ -2290,8 +2290,8 @@ ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX1032-NEXT: s_mov_b32 s3, exec_lo ; GFX1032-NEXT: ; implicit-def: $vcc_hi -; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0 +; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo ; GFX1032-NEXT: s_cbranch_execz BB11_2 @@ -2462,8 +2462,8 @@ ; ; GFX1064-LABEL: sub_i64_uniform: ; GFX1064: ; %bb.0: ; %entry -; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX1064-NEXT: s_mov_b64 s[6:7], exec ; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 ; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s7, v0 @@ -2493,13 +2493,13 @@ ; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX1064-NEXT: v_mul_lo_u32 v0, s2, v0 -; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 -; GFX1064-NEXT: v_readfirstlane_b32 s5, v2 +; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s4, v2 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3 -; GFX1064-NEXT: v_sub_co_u32_e64 v0, vcc, s4, v0 -; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s5, v1, vcc +; GFX1064-NEXT: v_sub_co_u32_e64 v0, vcc, s2, v0 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s4, v1, vcc ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: s_endpgm ; @@ -2508,8 +2508,8 @@ ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX1032-NEXT: s_mov_b32 s5, exec_lo ; GFX1032-NEXT: ; implicit-def: $vcc_hi -; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s5, 0 +; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 ; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo ; GFX1032-NEXT: s_cbranch_execz BB12_2 @@ -2536,13 +2536,13 @@ ; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 -; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 -; GFX1032-NEXT: v_readfirstlane_b32 s5, v2 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s4, v2 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3 -; GFX1032-NEXT: v_sub_co_u32_e64 v0, vcc_lo, s4, v0 -; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo +; GFX1032-NEXT: v_sub_co_u32_e64 v0, vcc_lo, s2, v0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: s_endpgm entry: @@ -3721,15 +3721,15 @@ ; GFX1064-NEXT: BB18_2: ; GFX1064-NEXT: v_nop ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX1064-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] +; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s2, -1 -; GFX1064-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[0:1] -; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc -; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc ; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: s_endpgm @@ -3756,15 +3756,15 @@ ; GFX1032-NEXT: BB18_2: ; GFX1032-NEXT: v_nop ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo +; GFX1032-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1] +; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s2, -1 -; GFX1032-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1] -; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo -; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo ; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: s_endpgm @@ -4141,15 +4141,15 @@ ; GFX1064-NEXT: BB20_2: ; GFX1064-NEXT: v_nop ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX1064-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] +; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc ; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1064-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] -; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc -; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc ; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: s_endpgm @@ -4176,15 +4176,15 @@ ; GFX1032-NEXT: BB20_2: ; GFX1032-NEXT: v_nop ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo +; GFX1032-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[0:1] +; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1032-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[4:5], v[0:1] -; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo -; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo ; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: s_endpgm @@ -4562,15 +4562,15 @@ ; GFX1064-NEXT: BB22_2: ; GFX1064-NEXT: v_nop ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_mov_b32_e32 v1, 0 ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX1064-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] +; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1064-NEXT: s_mov_b32 s2, -1 -; GFX1064-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1] -; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc -; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, s5, vcc ; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: s_endpgm @@ -4597,15 +4597,15 @@ ; GFX1032-NEXT: BB22_2: ; GFX1032-NEXT: v_nop ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_mov_b32_e32 v1, 0 ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo +; GFX1032-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1] +; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc_lo ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 ; GFX1032-NEXT: s_mov_b32 s2, -1 -; GFX1032-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1] -; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo -; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, s5, vcc_lo ; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: s_endpgm @@ -4979,15 +4979,15 @@ ; GFX1064-NEXT: BB24_2: ; GFX1064-NEXT: v_nop ; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc ; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX1064-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] +; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc ; GFX1064-NEXT: s_mov_b32 s2, -1 ; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1064-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1] -; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc -; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc ; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1064-NEXT: s_endpgm @@ -5014,15 +5014,15 @@ ; GFX1032-NEXT: BB24_2: ; GFX1032-NEXT: v_nop ; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo ; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo +; GFX1032-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[0:1] +; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX1032-NEXT: s_mov_b32 s2, -1 ; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1032-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[4:5], v[0:1] -; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo -; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo ; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX1032-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/cc-update.ll b/llvm/test/CodeGen/AMDGPU/cc-update.ll --- a/llvm/test/CodeGen/AMDGPU/cc-update.ll +++ b/llvm/test/CodeGen/AMDGPU/cc-update.ll @@ -47,9 +47,9 @@ ; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 +; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0 -; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: ; implicit-def: $vcc_hi ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX1010-NEXT: s_endpgm @@ -146,9 +146,9 @@ ; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 +; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0 -; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: s_getpc_b64 s[4:5] ; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+4 @@ -213,9 +213,9 @@ ; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 +; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0 -; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: ; implicit-def: $vcc_hi ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX1010-NEXT: s_endpgm @@ -318,9 +318,9 @@ ; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 +; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0 -; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: s_getpc_b64 s[4:5] ; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+4 @@ -382,8 +382,8 @@ ; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_mov_b32 s6, 0x20000 -; GFX1010-NEXT: ; implicit-def: $vcc_hi ; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 +; GFX1010-NEXT: ; implicit-def: $vcc_hi ; GFX1010-NEXT: s_waitcnt vmcnt(0) ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX1010-NEXT: v_nop diff --git a/llvm/test/CodeGen/AMDGPU/idot2.ll b/llvm/test/CodeGen/AMDGPU/idot2.ll --- a/llvm/test/CodeGen/AMDGPU/idot2.ll +++ b/llvm/test/CodeGen/AMDGPU/idot2.ll @@ -252,16 +252,16 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_mov_b32 s4, 0xffff -; GFX10-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_and_b32 s6, s2, s4 -; GFX10-DL-NEXT: s_and_b32 s4, s3, s4 +; GFX10-DL-NEXT: s_and_b32 s6, s2, s5 +; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 ; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16 +; GFX10-DL-NEXT: v_mul_u32_u24_e64 v0, s5, s6 ; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 16 -; GFX10-DL-NEXT: v_mul_u32_u24_e64 v0, s4, s6 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 -; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, s5, v0 +; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, s4, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off @@ -515,23 +515,23 @@ ; GFX10-DL-LABEL: idot2_MixedTypedMul: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_lshr_b32 s5, s2, 16 -; GFX10-DL-NEXT: s_lshr_b32 s6, s3, 16 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16 +; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16 +; GFX10-DL-NEXT: s_sext_i32_i16 s0, s0 +; GFX10-DL-NEXT: s_sext_i32_i16 s1, s1 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s1, s0, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2 -; GFX10-DL-NEXT: s_sext_i32_i16 s3, s3 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s3, s2, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, @@ -788,23 +788,23 @@ ; GFX10-DL-LABEL: idot2_MixedExt: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_ashr_i32 s5, s2, 16 -; GFX10-DL-NEXT: s_ashr_i32 s6, s3, 16 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_ashr_i32 s2, s0, 16 +; GFX10-DL-NEXT: s_ashr_i32 s3, s1, 16 +; GFX10-DL-NEXT: s_sext_i32_i16 s0, s0 +; GFX10-DL-NEXT: s_and_b32 s1, s1, 0xffff +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s1, s0, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2 -; GFX10-DL-NEXT: s_and_b32 s3, s3, 0xffff -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s3, s2, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, @@ -917,13 +917,13 @@ ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_load_dword s2, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s3, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16 -; GFX10-DL-NEXT: s_and_b32 s3, s3, 0xffff -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s2, s4 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s3, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s2, s3 +; GFX10-DL-NEXT: s_and_b32 s2, s4, 0xffff +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s2, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off @@ -1320,24 +1320,24 @@ ; GFX10-DL-LABEL: notudot2_v4i16_Even: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX10-DL-NEXT: s_mov_b32 s7, 0xffff ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s6, s[0:1], 0x0 -; GFX10-DL-NEXT: s_mov_b32 s7, 0xffff +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_and_b32 s3, s3, s7 -; GFX10-DL-NEXT: s_and_b32 s5, s5, s7 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 -; GFX10-DL-NEXT: s_and_b32 s2, s2, s7 -; GFX10-DL-NEXT: s_and_b32 s4, s4, s7 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s3, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s2, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: s_and_b32 s1, s1, s7 +; GFX10-DL-NEXT: s_and_b32 s3, s3, s7 +; GFX10-DL-NEXT: s_and_b32 s0, s0, s7 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s1, v0 +; GFX10-DL-NEXT: s_and_b32 s1, s2, s7 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v0 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <4 x i16> addrspace(1)* %src2, @@ -1466,24 +1466,24 @@ ; GFX10-DL-LABEL: notudot2_v4i16_Middle: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX10-DL-NEXT: s_mov_b32 s7, 0xffff ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s6, s[0:1], 0x0 -; GFX10-DL-NEXT: s_mov_b32 s7, 0xffff +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_and_b32 s3, s3, s7 -; GFX10-DL-NEXT: s_and_b32 s5, s5, s7 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 -; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16 -; GFX10-DL-NEXT: s_lshr_b32 s4, s4, 16 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s3, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s2, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: s_and_b32 s1, s1, s7 +; GFX10-DL-NEXT: s_and_b32 s3, s3, s7 +; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 16 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s1, v0 +; GFX10-DL-NEXT: s_lshr_b32 s1, s2, 16 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v0 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <4 x i16> addrspace(1)* %src2, @@ -1612,24 +1612,24 @@ ; GFX10-DL-LABEL: notudot2_DiffIndex: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 -; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 +; GFX10-DL-NEXT: s_mov_b32 s2, 0xffff ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_lshr_b32 s6, s2, 16 -; GFX10-DL-NEXT: s_and_b32 s7, s3, s5 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 16 +; GFX10-DL-NEXT: s_and_b32 s6, s1, s2 +; GFX10-DL-NEXT: s_and_b32 s0, s0, s2 +; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 16 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s3, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_and_b32 s2, s2, s5 -; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 16 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s7, s6, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, @@ -1762,25 +1762,25 @@ ; GFX10-DL-LABEL: udot2_MultipleUses_add1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 -; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_lshr_b32 s6, s2, 16 -; GFX10-DL-NEXT: s_lshr_b32 s7, s3, 16 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_and_b32 s2, s2, s5 -; GFX10-DL-NEXT: s_and_b32 s3, s3, s5 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s7, s6, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s3, s2, v0 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16 +; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16 +; GFX10-DL-NEXT: s_mov_b32 s6, 0xffff +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 +; GFX10-DL-NEXT: s_and_b32 s0, s0, s6 +; GFX10-DL-NEXT: s_and_b32 s1, s1, s6 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s1, s0, v0 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, @@ -1910,24 +1910,24 @@ ; GFX10-DL-LABEL: idot2_MultipleUses_add1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_ashr_i32 s5, s2, 16 -; GFX10-DL-NEXT: s_ashr_i32 s6, s3, 16 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2 -; GFX10-DL-NEXT: s_sext_i32_i16 s3, s3 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v1, s3, s2, v0 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_ashr_i32 s2, s0, 16 +; GFX10-DL-NEXT: s_ashr_i32 s3, s1, 16 +; GFX10-DL-NEXT: s_sext_i32_i16 s0, s0 +; GFX10-DL-NEXT: s_sext_i32_i16 s1, s1 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v1, s1, s0, v0 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, @@ -2062,25 +2062,25 @@ ; GFX10-DL-LABEL: udot2_MultipleUses_mul1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 -; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 +; GFX10-DL-NEXT: s_mov_b32 s2, 0xffff ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_and_b32 s6, s2, s5 -; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_and_b32 s3, s0, s2 +; GFX10-DL-NEXT: s_and_b32 s2, s1, s2 +; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 16 +; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 16 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s1, s0, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 16 -; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 16 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s6, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s5, s6, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, @@ -2211,24 +2211,24 @@ ; GFX10-DL-LABEL: idot2_MultipleUses_mul1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_sext_i32_i16 s5, s2 -; GFX10-DL-NEXT: s_sext_i32_i16 s6, s3 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_sext_i32_i16 s2, s0 +; GFX10-DL-NEXT: s_sext_i32_i16 s3, s1 +; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 16 +; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 16 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s6, s5, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s1, s0, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s3, s2, v0 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, @@ -2364,25 +2364,25 @@ ; GFX10-DL-LABEL: udot2_MultipleUses_mul2: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_lshr_b32 s5, s2, 16 -; GFX10-DL-NEXT: s_lshr_b32 s6, s3, 16 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16 +; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16 +; GFX10-DL-NEXT: s_mov_b32 s6, 0xffff +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 +; GFX10-DL-NEXT: s_and_b32 s0, s0, s6 +; GFX10-DL-NEXT: s_and_b32 s1, s1, s6 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_mov_b32 s4, 0xffff -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0 -; GFX10-DL-NEXT: s_and_b32 s2, s2, s4 -; GFX10-DL-NEXT: s_and_b32 s3, s3, s4 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, @@ -2513,24 +2513,24 @@ ; GFX10-DL-LABEL: idot2_MultipleUses_mul2: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_ashr_i32 s5, s2, 16 -; GFX10-DL-NEXT: s_ashr_i32 s6, s3, 16 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_ashr_i32 s2, s0, 16 +; GFX10-DL-NEXT: s_ashr_i32 s3, s1, 16 +; GFX10-DL-NEXT: s_sext_i32_i16 s0, s0 +; GFX10-DL-NEXT: s_sext_i32_i16 s1, s1 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s3, s2, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s1, s0, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_sext_i32_i16 s2, s2 -; GFX10-DL-NEXT: s_sext_i32_i16 s3, s3 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s5, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s3, s2, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <2 x i16> addrspace(1)* %src2, diff --git a/llvm/test/CodeGen/AMDGPU/idot4s.ll b/llvm/test/CodeGen/AMDGPU/idot4s.ll --- a/llvm/test/CodeGen/AMDGPU/idot4s.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4s.ll @@ -643,30 +643,30 @@ ; GFX10-DL-LABEL: idot4_multiuse_mul1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_sext_i32_i8 s5, s2 -; GFX10-DL-NEXT: s_sext_i32_i8 s6, s3 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_sext_i32_i8 s2, s0 +; GFX10-DL-NEXT: s_sext_i32_i8 s3, s1 +; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x80008 +; GFX10-DL-NEXT: s_bfe_i32 s7, s1, 0x80008 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s7, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x80010 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80010 +; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 24 +; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 24 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80008 -; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x80008 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s5, s6, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s7, v0 -; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80010 -; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x80010 -; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24 -; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 24 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s5, s6, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s7, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, @@ -853,14 +853,14 @@ ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v0, 8, s2 ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v1, 8, s3 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-DL-NEXT: s_sext_i32_i8 s5, s2 -; GFX10-DL-NEXT: s_sext_i32_i8 s6, s3 +; GFX10-DL-NEXT: s_sext_i32_i8 s4, s2 +; GFX10-DL-NEXT: s_sext_i32_i8 s5, s3 ; GFX10-DL-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 ; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80010 -; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s5, s6, v2 ; GFX10-DL-NEXT: s_bfe_i32 s5, s3, 0x80010 +; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24 ; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 24 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, v0, v1, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s5, v0 @@ -1052,25 +1052,25 @@ ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x80000 -; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80000 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 8, s0 -; GFX10-DL-NEXT: s_lshr_b32 s5, s1, 16 +; GFX10-DL-NEXT: s_bfe_i32 s0, s0, 0x80000 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80000 +; GFX10-DL-NEXT: v_and_b32_e32 v7, s0, v3 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 8, s1 ; GFX10-DL-NEXT: v_and_b32_e32 v6, s3, v3 -; GFX10-DL-NEXT: v_and_b32_e32 v7, s4, v3 -; GFX10-DL-NEXT: s_bfe_i32 s0, s2, 0x80000 -; GFX10-DL-NEXT: s_bfe_i32 s1, s5, 0x80000 -; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6 +; GFX10-DL-NEXT: s_lshr_b32 s0, s1, 16 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v8, 8, s2 ; GFX10-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v7 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 8, s2 -; GFX10-DL-NEXT: v_and_b32_e32 v8, s1, v3 -; GFX10-DL-NEXT: v_and_b32_e32 v3, s0, v3 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 8, s5 +; GFX10-DL-NEXT: s_bfe_i32 s1, s2, 0x80000 +; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x80000 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 8, s0 +; GFX10-DL-NEXT: v_and_b32_e32 v7, s2, v3 +; GFX10-DL-NEXT: v_and_b32_e32 v3, s1, v3 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 -; GFX10-DL-NEXT: v_lshl_or_b32 v3, v6, 16, v3 -; GFX10-DL-NEXT: v_lshl_or_b32 v5, v7, 16, v8 +; GFX10-DL-NEXT: v_lshl_or_b32 v5, v6, 16, v7 +; GFX10-DL-NEXT: v_lshl_or_b32 v3, v8, 16, v3 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v4, v2 diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll --- a/llvm/test/CodeGen/AMDGPU/idot4u.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll @@ -623,11 +623,11 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_and_b32 s3, s2, s1 ; GFX10-DL-NEXT: s_and_b32 s1, s0, s1 -; GFX10-DL-NEXT: s_bfe_u32 s2, s2, 0x80008 ; GFX10-DL-NEXT: s_bfe_u32 s0, s0, 0x80008 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s3, v2 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s2, v2 +; GFX10-DL-NEXT: s_bfe_u32 s1, s2, 0x80008 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, @@ -946,6 +946,7 @@ ; GFX10-DL-LABEL: udot4_CommutationAccrossMADs: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX10-DL-NEXT: s_movk_i32 s4, 0xff ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2 @@ -955,20 +956,19 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 -; GFX10-DL-NEXT: s_movk_i32 s2, 0xff ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x80008 -; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x80008 -; GFX10-DL-NEXT: s_and_b32 s5, s0, s2 -; GFX10-DL-NEXT: s_and_b32 s2, s1, s2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s3, v2 -; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x80010 -; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x80010 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2 +; GFX10-DL-NEXT: s_and_b32 s2, s0, s4 +; GFX10-DL-NEXT: s_and_b32 s3, s1, s4 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s5, v2 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s3, v2 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v2 ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm @@ -1140,31 +1140,31 @@ ; GFX10-DL-LABEL: udot4_multiuse_mul1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 -; GFX10-DL-NEXT: s_movk_i32 s5, 0xff +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 +; GFX10-DL-NEXT: s_movk_i32 s2, 0xff ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_and_b32 s6, s2, s5 -; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_and_b32 s3, s0, s2 +; GFX10-DL-NEXT: s_and_b32 s2, s1, s2 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x80008 +; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x80008 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s7, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010 +; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24 +; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v0 ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80008 -; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80008 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s7, v0 -; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80010 -; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80010 -; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24 -; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s7, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, @@ -1348,32 +1348,32 @@ ; GFX10-DL-LABEL: udot4_multiuse_add1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX10-DL-NEXT: s_movk_i32 s7, 0xff ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 -; GFX10-DL-NEXT: s_movk_i32 s5, 0xff +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_bfe_u32 s6, s2, 0x80008 -; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80008 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_and_b32 s8, s2, s5 -; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s7, v0 -; GFX10-DL-NEXT: s_bfe_u32 s6, s2, 0x80010 -; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80010 -; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24 -; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s5, v0 -; GFX10-DL-NEXT: v_add_nc_u32_e32 v0, s4, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0 +; GFX10-DL-NEXT: s_and_b32 s2, s0, s7 +; GFX10-DL-NEXT: s_and_b32 s3, s1, s7 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v0 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010 +; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24 +; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24 ; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v1 +; GFX10-DL-NEXT: v_add_nc_u32_e32 v0, s6, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s0, s1, v1 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, @@ -1560,15 +1560,15 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008 -; GFX10-DL-NEXT: s_sext_i32_i8 s4, s0 -; GFX10-DL-NEXT: s_sext_i32_i8 s5, s1 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_sext_i32_i8 s2, s0 +; GFX10-DL-NEXT: s_sext_i32_i8 s3, s1 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off @@ -1754,20 +1754,20 @@ ; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 ; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 -; GFX10-DL-NEXT: s_movk_i32 s5, 0xff -; GFX10-DL-NEXT: s_mov_b32 s6, 0xffff +; GFX10-DL-NEXT: s_movk_i32 s6, 0xff +; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2 ; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3 -; GFX10-DL-NEXT: s_and_b32 s7, s2, s5 ; GFX10-DL-NEXT: v_mov_b32_e32 v2, s4 -; GFX10-DL-NEXT: s_and_b32 s5, s3, s5 -; GFX10-DL-NEXT: v_and_b32_sdwa v0, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 -; GFX10-DL-NEXT: v_and_b32_sdwa v1, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 +; GFX10-DL-NEXT: s_and_b32 s4, s2, s6 +; GFX10-DL-NEXT: s_and_b32 s6, s3, s6 +; GFX10-DL-NEXT: v_and_b32_sdwa v0, s5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 +; GFX10-DL-NEXT: v_and_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s6, v2 ; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80010 -; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s7, s5, v2 ; GFX10-DL-NEXT: s_bfe_u32 s5, s3, 0x80010 +; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24 ; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v1, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s5, v0 @@ -1956,14 +1956,14 @@ ; GFX10-DL-NEXT: v_and_b32_sdwa v7, v3, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v5, 8, s1 ; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 -; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16 -; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16 +; GFX10-DL-NEXT: s_lshr_b32 s2, s1, 16 +; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 16 ; GFX10-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v7 -; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24 -; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24 -; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 -; GFX10-DL-NEXT: v_and_b32_sdwa v3, v3, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6 +; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX10-DL-NEXT: v_and_b32_sdwa v3, v3, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 ; GFX10-DL-NEXT: v_lshl_or_b32 v5, s1, 16, v6 ; GFX10-DL-NEXT: v_lshl_or_b32 v3, s0, 16, v3 @@ -2176,15 +2176,15 @@ ; GFX10-DL-NEXT: v_lshrrev_b16_e64 v4, 8, s1 ; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 24 ; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 24 -; GFX10-DL-NEXT: s_lshr_b32 s4, s0, 16 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s2, s3 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, v3, v4 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, s0, s1 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s2, s3 -; GFX10-DL-NEXT: s_lshr_b32 s0, s1, 16 +; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 16 +; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 16 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v3 ; GFX10-DL-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 8, v5 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s4, s0 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s0, s1 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xffff, v3 ; GFX10-DL-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4 diff --git a/llvm/test/CodeGen/AMDGPU/idot8s.ll b/llvm/test/CodeGen/AMDGPU/idot8s.ll --- a/llvm/test/CodeGen/AMDGPU/idot8s.ll +++ b/llvm/test/CodeGen/AMDGPU/idot8s.ll @@ -487,33 +487,33 @@ ; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 12 ; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40000 ; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40000 -; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x40004 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s2 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s3 +; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x40004 ; GFX10-DL-NEXT: s_bfe_i32 s7, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s8, s1, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s2, s1, 0x40004 +; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s7, s8 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3 -; GFX10-DL-NEXT: s_mov_b32 s3, 0xffff ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4 -; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s7, s8 -; GFX10-DL-NEXT: v_and_b32_e32 v3, s3, v3 -; GFX10-DL-NEXT: v_and_b32_e32 v4, s3, v4 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 -; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40014 -; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40014 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s6, s2, v2 -; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010 +; GFX10-DL-NEXT: s_mov_b32 s2, 0xffff +; GFX10-DL-NEXT: v_and_b32_e32 v3, s2, v3 +; GFX10-DL-NEXT: v_and_b32_e32 v4, s2, v4 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 28 ; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 28 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v2 ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off @@ -831,33 +831,33 @@ ; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 12 ; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40000 ; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40000 -; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x40004 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s2 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s3 +; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x40004 ; GFX10-DL-NEXT: s_bfe_i32 s7, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s8, s1, 0x40008 ; GFX10-DL-NEXT: s_bfe_i32 s2, s1, 0x40004 +; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s7, s8 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3 -; GFX10-DL-NEXT: s_movk_i32 s3, 0xff ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4 -; GFX10-DL-NEXT: v_mul_i32_i24_e64 v5, s7, s8 -; GFX10-DL-NEXT: v_and_b32_e32 v3, s3, v3 -; GFX10-DL-NEXT: v_and_b32_e32 v4, s3, v4 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40010 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 -; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x40014 -; GFX10-DL-NEXT: s_bfe_i32 s5, s1, 0x40014 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s6, s2, v2 -; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010 +; GFX10-DL-NEXT: s_movk_i32 s2, 0xff +; GFX10-DL-NEXT: v_and_b32_e32 v3, s2, v3 +; GFX10-DL-NEXT: v_and_b32_e32 v4, s2, v4 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 28 ; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 28 -; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v2 ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off @@ -1132,43 +1132,43 @@ ; GFX10-DL-LABEL: idot8_multiuses_mul1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_bfe_i32 s5, s2, 0x40000 -; GFX10-DL-NEXT: s_bfe_i32 s6, s3, 0x40000 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x40004 -; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x40004 -; GFX10-DL-NEXT: v_mad_i32_i24 v0, s5, s6, v0 -; GFX10-DL-NEXT: v_mad_i32_i24 v1, s5, s6, v0 -; GFX10-DL-NEXT: s_bfe_i32 s5, s2, 0x40008 -; GFX10-DL-NEXT: s_bfe_i32 s6, s3, 0x40008 -; GFX10-DL-NEXT: v_mad_i32_i24 v1, s4, s7, v1 -; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x4000c -; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x4000c -; GFX10-DL-NEXT: v_mad_i32_i24 v1, s5, s6, v1 -; GFX10-DL-NEXT: s_bfe_i32 s5, s2, 0x40010 -; GFX10-DL-NEXT: s_bfe_i32 s6, s3, 0x40010 -; GFX10-DL-NEXT: v_mad_i32_i24 v1, s4, s7, v1 -; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x40014 -; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x40014 -; GFX10-DL-NEXT: v_mad_i32_i24 v1, s5, s6, v1 -; GFX10-DL-NEXT: s_bfe_i32 s5, s2, 0x40018 -; GFX10-DL-NEXT: s_bfe_i32 s6, s3, 0x40018 -; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 28 -; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 28 -; GFX10-DL-NEXT: v_mad_i32_i24 v1, s4, s7, v1 -; GFX10-DL-NEXT: v_mad_i32_i24 v1, s5, s6, v1 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40000 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40000 +; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0 +; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v0 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40004 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40004 +; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40008 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40008 ; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x4000c +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x4000c +; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40010 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40010 +; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1 +; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x40018 +; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x40018 +; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 28 +; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 28 +; GFX10-DL-NEXT: v_mad_i32_i24 v1, s2, s3, v1 +; GFX10-DL-NEXT: v_mad_i32_i24 v1, s0, s1, v1 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v0, v1 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, @@ -1708,49 +1708,49 @@ ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_and_b32 s4, s0, 15 -; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40004 -; GFX10-DL-NEXT: s_and_b32 s6, s1, 15 -; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40004 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 28 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX10-DL-NEXT: s_bfe_u32 s8, s0, 0x40010 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s6, s6, s7 -; GFX10-DL-NEXT: s_bfe_u32 s9, s0, 0x40014 -; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40008 -; GFX10-DL-NEXT: v_pk_lshlrev_b16 v3, 12, s4 op_sel_hi:[0,1] -; GFX10-DL-NEXT: s_bfe_u32 s0, s0, 0x4000c -; GFX10-DL-NEXT: v_pk_lshlrev_b16 v4, 12, s6 op_sel_hi:[0,1] -; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40008 -; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x4000c +; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40010 +; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s7, s0, 0x4000c +; GFX10-DL-NEXT: s_and_b32 s8, s0, 15 +; GFX10-DL-NEXT: s_bfe_u32 s0, s0, 0x40004 +; GFX10-DL-NEXT: s_and_b32 s9, s1, 15 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s8, s0 +; GFX10-DL-NEXT: s_bfe_u32 s8, s1, 0x40004 +; GFX10-DL-NEXT: v_pk_lshlrev_b16 v3, 12, s0 op_sel_hi:[0,1] +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s9, s8 +; GFX10-DL-NEXT: s_bfe_u32 s9, s1, 0x4000c +; GFX10-DL-NEXT: v_pk_lshlrev_b16 v4, 12, s0 op_sel_hi:[0,1] +; GFX10-DL-NEXT: s_bfe_u32 s0, s1, 0x40008 ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v3, 12, v3 op_sel_hi:[0,1] -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s5, s0 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s6, s6, s7 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s9 ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v4 op_sel_hi:[0,1] -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40010 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s7, s4 -; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40018 -; GFX10-DL-NEXT: v_pk_lshlrev_b16 v5, 12, s0 op_sel_hi:[0,1] +; GFX10-DL-NEXT: v_pk_lshlrev_b16 v5, 12, s6 op_sel_hi:[0,1] +; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s0 op_sel_hi:[0,1] +; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s0, s1, 0x40014 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v4 -; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s4 op_sel_hi:[0,1] -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s8, s9 ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v5 op_sel_hi:[0,1] -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s5, s0 -; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v6 op_sel_hi:[0,1] +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s5 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s6, s0 ; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s4 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_pk_lshlrev_b16 v7, 12, s0 op_sel_hi:[0,1] -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s2, s3 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s1, s6, s1 +; GFX10-DL-NEXT: s_bfe_u32 s8, s1, 0x40018 +; GFX10-DL-NEXT: s_lshr_b32 s0, s1, 28 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s1, s2, s3 ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v7 op_sel_hi:[0,1] -; GFX10-DL-NEXT: v_pk_lshlrev_b16 v7, 12, s1 op_sel_hi:[0,1] +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s8, s0 +; GFX10-DL-NEXT: v_pk_lshlrev_b16 v7, 12, s0 op_sel_hi:[0,1] ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v3, 12, v6 op_sel_hi:[0,1] -; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s0 op_sel_hi:[0,1] +; GFX10-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s1 op_sel_hi:[0,1] ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5 ; GFX10-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v7 op_sel_hi:[0,1] @@ -2141,38 +2141,36 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_lshr_b32 s7, s0, 4 ; GFX10-DL-NEXT: s_lshr_b32 s14, s1, 4 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s7 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s14 ; GFX10-DL-NEXT: s_lshr_b32 s8, s0, 12 ; GFX10-DL-NEXT: s_lshr_b32 s15, s1, 12 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s0 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s7 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s14 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s1 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v14, 12, s15 -; GFX10-DL-NEXT: s_lshr_b32 s9, s0, 8 -; GFX10-DL-NEXT: s_lshr_b32 s16, s1, 8 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s8 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 12, v7 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v12 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v13, 12, v13 +; GFX10-DL-NEXT: s_lshr_b32 s9, s0, 8 +; GFX10-DL-NEXT: s_lshr_b32 s16, s1, 8 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s9 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s16 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v3, 12, v3 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 12, v4 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s16 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, v7, v12 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v19, 12, v6 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, v7, v13 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v14, 12, v14 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 12, v5 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v12 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, v3, v4 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 8, v7 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, v19, v14 ; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 20 ; GFX10-DL-NEXT: s_lshr_b32 s4, s0, 16 ; GFX10-DL-NEXT: s_lshr_b32 s5, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s6, s0, 24 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, v3, v4 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, v19, v14 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v6, 8, v7 ; GFX10-DL-NEXT: s_lshr_b32 s10, s1, 20 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v13 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 12, v5 -; GFX10-DL-NEXT: s_lshr_b32 s11, s1, 16 ; GFX10-DL-NEXT: v_or_b32_sdwa v3, v3, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX10-DL-NEXT: s_lshr_b32 s12, s1, 28 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s6 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s5 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s4 @@ -2180,8 +2178,9 @@ ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s10 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v5, v12 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 8, v4 +; GFX10-DL-NEXT: s_lshr_b32 s11, s1, 16 +; GFX10-DL-NEXT: s_lshr_b32 s12, s1, 28 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s11 -; GFX10-DL-NEXT: s_lshr_b32 s13, s1, 24 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 12, v8 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v8, 12, v9 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v9, 12, v10 @@ -2190,13 +2189,14 @@ ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s12 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 12, v11 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v10, 12, v13 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s13 +; GFX10-DL-NEXT: s_lshr_b32 s13, s1, 24 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 12, v7 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s13 ; GFX10-DL-NEXT: v_ashrrev_i16_e64 v11, 12, v16 -; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, v5, v10 -; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v15 +; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v10, v9, v7 +; GFX10-DL-NEXT: v_ashrrev_i16_e64 v12, 12, v15 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v8, v8, v11 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 8, v4 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/idot8u.ll b/llvm/test/CodeGen/AMDGPU/idot8u.ll --- a/llvm/test/CodeGen/AMDGPU/idot8u.ll +++ b/llvm/test/CodeGen/AMDGPU/idot8u.ll @@ -459,28 +459,28 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40008 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x4000c -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c ; GFX10-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x4000c +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x4000c +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: global_store_short v[0:1], v2, off @@ -762,28 +762,28 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40008 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x4000c -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c ; GFX10-DL-NEXT: v_and_b32_e32 v2, 0xff, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x4000c +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x4000c +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off @@ -1075,30 +1075,30 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 -; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x4000c -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s6, v2 -; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s4 +; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s5 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s4, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 -; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3 +; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 @@ -1375,30 +1375,30 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40008 -; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x4000c +; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40008 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 -; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c -; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x4000c +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x4000c +; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s2, s3 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 -; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s7 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s6, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3 -; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 @@ -1656,43 +1656,43 @@ ; GFX10-DL-LABEL: udot8_multiuses_mul1: ; GFX10-DL: ; %bb.0: ; %entry ; GFX10-DL-NEXT: s_clause 0x1 -; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-DL-NEXT: ; implicit-def: $vcc_hi ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0 -; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0 +; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 +; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_and_b32 s5, s2, 15 -; GFX10-DL-NEXT: s_and_b32 s6, s3, 15 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 -; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s8, s2, 0x40008 -; GFX10-DL-NEXT: s_bfe_u32 s9, s3, 0x40008 -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s6, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s4, s7, v0 -; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x4000c -; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x4000c -; GFX10-DL-NEXT: v_mad_u32_u24 v0, s5, s6, v0 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s9, v1 -; GFX10-DL-NEXT: s_bfe_u32 s8, s2, 0x40010 -; GFX10-DL-NEXT: s_bfe_u32 s9, s3, 0x40010 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s4, s7, v1 -; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x40014 -; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x40014 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s9, v1 -; GFX10-DL-NEXT: s_bfe_u32 s8, s2, 0x40018 -; GFX10-DL-NEXT: s_bfe_u32 s9, s3, 0x40018 -; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 28 -; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 28 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s4, s7, v1 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s9, v1 -; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v1 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6 +; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 +; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40004 +; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40004 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v0 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40008 +; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x4000c +; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x4000c +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40010 +; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40010 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x40018 +; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40018 +; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 +; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1 +; GFX10-DL-NEXT: v_mad_u32_u24 v1, s0, s1, v1 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v0, v1 -; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, @@ -2209,33 +2209,33 @@ ; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40004 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 ; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x4000c -; GFX10-DL-NEXT: s_bfe_u32 s7, s0, 0x4000c ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s5 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40008 ; GFX10-DL-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40008 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, s2, s3 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s3, s5, s6 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s7 +; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s5 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s3 +; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x40014 +; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, s2, s4 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 -; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40014 -; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40010 -; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40014 -; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, s4, s3 -; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x40018 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s5 -; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s6, s7 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40018 +; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40010 +; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s2, s2, s3 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s4, s4, s5 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s3, s0 -; GFX10-DL-NEXT: s_pack_ll_b32_b16 s1, s5, s1 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s1, s3, s1 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, s2, s4 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 +; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:BYTE_0 +; GFX10-DL-NEXT: s_pack_ll_b32_b16 s0, s2, s0 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, s0, s1 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 @@ -2567,54 +2567,54 @@ ; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0 ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004 -; GFX10-DL-NEXT: s_and_b32 s4, s0, 15 -; GFX10-DL-NEXT: s_and_b32 s6, s1, 15 -; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x4000c -; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x4000c -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, s2, s3 -; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, s4, s6 -; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40008 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s5, s7 +; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x40004 +; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 +; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, s3, s5 +; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 +; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x4000c +; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, s2, s3 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s6, s5 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v3 -; GFX10-DL-NEXT: s_mov_b32 s4, 0xffff -; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40014 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, s2, s3 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 8, v5 +; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s2, s1, 0x40008 +; GFX10-DL-NEXT: s_mov_b32 s3, 0xffff +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, s4, s2 ; GFX10-DL-NEXT: v_or_b32_e32 v3, v4, v3 -; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x40014 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 8, v5 +; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40014 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 -; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40018 +; GFX10-DL-NEXT: v_and_b32_e32 v3, s3, v3 ; GFX10-DL-NEXT: v_or_b32_sdwa v4, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX10-DL-NEXT: v_and_b32_e32 v3, s4, v3 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s4, s6 +; GFX10-DL-NEXT: s_bfe_u32 s5, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x40010 -; GFX10-DL-NEXT: s_lshr_b32 s8, s1, 28 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s3, s6 ; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4 -; GFX10-DL-NEXT: s_bfe_u32 s1, s1, 0x40018 +; GFX10-DL-NEXT: s_lshr_b32 s4, s1, 28 ; GFX10-DL-NEXT: v_mul_lo_u16_e64 v6, s2, s7 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, s0, s8 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v7, s0, s4 +; GFX10-DL-NEXT: v_lshlrev_b16_e64 v5, 8, v5 ; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v4 +; GFX10-DL-NEXT: s_bfe_u32 s0, s1, 0x40018 +; GFX10-DL-NEXT: v_mul_lo_u16_e64 v10, s5, s0 +; GFX10-DL-NEXT: v_or_b32_e32 v5, v6, v5 ; GFX10-DL-NEXT: v_lshlrev_b16_e64 v7, 8, v7 +; GFX10-DL-NEXT: v_and_b32_e32 v5, s3, v5 ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v3, v2 -; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v5 -; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s5, s1 +; GFX10-DL-NEXT: v_or_b32_sdwa v3, v10, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v8 -; GFX10-DL-NEXT: v_or_b32_e32 v3, v6, v3 -; GFX10-DL-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX10-DL-NEXT: v_or_b32_e32 v3, v5, v3 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 -; GFX10-DL-NEXT: v_and_b32_e32 v3, s4, v3 -; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 -; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v5 -; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 -; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v4 -; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 -; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v3 +; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v5 +; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v4 +; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX10-DL-NEXT: v_add_nc_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 ; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off ; GFX10-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, @@ -2868,30 +2868,30 @@ ; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-DL-NEXT: s_and_b32 s2, s0, 15 ; GFX10-DL-NEXT: s_and_b32 s3, s1, 15 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40004 -; GFX10-DL-NEXT: s_bfe_u32 s6, s1, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x40008 +; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x4000c ; GFX10-DL-NEXT: s_waitcnt vmcnt(0) ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40004 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40004 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40008 ; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x4000c -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 -; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x4000c -; GFX10-DL-NEXT: s_bfe_u32 s5, s1, 0x40014 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s6, v2 -; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s4 +; GFX10-DL-NEXT: v_mul_u32_u24_e64 v3, s3, s5 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s4, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40010 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40010 -; GFX10-DL-NEXT: s_bfe_u32 s4, s0, 0x40014 -; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v3, 15, v3 +; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 ; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 +; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40014 +; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40014 +; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x40018 ; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x40018 ; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 28 ; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 28 -; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s5, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2 ; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2 ; GFX10-DL-NEXT: v_and_b32_e32 v2, 15, v2 diff --git a/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll b/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll --- a/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll +++ b/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll @@ -34,8 +34,8 @@ ; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, v1 -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_short v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off @@ -97,8 +97,8 @@ ; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, v1 -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_short v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off @@ -160,8 +160,8 @@ ; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, v1 -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off @@ -223,8 +223,8 @@ ; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, v1 -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off @@ -286,8 +286,8 @@ ; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, v1 -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off @@ -363,8 +363,8 @@ ; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v3, v1 -; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[1:2], off ; GFX10-NEXT: global_store_dword v[0:1], v3, off diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll @@ -593,9 +593,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 0) call void asm sideeffect "", ""() @@ -614,9 +614,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x1 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 1) call void asm sideeffect "", ""() @@ -635,9 +635,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x2 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 2) call void asm sideeffect "", ""() @@ -656,9 +656,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x4 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 4) call void asm sideeffect "", ""() @@ -677,9 +677,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x8 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 8) call void asm sideeffect "", ""() @@ -698,9 +698,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 1 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 1 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 16) call void asm sideeffect "", ""() @@ -719,9 +719,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 2 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 2 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 32) call void asm sideeffect "", ""() @@ -740,9 +740,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 4 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 4 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 64) call void asm sideeffect "", ""() @@ -761,9 +761,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x0 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 8 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 8 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 128) call void asm sideeffect "", ""() @@ -782,9 +782,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0xf ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 0 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 15) call void asm sideeffect "", ""() @@ -803,9 +803,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0xf ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 15 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 15 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 255) call void asm sideeffect "", ""() @@ -825,9 +825,9 @@ ; GFX10: ; %bb.0: ; GFX10-NEXT: s_round_mode 0x5 ; GFX10-NEXT: ; implicit-def: $vcc_hi +; GFX10-NEXT: s_denorm_mode 5 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_denorm_mode 5 ; GFX10-NEXT: s_endpgm call void @llvm.amdgcn.s.setreg(i32 14337, i32 597) call void asm sideeffect "", ""() diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll @@ -101,8 +101,8 @@ ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} -; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 +; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} ; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048 diff --git a/llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir b/llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir --- a/llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir +++ b/llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir @@ -25,8 +25,8 @@ ; GCN: $vcc_hi = IMPLICIT_DEF ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store 4, addrspace 3) ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec - ; GCN: $m0 = S_MOV_B32 0 ; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]] + ; GCN: $m0 = S_MOV_B32 0 ; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec { ; GCN: DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4) ; GCN: S_WAITCNT 0 diff --git a/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll b/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll --- a/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll +++ b/llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll @@ -15,7 +15,7 @@ define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <4 x i32> addrspace(1)* %input, <4 x float> addrspace(1)* %output, i32 %i) { ; GCN-LABEL: kernel_background_evaluate: ; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dword s6, s[0:1], 0x24 +; GCN-NEXT: s_load_dword s0, s[0:1], 0x24 ; GCN-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GCN-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GCN-NEXT: s_mov_b32 s38, -1 @@ -26,8 +26,6 @@ ; GCN-NEXT: v_mov_b32_e32 v2, 0x4000 ; GCN-NEXT: v_mov_b32_e32 v3, 0 ; GCN-NEXT: v_mov_b32_e32 v4, 0x400000 -; GCN-NEXT: s_mov_b64 s[0:1], s[36:37] -; GCN-NEXT: s_mov_b64 s[2:3], s[38:39] ; GCN-NEXT: s_mov_b32 s32, 0xc0000 ; GCN-NEXT: v_add_nc_u32_e64 v40, 4, 0x4000 ; GCN-NEXT: ; implicit-def: $vcc_hi @@ -35,7 +33,9 @@ ; GCN-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+4 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: s_mov_b64 s[0:1], s[36:37] +; GCN-NEXT: s_mov_b64 s[2:3], s[38:39] ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll --- a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll +++ b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll @@ -136,10 +136,10 @@ ; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+4 ; GFX10-NEXT: v_mov_b32_e32 v40, v16 -; GFX10-NEXT: v_mov_b32_e32 v41, v15 +; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: image_gather4_c_b_cl v[0:3], v[12:19], s[36:43], s[44:47] dmask:0x1 +; GFX10-NEXT: v_mov_b32_e32 v41, v15 ; GFX10-NEXT: v_mov_b32_e32 v42, v14 -; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v43, v13 ; GFX10-NEXT: v_mov_b32_e32 v44, v12 ; GFX10-NEXT: ; implicit-def: $vcc_hi diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -235,9 +235,9 @@ ; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc ; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo ; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec -; GCN: global_store_dword ; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo ; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec +; GCN: global_store_dword ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]] ; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]] ; GCN: BB{{.*}}: ; %Flow