diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -181,9 +181,6 @@ int64_t &Offset1, int64_t &Offset2) const override; - unsigned getOperandSizeInBytes(const MachineInstr &LdSt, - const MachineOperand *MOp) const; - bool getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl &BaseOps, int64_t &Offset, diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -264,17 +264,6 @@ } } -unsigned SIInstrInfo::getOperandSizeInBytes(const MachineInstr &LdSt, - const MachineOperand *MOp) const { - assert(MOp && "Unexpected null machine operand!"); - const MachineRegisterInfo &MRI = LdSt.getParent()->getParent()->getRegInfo(); - const Register Reg = MOp->getReg(); - const TargetRegisterClass *DstRC = Register::isVirtualRegister(Reg) - ? MRI.getRegClass(Reg) - : RI.getPhysRegClass(Reg); - return (RI.getRegSizeInBits(*DstRC) / 8); -} - bool SIInstrInfo::getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, @@ -284,7 +273,8 @@ unsigned Opc = LdSt.getOpcode(); OffsetIsScalable = false; - const MachineOperand *BaseOp, *OffsetOp, *MOp; + const MachineOperand *BaseOp, *OffsetOp; + int DataOpIdx; if (isDS(LdSt)) { BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); @@ -299,10 +289,10 @@ BaseOps.push_back(BaseOp); Offset = OffsetOp->getImm(); // Get appropriate operand, and compute width accordingly. - MOp = getNamedOperand(LdSt, AMDGPU::OpName::vdst); - if (!MOp) - MOp = getNamedOperand(LdSt, AMDGPU::OpName::data0); - Width = getOperandSizeInBytes(LdSt, MOp); + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); + if (DataOpIdx == -1) + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0); + Width = getOpSize(LdSt, DataOpIdx); } else { // The 2 offset instructions use offset0 and offset1 instead. We can treat // these as a load with a single offset if the 2 offsets are consecutive. @@ -335,14 +325,14 @@ BaseOps.push_back(BaseOp); Offset = EltSize * Offset0; // Get appropriate operand(s), and compute width accordingly. - MOp = getNamedOperand(LdSt, AMDGPU::OpName::vdst); - if (!MOp) { - MOp = getNamedOperand(LdSt, AMDGPU::OpName::data0); - Width = getOperandSizeInBytes(LdSt, MOp); - MOp = getNamedOperand(LdSt, AMDGPU::OpName::data1); - Width += getOperandSizeInBytes(LdSt, MOp); + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); + if (DataOpIdx == -1) { + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0); + Width = getOpSize(LdSt, DataOpIdx); + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); + Width += getOpSize(LdSt, DataOpIdx); } else { - Width = getOperandSizeInBytes(LdSt, MOp); + Width = getOpSize(LdSt, DataOpIdx); } } return true; @@ -368,33 +358,27 @@ BaseOps.push_back(RSrc); BaseOps.push_back(SOffset); Offset = OffsetImm->getImm(); - // Get appropriate operand, and compute width accordingly. - MOp = getNamedOperand(LdSt, AMDGPU::OpName::vdst); - if (!MOp) - MOp = getNamedOperand(LdSt, AMDGPU::OpName::vdata); - Width = getOperandSizeInBytes(LdSt, MOp); - return true; - } - - BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); - if (!BaseOp) // e.g. BUFFER_WBINVL1_VOL - return false; - BaseOps.push_back(BaseOp); - - BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); - if (BaseOp) + } else { + BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); + if (!BaseOp) // e.g. BUFFER_WBINVL1_VOL + return false; BaseOps.push_back(BaseOp); - const MachineOperand *OffsetImm = - getNamedOperand(LdSt, AMDGPU::OpName::offset); - Offset = OffsetImm->getImm(); - if (SOffset) // soffset can be an inline immediate. - Offset += SOffset->getImm(); + BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); + if (BaseOp) + BaseOps.push_back(BaseOp); + + const MachineOperand *OffsetImm = + getNamedOperand(LdSt, AMDGPU::OpName::offset); + Offset = OffsetImm->getImm(); + if (SOffset) // soffset can be an inline immediate. + Offset += SOffset->getImm(); + } // Get appropriate operand, and compute width accordingly. - MOp = getNamedOperand(LdSt, AMDGPU::OpName::vdst); - if (!MOp) - MOp = getNamedOperand(LdSt, AMDGPU::OpName::vdata); - Width = getOperandSizeInBytes(LdSt, MOp); + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); + if (DataOpIdx == -1) + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata); + Width = getOpSize(LdSt, DataOpIdx); return true; } @@ -406,8 +390,8 @@ OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset); Offset = OffsetOp ? OffsetOp->getImm() : 0; // Get appropriate operand, and compute width accordingly. - MOp = getNamedOperand(LdSt, AMDGPU::OpName::sdst); - Width = getOperandSizeInBytes(LdSt, MOp); + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst); + Width = getOpSize(LdSt, DataOpIdx); return true; } @@ -421,10 +405,10 @@ BaseOps.push_back(BaseOp); Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm(); // Get appropriate operand, and compute width accordingly. - MOp = getNamedOperand(LdSt, AMDGPU::OpName::vdst); - if (!MOp) - MOp = getNamedOperand(LdSt, AMDGPU::OpName::vdata); - Width = getOperandSizeInBytes(LdSt, MOp); + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); + if (DataOpIdx == -1) + DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata); + Width = getOpSize(LdSt, DataOpIdx); return true; }