diff --git a/llvm/lib/Target/VE/CMakeLists.txt b/llvm/lib/Target/VE/CMakeLists.txt --- a/llvm/lib/Target/VE/CMakeLists.txt +++ b/llvm/lib/Target/VE/CMakeLists.txt @@ -2,6 +2,7 @@ tablegen(LLVM VEGenRegisterInfo.inc -gen-register-info) tablegen(LLVM VEGenInstrInfo.inc -gen-instr-info) +tablegen(LLVM VEGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM VEGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM VEGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM VEGenAsmMatcher.inc -gen-asm-matcher) @@ -24,5 +25,6 @@ ) add_subdirectory(AsmParser) +add_subdirectory(Disassembler) add_subdirectory(TargetInfo) add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/VE/Disassembler/CMakeLists.txt b/llvm/lib/Target/VE/Disassembler/CMakeLists.txt new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/VE/Disassembler/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_component_library(LLVMVEDisassembler + VEDisassembler.cpp + ) diff --git a/llvm/lib/Target/VE/LLVMBuild.txt b/llvm/lib/Target/VE/Disassembler/LLVMBuild.txt copy from llvm/lib/Target/VE/LLVMBuild.txt copy to llvm/lib/Target/VE/Disassembler/LLVMBuild.txt --- a/llvm/lib/Target/VE/LLVMBuild.txt +++ b/llvm/lib/Target/VE/Disassembler/LLVMBuild.txt @@ -1,4 +1,4 @@ -;===- ./lib/Target/VE/LLVMBuild.txt ----------------------------*- Conf -*--===; +;===- ./lib/Target/VE/Disassembler/LLVMBuild.txt ---------------*- Conf -*--===; ; ; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. ; See https://llvm.org/LICENSE.txt for license information. @@ -14,20 +14,9 @@ ; ;===------------------------------------------------------------------------===; -[common] -subdirectories = AsmParser MCTargetDesc TargetInfo - [component_0] -type = TargetGroup -name = VE -parent = Target -has_asmparser = 1 -has_asmprinter = 1 - -[component_1] type = Library -name = VECodeGen +name = VEDisassembler parent = VE -required_libraries = Analysis AsmPrinter CodeGen Core - MC SelectionDAG VEDesc VEInfo Support Target +required_libraries = MCDisassembler VEInfo Support add_to_library_groups = VE diff --git a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp @@ -0,0 +1,280 @@ +//===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file is part of the VE Disassembler. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/VEMCTargetDesc.h" +#include "TargetInfo/VETargetInfo.h" +#include "VE.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +#define DEBUG_TYPE "ve-disassembler" + +typedef MCDisassembler::DecodeStatus DecodeStatus; + +namespace { + +/// A disassembler class for VE. +class VEDisassembler : public MCDisassembler { +public: + VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) + : MCDisassembler(STI, Ctx) {} + virtual ~VEDisassembler() {} + + DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef Bytes, uint64_t Address, + raw_ostream &CStream) const override; +}; +} // namespace + +static MCDisassembler *createVEDisassembler(const Target &T, + const MCSubtargetInfo &STI, + MCContext &Ctx) { + return new VEDisassembler(STI, Ctx); +} + +extern "C" void LLVMInitializeVEDisassembler() { + // Register the disassembler. + TargetRegistry::RegisterMCDisassembler(getTheVETarget(), + createVEDisassembler); +} + +static const unsigned I32RegDecoderTable[] = { + VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, + VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, + VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, + VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, + VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34, + VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, + VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, + VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, + VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, + VE::SW63}; + +static const unsigned I64RegDecoderTable[] = { + VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, + VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, + VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, + VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, + VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, + VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, + VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, + VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, + VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, + VE::SX63}; + +static const unsigned F32RegDecoderTable[] = { + VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, + VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, + VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, + VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, + VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34, + VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, + VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, + VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, + VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, + VE::SF63}; + +static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 63) + return MCDisassembler::Fail; + unsigned Reg = I32RegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 63) + return MCDisassembler::Fail; + unsigned Reg = I64RegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 63) + return MCDisassembler::Fail; + unsigned Reg = F32RegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address, + const void *Decoder); + +#include "VEGenDisassemblerTables.inc" + +/// Read four bytes from the ArrayRef and return 32 bit word. +static DecodeStatus readInstruction64(ArrayRef Bytes, uint64_t Address, + uint64_t &Size, uint64_t &Insn, + bool IsLittleEndian) { + // We want to read exactly 8 Bytes of data. + if (Bytes.size() < 8) { + Size = 0; + return MCDisassembler::Fail; + } + + Insn = IsLittleEndian + ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | + ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) | + ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) | + ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56) + : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) | + ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) | + ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) | + ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56); + + return MCDisassembler::Success; +} + +DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef Bytes, + uint64_t Address, + raw_ostream &CStream) const { + uint64_t Insn; + bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); + DecodeStatus Result = + readInstruction64(Bytes, Address, Size, Insn, isLittleEndian); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + + // Calling the auto-generated decoder function. + + Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI); + + if (Result != MCDisassembler::Fail) { + Size = 8; + return Result; + } + + return MCDisassembler::Fail; +} + +typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address, + const void *Decoder) { + unsigned sy = fieldFromInstruction(insn, 40, 7); + bool cy = fieldFromInstruction(insn, 47, 1); + unsigned sz = fieldFromInstruction(insn, 32, 7); + bool cz = fieldFromInstruction(insn, 39, 1); + uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); + DecodeStatus status; + + // Decode sz. + if (cz) { + status = DecodeI64RegisterClass(MI, sz, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } else { + MI.addOperand(MCOperand::createImm(0)); + } + + // Decode sy. + if (cy) { + status = DecodeI64RegisterClass(MI, sy, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } else { + MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); + } + + // Decode simm32. + MI.addOperand(MCOperand::createImm(simm32)); + + return MCDisassembler::Success; +} + +static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address, + const void *Decoder, bool isLoad, + DecodeFunc DecodeSX) { + unsigned sx = fieldFromInstruction(insn, 48, 7); + + DecodeStatus status; + if (isLoad) { + status = DecodeSX(MI, sx, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } + + status = DecodeASX(MI, insn, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + if (!isLoad) { + status = DecodeSX(MI, sx, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } + return MCDisassembler::Success; +} + +static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, + const void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); +} + +static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, + uint64_t Address, const void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); +} + +static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, + const void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); +} + +static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, + uint64_t Address, const void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); +} + +static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, + const void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); +} + +static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, + uint64_t Address, const void *Decoder) { + return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); +} + +static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, + const void *Decoder) { + uint64_t tgt = SignExtend64<7>(insn); + MI.addOperand(MCOperand::createImm(tgt)); + return MCDisassembler::Success; +} diff --git a/llvm/lib/Target/VE/LLVMBuild.txt b/llvm/lib/Target/VE/LLVMBuild.txt --- a/llvm/lib/Target/VE/LLVMBuild.txt +++ b/llvm/lib/Target/VE/LLVMBuild.txt @@ -15,7 +15,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser MCTargetDesc TargetInfo +subdirectories = AsmParser Disassembler MCTargetDesc TargetInfo [component_0] type = TargetGroup @@ -23,6 +23,7 @@ parent = Target has_asmparser = 1 has_asmprinter = 1 +has_disassembler = 1 [component_1] type = Library diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -661,14 +661,13 @@ } multiclass BCm opc, RegisterClass RC, Operand immOp> { - let DecoderMethod = "DecodeBranchCondition" in defm r : BCtgm; - let DecoderMethod = "DecodeBranchCondition", cy = 0 in + let cy = 0 in defm i : BCtgm; - let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0, + let cy = 0, sy = 0, cf = 15 /* AT */, isBarrier = 1 in defm a : BCtgm; - let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0, + let cy = 0, sy = 0, cf = 0 /* AF */ in defm na : BCtgm; } @@ -793,15 +792,15 @@ defm LDLZX : LOADm<"ldl.zx", 0x03, I32, i32, load>; // Section 8.2.5 - LD2B -let DecoderMethod = "DecodeLoadI16" in +let DecoderMethod = "DecodeLoadI32" in defm LD2BSX : LOADm<"ld2b.sx", 0x04, I32, i32, sextloadi16>; -let cx = 1, DecoderMethod = "DecodeLoadI16" in +let cx = 1, DecoderMethod = "DecodeLoadI32" in defm LD2BZX : LOADm<"ld2b.zx", 0x04, I32, i32, zextloadi16>; // Section 8.2.6 - LD1B -let DecoderMethod = "DecodeLoadI8" in +let DecoderMethod = "DecodeLoadI32" in defm LD1BSX : LOADm<"ld1b.sx", 0x05, I32, i32, sextloadi8>; -let cx = 1, DecoderMethod = "DecodeLoadI8" in +let cx = 1, DecoderMethod = "DecodeLoadI32" in defm LD1BZX : LOADm<"ld1b.zx", 0x05, I32, i32, zextloadi8>; // Multiclass for store instructions. @@ -842,11 +841,11 @@ defm STL : STOREm<"stl", 0x13, I32, i32, store>; // Section 8.2.10 - ST2B -let DecoderMethod = "DecodeStoreI16" in +let DecoderMethod = "DecodeStoreI32" in defm ST2B : STOREm<"st2b", 0x14, I32, i32, truncstorei16>; // Section 8.2.11 - ST1B -let DecoderMethod = "DecodeStoreI8" in +let DecoderMethod = "DecodeStoreI32" in defm ST1B : STOREm<"st1b", 0x15, I32, i32, truncstorei8>; // Section 8.2.12 - DLDS @@ -1110,7 +1109,7 @@ defm BRCFS : BCRm<"br${cf}.s", "br.s", "braf.s", 0x18, F32, simm7fp>; // Section 8.8.5 - BSIC (Branch and Save IC) -let isCall = 1, hasSideEffects = 0, DecoderMethod = "DecodeCall" in +let isCall = 1, hasSideEffects = 0 in defm BSIC : RMm<"bsic", 0x08, I64>; // Call instruction is a special case of BSIC. diff --git a/llvm/test/MC/VE/LD.s b/llvm/test/MC/VE/LD.s --- a/llvm/test/MC/VE/LD.s +++ b/llvm/test/MC/VE/LD.s @@ -1,45 +1,48 @@ -# RUN: llvm-mc -triple ve-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple=ve --show-encoding < %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \ +# RUN: | FileCheck %s --check-prefixes=CHECK-INST -# CHECK: ld %s11, 8199 -# CHECK: encoding: [0x07,0x20,0x00,0x00,0x00,0x00,0x0b,0x01] +# CHECK-INST: ld %s11, 8199 +# CHECK-ENCODING: encoding: [0x07,0x20,0x00,0x00,0x00,0x00,0x0b,0x01] ld %s11, 8199 -# CHECK: ld %s11, 20(%s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x01] +# CHECK-INST: ld %s11, 20(%s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x01] ld %s11, 20(%s11) -# CHECK: ld %s11, -1(, %s11) -# CHECK: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x01] +# CHECK-INST: ld %s11, -1(, %s11) +# CHECK-ENCODING: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x01] ld %s11, -1(, %s11) -# CHECK: ld %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x01] +# CHECK-INST: ld %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x01] ld %s11, 20(%s10, %s11) -# CHECK: ldu %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x02] +# CHECK-INST: ldu %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x02] ldu %s11, 20(%s10, %s11) -# CHECK: ldl.sx %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x03] +# CHECK-INST: ldl.sx %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x03] ldl.sx %s11, 20(%s10, %s11) -# CHECK: ldl.zx %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x03] +# CHECK-INST: ldl.zx %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x03] ldl.zx %s11, 20(%s10, %s11) -# CHECK: ld2b.sx %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x04] +# CHECK-INST: ld2b.sx %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x04] ld2b.sx %s11, 20(%s10, %s11) -# CHECK: ld2b.zx %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x04] +# CHECK-INST: ld2b.zx %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x04] ld2b.zx %s11, 20(%s10, %s11) -# CHECK: ld1b.sx %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x05] +# CHECK-INST: ld1b.sx %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x05] ld1b.sx %s11, 20(%s10, %s11) -# CHECK: ld1b.zx %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x05] +# CHECK-INST: ld1b.zx %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x05] ld1b.zx %s11, 20(%s10, %s11) diff --git a/llvm/test/MC/VE/LEA.s b/llvm/test/MC/VE/LEA.s --- a/llvm/test/MC/VE/LEA.s +++ b/llvm/test/MC/VE/LEA.s @@ -1,29 +1,36 @@ -# RUN: llvm-mc -triple ve-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple=ve --show-encoding < %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \ +# RUN: | FileCheck %s --check-prefixes=CHECK-INST -# CHECK: lea %s11, 23 -# CHECK: encoding: [0x17,0x00,0x00,0x00,0x00,0x00,0x0b,0x06] +# CHECK-INST: lea %s11, 23 +# CHECK-ENCODING: encoding: [0x17,0x00,0x00,0x00,0x00,0x00,0x0b,0x06] lea %s11, 23 -# CHECK: lea %s63, 324(, %s11) -# CHECK: encoding: [0x44,0x01,0x00,0x00,0x8b,0x00,0x3f,0x06] +# CHECK-INST: lea %s63, 324(, %s11) +# CHECK-ENCODING: encoding: [0x44,0x01,0x00,0x00,0x8b,0x00,0x3f,0x06] lea %s63, 324(,%s11) -# CHECK: lea %s11, 324(%s10) -# CHECK: encoding: [0x44,0x01,0x00,0x00,0x00,0x8a,0x0b,0x06] +# CHECK-INST: lea %s11, 324(%s10) +# CHECK-ENCODING: encoding: [0x44,0x01,0x00,0x00,0x00,0x8a,0x0b,0x06] lea %s11, 324(%s10 ) -# CHECK: lea %s11, 324(%s13, %s11) -# CHECK: encoding: [0x44,0x01,0x00,0x00,0x8b,0x8d,0x0b,0x06] +# CHECK-INST: lea %s11, 324(%s13, %s11) +# CHECK-ENCODING: encoding: [0x44,0x01,0x00,0x00,0x8b,0x8d,0x0b,0x06] lea %s11, 324 (%s13,%s11) -# CHECK: lea %s11, (%s10) -# CHECK: encoding: [0x00,0x00,0x00,0x00,0x00,0x8a,0x0b,0x06] +# CHECK-INST: lea %s11, (%s10) +# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8a,0x0b,0x06] lea %s11, (%s10) -# CHECK: lea %s11, (, %s12) -# CHECK: encoding: [0x00,0x00,0x00,0x00,0x8c,0x00,0x0b,0x06] +# CHECK-INST: lea %s11, (, %s12) +# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8c,0x00,0x0b,0x06] lea %s11, (,%s12) -# CHECK: lea.sl %s11, -1(%s13, %s11) -# CHECK: encoding: [0xff,0xff,0xff,0xff,0x8b,0x8d,0x8b,0x06] +# CHECK-INST: lea.sl %s11, -1(%s13, %s11) +# CHECK-ENCODING: encoding: [0xff,0xff,0xff,0xff,0x8b,0x8d,0x8b,0x06] lea.sl %s11, -1(%s13, %s11) + +# CHECK-INST: lea.sl %s11, -1(-64, %s11) +# CHECK-ENCODING: encoding: [0xff,0xff,0xff,0xff,0x8b,0x40,0x8b,0x06] +lea.sl %s11, -1(-64, %s11) diff --git a/llvm/test/MC/VE/ST.s b/llvm/test/MC/VE/ST.s --- a/llvm/test/MC/VE/ST.s +++ b/llvm/test/MC/VE/ST.s @@ -1,33 +1,36 @@ -# RUN: llvm-mc -triple ve-unknown-unknown --show-encoding %s | FileCheck %s +# RUN: llvm-mc -triple=ve --show-encoding < %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \ +# RUN: | FileCheck %s --check-prefixes=CHECK-INST -# CHECK: st %s11, 32767 -# CHECK: encoding: [0xff,0x7f,0x00,0x00,0x00,0x00,0x0b,0x11] +# CHECK-INST: st %s11, 32767 +# CHECK-ENCODING: encoding: [0xff,0x7f,0x00,0x00,0x00,0x00,0x0b,0x11] st %s11, 32767 -# CHECK: st %s11, 20(%s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x11] +# CHECK-INST: st %s11, 20(%s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x11] st %s11, 20(%s11) -# CHECK: st %s11, -1(, %s11) -# CHECK: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x11] +# CHECK-INST: st %s11, -1(, %s11) +# CHECK-ENCODING: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x11] st %s11, -1(, %s11) -# CHECK: st %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x11] +# CHECK-INST: st %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x11] st %s11, 20(%s10, %s11) -# CHECK: stu %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x12] +# CHECK-INST: stu %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x12] stu %s11, 20(%s10, %s11) -# CHECK: stl %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x13] +# CHECK-INST: stl %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x13] stl %s11, 20(%s10, %s11) -# CHECK: st2b %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x14] +# CHECK-INST: st2b %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x14] st2b %s11, 20(%s10, %s11) -# CHECK: st1b %s11, 20(%s10, %s11) -# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x15] +# CHECK-INST: st1b %s11, 20(%s10, %s11) +# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x15] st1b %s11, 20(%s10, %s11)