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| Differential D80867
[x86] form reduction intrinsics over raw IR ClosedPublic Authored by spatel on May 30 2020, 6:34 AM.
Details Summary This flips the switch on forming reduction intrinsics in the vectorizers. The IR diffs seem ok, but that doesn't provide any info on what happens in expansion/codegen. I will see if we can expose any obvious bugs using PhaseOrdering IR tests that include the expansion pass. A motivating example is seen in https://bugs.llvm.org/show_bug.cgi?id=43953#c2 - if we had intrinsics there, we might get CGP or InstCombine to fold them.
Diff Detail
Event Timelinespatel retitled this revision from [x86][WIP] form reduction intrinsics over raw IR to [x86] form reduction intrinsics over raw IR. Comment ActionsPatch updated: I haven't figured out how to get the new pass manager to mimic that, so for now the file uses the old pass manager only. That shows the reduction expansion pass creates FP instructions for accumulation that could be avoided, but the backend squashes those. Everything else is identical. Note the failure to generate fmin/fmax reductions in SLP - it doesn't seem to recognize the min/max IR intrinsics as reduction candidates, but that's an existing/different issue. We have codegen test coverage for all of the reduction intrinsics too, so that covers everything from intrinsics to x86 asm. So I think we can enable this now without any regressions. This revision is now accepted and ready to land.Jun 4 2020, 11:52 AM spatel added inline comments.
Closed by commit rGe50059f6b6b3: [x86] form reduction intrinsics from vectorizers instead of raw IR (authored by spatel). · Explain WhyJun 5 2020, 10:04 AM This revision was automatically updated to reflect the committed changes. spatel marked an inline comment as done. spatel added inline comments.
Revision Contents
Diff 268860 llvm/lib/Target/X86/X86TargetTransformInfo.h
llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
llvm/test/Transforms/SLPVectorizer/X86/reassociated-loads.ll
llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
llvm/test/Transforms/SLPVectorizer/X86/reduction_loads.ll
llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll
llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll
llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
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maybe it's time to drop the experimental bit? :)