diff --git a/llvm/lib/MC/MCAsmInfoXCOFF.cpp b/llvm/lib/MC/MCAsmInfoXCOFF.cpp
--- a/llvm/lib/MC/MCAsmInfoXCOFF.cpp
+++ b/llvm/lib/MC/MCAsmInfoXCOFF.cpp
@@ -14,6 +14,8 @@
 
 MCAsmInfoXCOFF::MCAsmInfoXCOFF() {
   IsLittleEndian = false;
+  PrivateGlobalPrefix = "L..";
+  PrivateLabelPrefix = "L..";
   SupportsQuotedNames = false;
   UseDotAlignForAlignment = true;
   ZeroDirective = "\t.space\t";
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -477,7 +477,7 @@
 ; CHECKASM-LABEL: .call_test_fpr_max:
 
 ; ASM32PWR4:       stwu 1, -128(1)
-; ASM32PWR4-NEXT:  lwz [[REG:[0-9]+]], LC2(2)
+; ASM32PWR4-NEXT:  lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT:  lfd 1, 0([[REG]])
 ; ASM32PWR4-DAG:   stfd 1, 56(1)
 ; ASM32PWR4-DAG:   stfd 1, 64(1)
@@ -528,7 +528,7 @@
 ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:       stdu 1, -160(1)
-; ASM64PWR4-NEXT:  ld [[REG:[0-9]+]], LC2(2)
+; ASM64PWR4-NEXT:  ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT:  lfd 1, 0([[REG]])
 ; ASM64PWR4-DAG:   stfd 1, 112(1)
 ; ASM64PWR4-DAG:   stfd 1, 120(1)
@@ -718,9 +718,9 @@
 ; CHECKASM-LABEL: .call_test_vararg:
 
 ; ASM32PWR4:      stwu 1, -80(1)
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC1(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC2(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
@@ -746,9 +746,9 @@
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
@@ -786,10 +786,10 @@
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -80(1)
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC1(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: li 6, 42
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC2(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
@@ -816,10 +816,10 @@
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: li 5, 42
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
@@ -858,11 +858,11 @@
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -80(1)
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC1(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-DAG:  li 6, 0
 ; ASM32PWR4-DAG:  li 7, 42
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC2(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
@@ -889,10 +889,10 @@
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: li 5, 42
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
@@ -921,7 +921,7 @@
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -64(1)
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC1(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfs 1, 60(1)
@@ -939,7 +939,7 @@
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfs 1, 124(1)
@@ -1010,16 +1010,16 @@
 ; ASM32PWR4-DAG:   li 8, 6
 ; ASM32PWR4-DAG:   li 9, 7
 ; ASM32PWR4-DAG:   li 10, 8
-; ASM32PWR4-DAG:   lwz [[REGCADDR:[0-9]+]], LC6(2)
+; ASM32PWR4-DAG:   lwz [[REGCADDR:[0-9]+]], L..C6(2)
 ; ASM32PWR4-DAG:   lbz [[REGC:[0-9]+]], 0([[REGCADDR]])
 ; ASM32PWR4-DAG:   stw [[REGC]], 56(1)
-; ASM32PWR4-DAG:   lwz [[REGSIADDR:[0-9]+]], LC4(2)
+; ASM32PWR4-DAG:   lwz [[REGSIADDR:[0-9]+]], L..C4(2)
 ; ASM32PWR4-DAG:   lha [[REGSI:[0-9]+]], 0([[REGSIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGSI]], 60(1)
-; ASM32PWR4-DAG:   lwz [[REGIADDR:[0-9]+]], LC5(2)
+; ASM32PWR4-DAG:   lwz [[REGIADDR:[0-9]+]], L..C5(2)
 ; ASM32PWR4-DAG:   lwz [[REGI:[0-9]+]], 0([[REGIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGI]], 64(1)
-; ASM32PWR4-DAG:   lwz [[REGLLIADDR:[0-9]+]], LC7(2)
+; ASM32PWR4-DAG:   lwz [[REGLLIADDR:[0-9]+]], L..C7(2)
 ; ASM32PWR4-DAG:   lwz [[REGLLI1:[0-9]+]], 0([[REGLLIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGLLI1]], 68(1)
 ; ASM32PWR4-DAG:   lwz [[REGLLI2:[0-9]+]], 4([[REGLLIADDR]])
@@ -1064,16 +1064,16 @@
 ; ASM64PWR4-DAG:   li 8, 6
 ; ASM64PWR4-DAG:   li 9, 7
 ; ASM64PWR4-DAG:   li 10, 8
-; ASM64PWR4-DAG:   ld [[REGCADDR:[0-9]+]], LC5(2)
+; ASM64PWR4-DAG:   ld [[REGCADDR:[0-9]+]], L..C5(2)
 ; ASM64PWR4-DAG:   lbz [[REGC:[0-9]+]], 0([[REGCADDR]])
 ; ASM64PWR4-DAG:   std [[REGC]], 112(1)
-; ASM64PWR4-DAG:   ld [[REGSIADDR:[0-9]+]], LC3(2)
+; ASM64PWR4-DAG:   ld [[REGSIADDR:[0-9]+]], L..C3(2)
 ; ASM64PWR4-DAG:   lha [[REGSI:[0-9]+]], 0([[REGSIADDR]])
 ; ASM64PWR4-DAG:   std [[REGSI]], 120(1)
-; ASM64PWR4-DAG:   ld [[REGIADDR:[0-9]+]], LC4(2)
+; ASM64PWR4-DAG:   ld [[REGIADDR:[0-9]+]], L..C4(2)
 ; ASM64PWR4-DAG:   lwz [[REGI:[0-9]+]], 0([[REGIADDR]])
 ; ASM64PWR4-DAG:   std [[REGI]], 128(1)
-; ASM64PWR4-DAG:   ld [[REGLLIADDR:[0-9]+]], LC6(2)
+; ASM64PWR4-DAG:   ld [[REGLLIADDR:[0-9]+]], L..C6(2)
 ; ASM64PWR4-DAG:   ld [[REGLLI:[0-9]+]], 0([[REGLLIADDR]])
 ; ASM64PWR4-DAG:   std [[REGLLI]], 136(1)
 ; ASM64PWR4-DAG:   std [[REGI]], 144(1)
@@ -1125,9 +1125,9 @@
 ; ASM32PWR4-DAG:  li 8, 6
 ; ASM32PWR4-DAG:  li 9, 7
 ; ASM32PWR4-DAG:  li 10, 8
-; ASM32PWR4-DAG:  lwz [[REGF:[0-9]+]], LC8(2)
+; ASM32PWR4-DAG:  lwz [[REGF:[0-9]+]], L..C8(2)
 ; ASM32PWR4-DAG:  lfs 1, 0([[REGF]])
-; ASM32PWR4-DAG:  lwz [[REGD:[0-9]+]], LC9(2)
+; ASM32PWR4-DAG:  lwz [[REGD:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG:  lfd 2, 0([[REGD:[0-9]+]])
 ; ASM32PWR4-DAG:  stfs 1, 56(1)
 ; ASM32PWR4-DAG:  stfd 2, 60(1)
@@ -1164,9 +1164,9 @@
 ; ASM64PWR4-DAG:  li 8, 6
 ; ASM64PWR4-DAG:  li 9, 7
 ; ASM64PWR4-DAG:  li 10, 8
-; ASM64PWR4-DAG:  ld [[REGF:[0-9]+]], LC7(2)
+; ASM64PWR4-DAG:  ld [[REGF:[0-9]+]], L..C7(2)
 ; ASM64PWR4-DAG:  lfs 1, 0([[REGF]])
-; ASM64PWR4-DAG:  ld [[REGD:[0-9]+]], LC8(2)
+; ASM64PWR4-DAG:  ld [[REGD:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG:  lfd 2, 0([[REGD]])
 ; ASM64PWR4-DAG:  stfs 1, 112(1)
 ; ASM64PWR4-DAG:  stfd 2, 120(1)
@@ -1211,7 +1211,7 @@
 ; ASM32PWR4-DAG: li 6, 4
 ; ASM32PWR4-DAG: li 7, 5
 ; ASM32PWR4-DAG: li 8, 6
-; ASM32PWR4-DAG: lwz [[REG:[0-9]+]], LC9(2)
+; ASM32PWR4-DAG: lwz [[REG:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG: lfd 1, 0([[REG]])
 ; ASM32PWR4-DAG: stfd 1, 56(1)
 ; ASM32PWR4-DAG: lwz 9, 56(1)
@@ -1243,7 +1243,7 @@
 ; ASM64PWR4-DAG: li 6, 4
 ; ASM64PWR4-DAG: li 7, 5
 ; ASM64PWR4-DAG: li 8, 6
-; ASM64PWR4-DAG: ld [[REG:[0-9]+]], LC8(2)
+; ASM64PWR4-DAG: ld [[REG:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG: lfd 1, 0([[REG]])
 ; ASM64PWR4-DAG: stfd 1, 120(1)
 ; ASM64PWR4-DAG: ld 9, 120(1)
@@ -1296,9 +1296,9 @@
 ; ASM32PWR4-DAG:   li 7, 5
 ; ASM32PWR4-DAG:   li 8, 6
 ; ASM32PWR4-DAG:   li 9, 7
-; ASM32PWR4-DAG:   lwz [[REGD:[0-9]+]], LC9(2)
+; ASM32PWR4-DAG:   lwz [[REGD:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG:   lfd 1, 0([[REGD]])
-; ASM32PWR4-DAG:   lwz [[REGF:[0-9]+]], LC8(2)
+; ASM32PWR4-DAG:   lwz [[REGF:[0-9]+]], L..C8(2)
 ; ASM32PWR4-DAG:   lfs 2, 0([[REGF]])
 ; ASM32PWR4-DAG:   stfd 1, 52(1)
 ; ASM32PWR4-DAG:   stfs 2, 60(1)
@@ -1338,9 +1338,9 @@
 ; ASM64PWR4-DAG:   li 7, 5
 ; ASM64PWR4-DAG:   li 8, 6
 ; ASM64PWR4-DAG:   li 9, 7
-; ASM64PWR4-DAG:   ld [[REGD:[0-9]+]], LC8(2)
+; ASM64PWR4-DAG:   ld [[REGD:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG:   lfd 1, 0([[REGD]])
-; ASM64PWR4-DAG:   ld [[REGF:[0-9]+]], LC7(2)
+; ASM64PWR4-DAG:   ld [[REGF:[0-9]+]], L..C7(2)
 ; ASM64PWR4-DAG:   lfs 2, 0([[REGF]])
 ; ASM64PWR4-DAG:   stfs 2, 112(1)
 ; ASM64PWR4-DAG:   stfd 1, 120(1)
@@ -1564,14 +1564,14 @@
 ; ASM32PWR4-DAG:    li 9, 7
 ; ASM32PWR4-DAG:    li 8, 6
 ; ASM32PWR4-DAG:    li 10, 8
-; ASM32PWR4-DAG:    lwz [[REG1:[0-9]+]], LC10(2)
-; ASM32PWR4-DAG:    lwz [[REG2:[0-9]+]], LC11(2)
-; ASM32PWR4-DAG:    lwz [[REG3:[0-9]+]], LC12(2)
-; ASM32PWR4-DAG:    lwz [[REG4:[0-9]+]], LC13(2)
-; ASM32PWR4-DAG:    lwz [[REG5:[0-9]+]], LC14(2)
-; ASM32PWR4-DAG:    lwz [[REG6:[0-9]+]], LC15(2)
-; ASM32PWR4-DAG:    lwz [[REG7:[0-9]+]], LC16(2)
-; ASM32PWR4-DAG:    lwz [[REG8:[0-9]+]], LC17(2)
+; ASM32PWR4-DAG:    lwz [[REG1:[0-9]+]], L..C10(2)
+; ASM32PWR4-DAG:    lwz [[REG2:[0-9]+]], L..C11(2)
+; ASM32PWR4-DAG:    lwz [[REG3:[0-9]+]], L..C12(2)
+; ASM32PWR4-DAG:    lwz [[REG4:[0-9]+]], L..C13(2)
+; ASM32PWR4-DAG:    lwz [[REG5:[0-9]+]], L..C14(2)
+; ASM32PWR4-DAG:    lwz [[REG6:[0-9]+]], L..C15(2)
+; ASM32PWR4-DAG:    lwz [[REG7:[0-9]+]], L..C16(2)
+; ASM32PWR4-DAG:    lwz [[REG8:[0-9]+]], L..C17(2)
 ; ASM32PWR4-DAG:    lha 5, 0([[REG1]])
 ; ASM32PWR4-DAG:    lwz 11, 0([[REG7]])
 ; ASM32PWR4-DAG:    lwz 7, 4([[REG7]])
@@ -1610,14 +1610,14 @@
 ; ASM64PWR4-DAG:    li 8, 6
 ; ASM64PWR4-DAG:    li 9, 7
 ; ASM64PWR4-DAG:    li 10, 8
-; ASM64PWR4-DAG:    ld [[REG1:[0-9]+]], LC9(2)
-; ASM64PWR4-DAG:    ld [[REG2:[0-9]+]], LC10(2)
-; ASM64PWR4-DAG:    ld [[REG3:[0-9]+]], LC11(2)
-; ASM64PWR4-DAG:    ld [[REG4:[0-9]+]], LC12(2)
-; ASM64PWR4-DAG:    ld [[REG5:[0-9]+]], LC13(2)
-; ASM64PWR4-DAG:    ld [[REG6:[0-9]+]], LC14(2)
-; ASM64PWR4-DAG:    ld [[REG7:[0-9]+]], LC15(2)
-; ASM64PWR4-DAG:    ld [[REG8:[0-9]+]], LC16(2)
+; ASM64PWR4-DAG:    ld [[REG1:[0-9]+]], L..C9(2)
+; ASM64PWR4-DAG:    ld [[REG2:[0-9]+]], L..C10(2)
+; ASM64PWR4-DAG:    ld [[REG3:[0-9]+]], L..C11(2)
+; ASM64PWR4-DAG:    ld [[REG4:[0-9]+]], L..C12(2)
+; ASM64PWR4-DAG:    ld [[REG5:[0-9]+]], L..C13(2)
+; ASM64PWR4-DAG:    ld [[REG6:[0-9]+]], L..C14(2)
+; ASM64PWR4-DAG:    ld [[REG7:[0-9]+]], L..C15(2)
+; ASM64PWR4-DAG:    ld [[REG8:[0-9]+]], L..C16(2)
 ; ASM64PWR4-DAG:    lha 7, 0([[REG1]])
 ; ASM64PWR4-DAG:    lbz 5, 0([[REG2]])
 ; ASM64PWR4-DAG:    ld 6, 0([[REG3]])
@@ -1672,12 +1672,12 @@
 ; CHECKASM-LABEL:  test_i1_stack:
 
 ; ASM32PWR4-DAG:   lbz [[REGB:[0-9]+]], 59(1)
-; ASM32PWR4-DAG:   lwz [[REGBTOC:[0-9]+]], LC18(2)
+; ASM32PWR4-DAG:   lwz [[REGBTOC:[0-9]+]], L..C18(2)
 ; ASM32PWR4-DAG:   stb [[SCRATCHREG:[0-9]+]], 0([[REGBTOC]])
 ; ASM32PWR4-DAG:   blr
 
 ; ASM64PWR4-DAG:   lbz [[REGB:[0-9]+]], 119(1)
-; ASM64PWR4-DAG:   ld [[REGBTOC:[0-9]+]], LC17(2)
+; ASM64PWR4-DAG:   ld [[REGBTOC:[0-9]+]], L..C17(2)
 ; ASM64PWR4-DAG:   stb [[SCRATCHREG:[0-9]+]], 0([[REGBTOC]])
 ; ASM64PWR4-DAG:   blr
 
@@ -1924,11 +1924,11 @@
 ; ASM32PWR4:       mflr 0
 ; ASM32PWR4-DAG:   stw 0, 8(1)
 ; ASM32PWR4-DAG:   stwu 1, -144(1)
-; ASM32PWR4-DAG:   lwz [[REGF1ADDR:[0-9]+]], LC20(2)
+; ASM32PWR4-DAG:   lwz [[REGF1ADDR:[0-9]+]], L..C20(2)
 ; ASM32PWR4-DAG:   lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]])
-; ASM32PWR4-DAG:   lwz [[REGDADDR:[0-9]+]], LC19(2)
+; ASM32PWR4-DAG:   lwz [[REGDADDR:[0-9]+]], L..C19(2)
 ; ASM32PWR4-DAG:   lfd [[REGD:[0-9]+]], 0([[REGDADDR]])
-; ASM32PWR4-DAG:   lwz [[REGF2ADDR:[0-9]+]], LC21(2)
+; ASM32PWR4-DAG:   lwz [[REGF2ADDR:[0-9]+]], L..C21(2)
 ; ASM32PWR4-DAG:   lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]])
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 56(1)
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 60(1)
@@ -1956,11 +1956,11 @@
 ; ASM64PWR4:       mflr 0
 ; ASM64PWR4-DAG:   std 0, 16(1)
 ; ASM64PWR4-DAG:   stdu 1, -176(1)
-; ASM64PWR4-DAG:   ld [[REGF1ADDR:[0-9]+]], LC18(2)
+; ASM64PWR4-DAG:   ld [[REGF1ADDR:[0-9]+]], L..C18(2)
 ; ASM64PWR4-DAG:   lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]])
-; ASM64PWR4-DAG:   ld [[REGDADDR:[0-9]+]], LC19(2)
+; ASM64PWR4-DAG:   ld [[REGDADDR:[0-9]+]], L..C19(2)
 ; ASM64PWR4-DAG:   ld [[REGD:[0-9]+]], 0([[REGDADDR]])
-; ASM64PWR4-DAG:   ld [[REGF2ADDR:[0-9]+]], LC20(2)
+; ASM64PWR4-DAG:   ld [[REGF2ADDR:[0-9]+]], L..C20(2)
 ; ASM64PWR4-DAG:   lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]])
 ; ASM64PWR4-DAG:   std [[SCRATCHREG:[0-9]+]], 112(1)
 ; ASM64PWR4-DAG:   std [[SCRATCHREG:[0-9]+]], 120(1)
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
@@ -30,14 +30,14 @@
 ; CHECKASM-LABEL: .call_test_byval_mem1:
 
 ; ASM32BIT:       stwu 1, -64(1)
-; ASM32BIT:       lwz [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32BIT:       lwz [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32BIT:       lbz [[REG2:[0-9]+]], 0([[REG1]])
 ; ASM32BIT:       stb [[REG2]], 56(1)
 ; ASM32BIT:       bl .test_byval_mem1
 ; ASM32BIT:       addi 1, 1, 64
 
 ; ASM64BIT:       stdu 1, -128(1)
-; ASM64BIT:       ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64BIT:       ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT:       lbz [[REG2:[0-9]+]], 0([[REG1]])
 ; ASM64BIT:       stb [[REG2]], 112(1)
 ; ASM64BIT:       bl .test_byval_mem1
@@ -106,7 +106,7 @@
 
 ; ASM32BIT:       stwu 1, -320(1)
 ; ASM32BIT-DAG:   addi 3, 1, 56
-; ASM32BIT-DAG:   lwz 4, LC{{[0-9]+}}(2)
+; ASM32BIT-DAG:   lwz 4, L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   li 5, 256
 ; ASM32BIT-NEXT:  bl .memcpy
 ; ASM32BIT:       bl .test_byval_mem2
@@ -136,7 +136,7 @@
 
 ; ASM64BIT:       stdu 1, -368(1)
 ; ASM64BIT-DAG:   addi 3, 1, 112
-; ASM64BIT-DAG:   ld 4, LC{{[0-9]+}}(2)
+; ASM64BIT-DAG:   ld 4, L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   li 5, 256
 ; ASM64BIT-NEXT:  bl .memcpy
 ; ASM64BIT:       bl .test_byval_mem2
@@ -204,7 +204,7 @@
 ; CHECKASM-LABEL: .call_test_byval_mem3:
 
 ; ASM32BIT:       stwu 1, -112(1)
-; ASM32BIT-DAG:   lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32BIT-DAG:   lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   addi 3, 1, 56
 ; ASM32BIT-DAG:   addi 4, [[REG]], 24
 ; ASM32BIT-DAG:   li 5, 33
@@ -220,7 +220,7 @@
 
 ; The memcpy call was inlined in 64-bit so MIR test is redundant and omitted.
 ; ASM64BIT:       stdu 1, -128(1)
-; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], 48([[REG1]])
 ; ASM64BIT-DAG:   std [[REG2]], 112(1)
 ; ASM64BIT-DAG:   lbz [[REG3:[0-9]+]], 56([[REG1]])
@@ -321,13 +321,13 @@
 
 ; ASM32BIT:       stwu 1, -336(1)
 ; ASM32BIT-NEXT:  stw [[REG1:[0-9]+]], {{[0-9]+}}(1)
-; ASM32BIT:       lwz [[REG1]], LC{{[0-9]+}}(2)
+; ASM32BIT:       lwz [[REG1]], L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   lhz [[REG2:[0-9]+]], 28([[REG1]])
 ; ASM32BIT-DAG:   sth [[REG2]], 56(1)
 ; ASM32BIT-DAG:   lbz [[REG3:[0-9]+]], 30([[REG1]])
 ; ASM32BIT-DAG:   stb [[REG3]], 58(1)
 ; ASM32BIT-DAG:   addi 3, 1, 60
-; ASM32BIT-DAG:   lwz 4, LC{{[0-9]+}}(2)
+; ASM32BIT-DAG:   lwz 4, L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   li 5, 256
 ; ASM32BIT-NEXT:  bl .memcpy
 ; ASM32BIT-DAG:   lwz 4, 0([[REG1]])
@@ -364,12 +364,12 @@
 ; 64BIT-NEXT:     ADJCALLSTACKUP 344, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64BIT:       stdu 1, -368(1)
-; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   addi 3, 1, 112
 ; ASM64BIT-DAG:   addi 4, [[REG1]], 24
 ; ASM64BIT-DAG:   li 5, 232
 ; ASM64BIT-NEXT:  bl .memcpy
-; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld 4, 0([[REG2]])
 ; ASM64BIT-DAG:   ld 5, 8([[REG2]])
 ; ASM64BIT-DAG:   ld 6, 16([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
@@ -39,7 +39,7 @@
 ; CHECKASM-LABEL: .call_test_byval_1Byte:
 
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-NEXT:  lbz 3, 0([[REG]])
 ; ASM32-NEXT:  slwi 3, 3, 24
 ; ASM32-NEXT:  bl .test_byval_1Byte
@@ -55,7 +55,7 @@
 
 ; ASM64:       std 0, 16(1)
 ; ASM64-NEXT:  stdu 1, -128(1)
-; ASM64-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-NEXT:  lbz 3, 0([[REG]])
 ; ASM64-NEXT:  sldi 3, 3, 56
 ; ASM64-NEXT:  bl .test_byval_1Byte
@@ -139,9 +139,9 @@
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-DAG:   li 3, 42
-; ASM32-DAG:   lwz [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-DAG:   lwz [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lfs 1, 0([[REG1]])
-; ASM32-DAG:   lwz [[REG2:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-DAG:   lwz [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lhz [[REG3:[0-9]+]], 0([[REG2]])
 ; ASM32-DAG:   slwi 5, [[REG3]], 16
 ; ASM32-DAG:   fmr 2, 1
@@ -167,9 +167,9 @@
 ; ASM64:       std 0, 16(1)
 ; ASM64-NEXT:  stdu 1, -112(1)
 ; ASM64-DAG:   li 3, 42
-; ASM64-DAG:   ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lfs 1, 0([[REG1]])
-; ASM64-DAG:   ld [[REG2:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-DAG:   ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lhz [[REG3:[0-9]+]], 0([[REG2]])
 ; ASM64-DAG:   sldi 5, [[REG3]], 48
 ; ASM64-DAG:   fmr 2, 1
@@ -254,7 +254,7 @@
 ; ASM32-DAG:   li 7, 5
 ; ASM32-DAG:   li 8, 6
 ; ASM32-DAG:   li 9, 7
-; ASM32-DAG:   lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-DAG:   lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM32-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
 ; ASM32-DAG:   rlwinm 10, [[REG2]], 8, 16, 23
@@ -292,7 +292,7 @@
 ; ASM64-DAG:   li 7, 5
 ; ASM64-DAG:   li 8, 6
 ; ASM64-DAG:   li 9, 7
-; ASM64-DAG:   ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-DAG:   ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
 ; ASM64-DAG:   rldic 10, [[REG2]], 40, 16
@@ -366,7 +366,7 @@
 ; CHECKASM-LABEL: .call_test_byval_4Byte:
 
 ; ASM32:       stwu 1, -80(1)
-; ASM32-NEXT:  lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REG]])
 ; ASM32-DAG:   lwz 4, 64(1)
 ; ASM32-NEXT:  bl .test_byval_4Byte
@@ -383,7 +383,7 @@
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -128(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[LD1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lwz [[LD2:[0-9]+]], 112(1)
 ; ASM64-DAG:   sldi 3, [[LD1]], 32
@@ -486,7 +486,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lbz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   slwi 4, [[REG1]], 24
@@ -505,7 +505,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   rlwinm 3, [[REG2]], 24, 0, 7
@@ -541,7 +541,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   slwi 4, [[REG1]], 16
@@ -560,7 +560,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   rlwinm 3, [[REG2]], 16, 0, 15
@@ -598,7 +598,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lbz [[REG2:[0-9]+]], 6([[REGADDR]])
@@ -621,7 +621,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG3:[0-9]+]], 6([[REGADDR]])
@@ -658,7 +658,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lwz 4, 4([[REGADDR]])
 ; ASM32-NEXT:  bl .test_byval_8Byte
@@ -671,7 +671,7 @@
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-NEXT:  ld 3, 0([[REGADDR]])
 ; ASM64-NEXT:  bl .test_byval_8Byte
 ; ASM64-NEXT:  nop
@@ -707,7 +707,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lwz 4, 4([[REGADDR]])
 ; ASM32-DAG:   lwz 5, 8([[REGADDR]])
@@ -730,7 +730,7 @@
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   ld 3, 0([[REGADDR]])
 ; ASM64-DAG:   ld 4, 8([[REGADDR]])
 ; ASM64-DAG:   ld 5, 16([[REGADDR]])
@@ -834,7 +834,7 @@
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lwz 4, 4([[REGADDR]])
 ; ASM32-DAG:   lwz 5, 8([[REGADDR]])
@@ -865,7 +865,7 @@
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   ld 3, 0([[REGADDR]])
 ; ASM64-DAG:   ld 4, 8([[REGADDR]])
 ; ASM64-DAG:   ld 5, 16([[REGADDR]])
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
--- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -57,9 +57,9 @@
 ; COMMON-NEXT:    .weak   .foo_ext_weak
 ; COMMON-NEXT:    .weak   foo_ext_weak[DS]
 ; COMMON-NEXT:    .toc
-; COMMON-NEXT: LC0:
+; COMMON-NEXT: L..C0:
 ; COMMON-NEXT:    .tc foo_ext_weak_p[TC],foo_ext_weak_p
-; COMMON-NEXT: LC1:
+; COMMON-NEXT: L..C1:
 ; COMMON-NEXT:    .tc b_w[TC],b_w[UA]
 
 ; CHECK-NOT:      .weak   .foo_ext_weak_ref
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern.ll b/llvm/test/CodeGen/PowerPC/aix-extern.ll
--- a/llvm/test/CodeGen/PowerPC/aix-extern.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern.ll
@@ -77,9 +77,9 @@
 ; COMMON-NEXT:	    .extern	.bar_extern
 ; COMMON-NEXT:      .extern     bar_extern[DS]
 ; COMMON-NEXT:	    .toc
-; COMMON-NEXT: LC0:
+; COMMON-NEXT: L..C0:
 ; COMMON-NEXT:      .tc b_e[TC],b_e[UA]
-; COMMON-NEXT: LC1:
+; COMMON-NEXT: L..C1:
 ; COMMON-NEXT:      .tc bar_p[TC],bar_p
 
 ; CHECKSYM:       Symbols [
diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll b/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
--- a/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll
@@ -48,25 +48,25 @@
 
 ; 32SMALL-ASM-LABEL: foo
 ; 32SMALL-ASM: .foo:
-; 32SMALL-ASM: Ltmp0:
-; 32SMALL-ASM: 	       lwz [[REG1:[0-9]+]], LC0(2)
+; 32SMALL-ASM: L..tmp0:
+; 32SMALL-ASM: 	       lwz [[REG1:[0-9]+]], L..C0(2)
 
 ; 32LARGE-ASM-LABEL: foo
 ; 32LARGE-ASM: .foo:
-; 32LARGE-ASM: Ltmp0:
-; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
-; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 32LARGE-ASM: L..tmp0:
+; 32LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
+; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
 
 ; 64SMALL-ASM-LABEL: foo
 ; 64SMALL-ASM: .foo:
-; 64SMALL-ASM: Ltmp0:
-; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
+; 64SMALL-ASM: L..tmp0:
+; 64SMALL-ASM:         ld [[REG1:[0-9]+]], L..C0(2)
 
 ; 64LARGE-ASM-LABEL: foo
 ; 64LARGE-ASM: .foo:
-; 64LARGE-ASM: Ltmp0:
-; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
-; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 64LARGE-ASM: L..tmp0:
+; 64LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
+; 64LARGE-ASM:         ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
 
 ; CHECK: .toc
-; CHECK: .tc Ltmp0[TC],Ltmp0
+; CHECK: .tc L..tmp0[TC],L..tmp0
diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll b/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
--- a/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
@@ -50,7 +50,7 @@
 ; 32SMALL-ASM: .LCPI0_0:
 ; 32SMALL-ASM:         .vbyte	4, 0x40b00000
 ; 32SMALL-ASM: .test_float:
-; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
+; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], L..C0(2)
 ; 32SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 32SMALL-ASM:         blr
 
@@ -59,8 +59,8 @@
 ; 32LARGE-ASM: .LCPI0_0:
 ; 32LARGE-ASM:         .vbyte	4, 0x40b00000
 ; 32LARGE-ASM: .test_float:
-; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
-; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 32LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
+; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; 32LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 32LARGE-ASM:         blr
 
@@ -69,7 +69,7 @@
 ; 64SMALL-ASM: .LCPI0_0:
 ; 64SMALL-ASM:         .vbyte	4, 0x40b00000
 ; 64SMALL-ASM: .test_float:
-; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
+; 64SMALL-ASM:         ld [[REG1:[0-9]+]], L..C0(2)
 ; 64SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 64SMALL-ASM:         blr
 
@@ -78,8 +78,8 @@
 ; 64LARGE-ASM: .LCPI0_0:
 ; 64LARGE-ASM:         .vbyte	4, 0x40b00000
 ; 64LARGE-ASM: .test_float:
-; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
-; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 64LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
+; 64LARGE-ASM:         ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; 64LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 64LARGE-ASM:         blr
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
--- a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
@@ -82,107 +82,107 @@
 ; 32SMALL-ASM: .jump_table:
 ; 32SMALL-ASM:      addi 3, 3, -1
 ; 32SMALL-ASM: 	    cmplwi 3, 3
-; 32SMALL-ASM: 	    bgt	0, LBB0_6
-; 32SMALL-ASM: 	    lwz 4, LC0(2)
+; 32SMALL-ASM: 	    bgt	0, L..BB0_6
+; 32SMALL-ASM: 	    lwz 4, L..C0(2)
 ; 32SMALL-ASM: 	    slwi 3, 3, 2
 ; 32SMALL-ASM: 	    lwzx 3, 3, 4
 ; 32SMALL-ASM: 	    add 3, 3, 4
 ; 32SMALL-ASM: 	    mtctr 3
 ; 32SMALL-ASM: 	    bctr
-; 32SMALL-ASM: LBB0_2:
-; 32SMALL-ASM: LBB0_3:
-; 32SMALL-ASM: LBB0_4:
-; 32SMALL-ASM: LBB0_5:
-; 32SMALL-ASM: LBB0_6:
+; 32SMALL-ASM: L..BB0_2:
+; 32SMALL-ASM: L..BB0_3:
+; 32SMALL-ASM: L..BB0_4:
+; 32SMALL-ASM: L..BB0_5:
+; 32SMALL-ASM: L..BB0_6:
 ; 32SMALL-ASM: 	    li 3, 0
 ; 32SMALL-ASM: 	    blr
 ; 32SMALL-ASM: 	    .csect .rodata[RO],2
 ; 32SMALL-ASM: 	    .align  2
 ; 32SMALL-ASM: .LJTI0_0:
-; 32SMALL-ASM: 	    .vbyte	4, LBB0_2-.LJTI0_0
-; 32SMALL-ASM: 	    .vbyte	4, LBB0_3-.LJTI0_0
-; 32SMALL-ASM: 	    .vbyte	4, LBB0_4-.LJTI0_0
-; 32SMALL-ASM: 	    .vbyte	4, LBB0_5-.LJTI0_0
+; 32SMALL-ASM: 	    .vbyte	4, L..BB0_2-.LJTI0_0
+; 32SMALL-ASM: 	    .vbyte	4, L..BB0_3-.LJTI0_0
+; 32SMALL-ASM: 	    .vbyte	4, L..BB0_4-.LJTI0_0
+; 32SMALL-ASM: 	    .vbyte	4, L..BB0_5-.LJTI0_0
 
 ; 32LARGE-ASM-LABEL: jump_table
 ; 32LARGE-ASM: .jump_table:
 ; 32LARGE-ASM:      addi 3, 3, -1
 ; 32LARGE-ASM:      cmplwi  3, 3
-; 32LARGE-ASM:      bgt     0, LBB0_6
-; 32LARGE-ASM: 	    addis 4, LC0@u(2)
+; 32LARGE-ASM:      bgt     0, L..BB0_6
+; 32LARGE-ASM: 	    addis 4, L..C0@u(2)
 ; 32LARGE-ASM: 	    slwi 3, 3, 2
-; 32LARGE-ASM:      lwz 4, LC0@l(4)
+; 32LARGE-ASM:      lwz 4, L..C0@l(4)
 ; 32LARGE-ASM:      lwzx 3, 3, 4
 ; 32LARGE-ASM:      add 3, 3, 4
 ; 32LARGE-ASM:      mtctr 3
 ; 32LARGE-ASM:      bctr
-; 32LARGE-ASM: LBB0_2:
-; 32LARGE-ASM: LBB0_3:
-; 32LARGE-ASM: LBB0_4:
-; 32LARGE-ASM: LBB0_5:
-; 32LARGE-ASM: LBB0_6:
+; 32LARGE-ASM: L..BB0_2:
+; 32LARGE-ASM: L..BB0_3:
+; 32LARGE-ASM: L..BB0_4:
+; 32LARGE-ASM: L..BB0_5:
+; 32LARGE-ASM: L..BB0_6:
 ; 32LARGE-ASM:      li 3, 0
 ; 32LARGE-ASM:      blr
 ; 32LARGE-ASM:      .csect .rodata[RO],2
 ; 32LARGE-ASM:      .align  2
 ; 32LARGE-ASM: .LJTI0_0:
-; 32LARGE-ASM:      .vbyte	4, LBB0_2-.LJTI0_0
-; 32LARGE-ASM:      .vbyte	4, LBB0_3-.LJTI0_0
-; 32LARGE-ASM:      .vbyte	4, LBB0_4-.LJTI0_0
-; 32LARGE-ASM:      .vbyte	4, LBB0_5-.LJTI0_0
+; 32LARGE-ASM:      .vbyte	4, L..BB0_2-.LJTI0_0
+; 32LARGE-ASM:      .vbyte	4, L..BB0_3-.LJTI0_0
+; 32LARGE-ASM:      .vbyte	4, L..BB0_4-.LJTI0_0
+; 32LARGE-ASM:      .vbyte	4, L..BB0_5-.LJTI0_0
 
 ; 64SMALL-ASM-LABEL: jump_table
 ; 64SMALL-ASM: .jump_table:
 ; 64SMALL-ASM:      addi 3, 3, -1
 ; 64SMALL-ASM:      cmplwi  3, 3
-; 64SMALL-ASM:      bgt     0, LBB0_6
-; 64SMALL-ASM:      ld 4, LC0(2)
+; 64SMALL-ASM:      bgt     0, L..BB0_6
+; 64SMALL-ASM:      ld 4, L..C0(2)
 ; 64SMALL-ASM:      rldic 3, 3, 2, 30
 ; 64SMALL-ASM:      lwax 3, 3, 4
 ; 64SMALL-ASM:      add 3, 3, 4
 ; 64SMALL-ASM:      mtctr 3
 ; 64SMALL-ASM:      bctr
-; 64SMALL-ASM: LBB0_2:
-; 64SMALL-ASM: LBB0_3:
-; 64SMALL-ASM: LBB0_4:
-; 64SMALL-ASM: LBB0_5:
-; 64SMALL-ASM: LBB0_6:
+; 64SMALL-ASM: L..BB0_2:
+; 64SMALL-ASM: L..BB0_3:
+; 64SMALL-ASM: L..BB0_4:
+; 64SMALL-ASM: L..BB0_5:
+; 64SMALL-ASM: L..BB0_6:
 ; 64SMALL-ASM:      li 3, 0
 ; 64SMALL-ASM:      blr
 ; 64SMALL-ASM:      .csect .rodata[RO],2
 ; 64SMALL-ASM:      .align  2
 ; 64SMALL-ASM: .LJTI0_0:
-; 64SMALL-ASM:      .vbyte	4, LBB0_2-.LJTI0_0
-; 64SMALL-ASM:      .vbyte	4, LBB0_3-.LJTI0_0
-; 64SMALL-ASM:      .vbyte	4, LBB0_4-.LJTI0_0
-; 64SMALL-ASM:      .vbyte	4, LBB0_5-.LJTI0_0
+; 64SMALL-ASM:      .vbyte	4, L..BB0_2-.LJTI0_0
+; 64SMALL-ASM:      .vbyte	4, L..BB0_3-.LJTI0_0
+; 64SMALL-ASM:      .vbyte	4, L..BB0_4-.LJTI0_0
+; 64SMALL-ASM:      .vbyte	4, L..BB0_5-.LJTI0_0
 
 ; 64LARGE-ASM-LABEL: jump_table
 ; 64LARGE-ASM: .jump_table:
 ; 64LARGE-ASM:      addi 3, 3, -1
 ; 64LARGE-ASM:      cmplwi  3, 3
-; 64LARGE-ASM:      bgt     0, LBB0_6
-; 64LARGE-ASM:      addis 4, LC0@u(2)
+; 64LARGE-ASM:      bgt     0, L..BB0_6
+; 64LARGE-ASM:      addis 4, L..C0@u(2)
 ; 64LARGE-ASM:      rldic 3, 3, 2, 30
-; 64LARGE-ASM:      ld 4, LC0@l(4)
+; 64LARGE-ASM:      ld 4, L..C0@l(4)
 ; 64LARGE-ASM:      lwax 3, 3, 4
 ; 64LARGE-ASM:      add 3, 3, 4
 ; 64LARGE-ASM:      mtctr 3
 ; 64LARGE-ASM:      bctr
-; 64LARGE-ASM: LBB0_2:
-; 64LARGE-ASM: LBB0_3:
-; 64LARGE-ASM: LBB0_4:
-; 64LARGE-ASM: LBB0_5:
-; 64LARGE-ASM: LBB0_6:
+; 64LARGE-ASM: L..BB0_2:
+; 64LARGE-ASM: L..BB0_3:
+; 64LARGE-ASM: L..BB0_4:
+; 64LARGE-ASM: L..BB0_5:
+; 64LARGE-ASM: L..BB0_6:
 ; 64LARGE-ASM:      li 3, 0
 ; 64LARGE-ASM:      blr
 ; 64LARGE-ASM:      .csect .rodata[RO],2
 ; 64LARGE-ASM:      .align  2
 ; 64LARGE-ASM: .LJTI0_0:
-; 64LARGE-ASM:      .vbyte	4, LBB0_2-.LJTI0_0
-; 64LARGE-ASM:      .vbyte	4, LBB0_3-.LJTI0_0
-; 64LARGE-ASM:      .vbyte	4, LBB0_4-.LJTI0_0
-; 64LARGE-ASM:      .vbyte	4, LBB0_5-.LJTI0_0
+; 64LARGE-ASM:      .vbyte	4, L..BB0_2-.LJTI0_0
+; 64LARGE-ASM:      .vbyte	4, L..BB0_3-.LJTI0_0
+; 64LARGE-ASM:      .vbyte	4, L..BB0_4-.LJTI0_0
+; 64LARGE-ASM:      .vbyte	4, L..BB0_5-.LJTI0_0
 
 ; CHECK: .toc
 ; CHECK: .tc .LJTI0_0[TC],.LJTI0_0
diff --git a/llvm/test/CodeGen/PowerPC/aix-weak.ll b/llvm/test/CodeGen/PowerPC/aix-weak.ll
--- a/llvm/test/CodeGen/PowerPC/aix-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-weak.ll
@@ -92,9 +92,9 @@
 ; COMMON-NEXT:  b:
 ; COMMON-NEXT:          .vbyte	4, 0                       # 0x0
 ; COMMON-NEXT:          .toc
-; COMMON-NEXT:  LC0:
+; COMMON-NEXT:  L..C0:
 ; COMMON-NEXT:          .tc foo_weak_p[TC],foo_weak_p
-; COMMON-NEXT:  LC1:
+; COMMON-NEXT:  L..C1:
 ; COMMON-NEXT:          .tc b[TC],b
 
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-externL.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-externL.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-externL.ll
@@ -0,0 +1,64 @@
+;; Test to make sure a symbol name that starts with an 'L' could be succesfully
+;; consumed. Note that this could fail if PrivateGlobalPrefix returns
+;; 'L'/'.L' instead of 'L..' because the resulting symbol gets created as
+;; a temporary symbol.
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN:     -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --symbols %t.o | \
+; RUN:   FileCheck --check-prefix=XCOFF32 %s
+
+; RUN: not --crash llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -mcpu=pwr4 -mattr=-altivec -filetype=obj -o %t.o 2>&1 < %s | \
+; RUN:   FileCheck --check-prefix=XCOFF64 %s
+; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
+
+@La = external global i32, align 4
+
+declare i32 @Lb(...)
+
+define void @foo() {
+entry:
+  store i32 1, i32* @La, align 4
+  call i32 bitcast (i32 (...)* @Lb to i32 ()*)()
+  ret void
+}
+
+; XCOFF32:         Index: [[#IND:]]{{.*}}{{[[:space:]] *}}Name: .Lb
+; XCOFF32-NEXT:    Value (RelocatableAddress): 0x0
+; XCOFF32-NEXT:    Section: N_UNDEF
+; XCOFF32-NEXT:    Type: 0x0
+; XCOFF32-NEXT:    StorageClass: C_EXT (0x2)
+; XCOFF32-NEXT:    NumberOfAuxEntries: 1
+; XCOFF32-NEXT:    CSECT Auxiliary Entry {
+; XCOFF32-NEXT:      Index: [[#IND+1]]
+; XCOFF32-NEXT:      SectionLen: 0
+; XCOFF32-NEXT:      ParameterHashIndex: 0x0
+; XCOFF32-NEXT:      TypeChkSectNum: 0x0
+; XCOFF32-NEXT:      SymbolAlignmentLog2: 0
+; XCOFF32-NEXT:      SymbolType: XTY_ER (0x0)
+; XCOFF32-NEXT:      StorageMappingClass: XMC_PR (0x0)
+; XCOFF32-NEXT:      StabInfoIndex: 0x0
+; XCOFF32-NEXT:      StabSectNum: 0x0
+; XCOFF32-NEXT:    }
+; XCOFF32-NEXT:  }
+; XCOFF32-NEXT:  Symbol {
+; XCOFF32-NEXT:    Index: [[#IND+2]]
+; XCOFF32-NEXT:    Name: La
+; XCOFF32-NEXT:    Value (RelocatableAddress): 0x0
+; XCOFF32-NEXT:    Section: N_UNDEF
+; XCOFF32-NEXT:    Type: 0x0
+; XCOFF32-NEXT:    StorageClass: C_EXT (0x2)
+; XCOFF32-NEXT:    NumberOfAuxEntries: 1
+; XCOFF32-NEXT:    CSECT Auxiliary Entry {
+; XCOFF32-NEXT:      Index: [[#IND+3]]
+; XCOFF32-NEXT:      SectionLen: 0
+; XCOFF32-NEXT:      ParameterHashIndex: 0x0
+; XCOFF32-NEXT:      TypeChkSectNum: 0x0
+; XCOFF32-NEXT:      SymbolAlignmentLog2: 0
+; XCOFF32-NEXT:      SymbolType: XTY_ER (0x0)
+; XCOFF32-NEXT:      StorageMappingClass: XMC_UA (0x4)
+; XCOFF32-NEXT:      StabInfoIndex: 0x0
+; XCOFF32-NEXT:      StabSectNum: 0x0
+; XCOFF32-NEXT:    }
+; XCOFF32-NEXT:  }
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
@@ -56,21 +56,21 @@
 ; CHECK32: .lcomm ptr,4,ptr[BS],2
 ; CHECK64: .lcomm ptr,8,ptr[BS],2
 ; CHECK:      .toc
-; CHECK-NEXT: LC0:
+; CHECK-NEXT: L..C0:
 ; CHECK-NEXT: .tc   a[TC],a[UA]
-; CHECK-NEXT: LC1:
+; CHECK-NEXT: L..C1:
 ; CHECK-NEXT: .tc   b[TC],b[UA]
-; CHECK-NEXT: LC2:
+; CHECK-NEXT: L..C2:
 ; CHECK-NEXT: .tc   c[TC],c[UA]
-; CHECK-NEXT: LC3:
+; CHECK-NEXT: L..C3:
 ; CHECK-NEXT: .tc   globa[TC],globa[RW]
-; CHECK-NEXT: LC4:
+; CHECK-NEXT: L..C4:
 ; CHECK-NEXT: .tc   ptr[TC],ptr[BS]
-; CHECK-NEXT: LC5:
+; CHECK-NEXT: L..C5:
 ; CHECK-NEXT: .tc   bar[TC],bar[DS]
-; CHECK-NEXT: LC6:
+; CHECK-NEXT: L..C6:
 ; CHECK-NEXT: .tc   foo[TC],foo[DS]
-; CHECK-NEXT: LC7:
+; CHECK-NEXT: L..C7:
 ; CHECK-NEXT: .tc   foobar[TC],foobar[DS]
 
 
diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
--- a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
@@ -140,7 +140,7 @@
 ; CHECKASM-LABEL: .test_byval_64Byte:
 
 ; ASM:         stdu 1, -112(1)
-; ASM-NEXT:    ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM-NEXT:    ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM-DAG:     ld 3, 0([[REG]])
 ; ASM-DAG:     ld 4, 8([[REG]])
 ; ASM-DAG:     ld 5, 16([[REG]])
diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
--- a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
+++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll
@@ -13,13 +13,13 @@
 }
 
 ; SMALL-LABEL: .test_load:{{$}}
-; SMALL: lwz [[REG1:[0-9]+]], LC0(2)
+; SMALL: lwz [[REG1:[0-9]+]], L..C0(2)
 ; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])
 ; SMALL: blr
 
 ; LARGE-LABEL: .test_load:{{$}}
-; LARGE: addis [[REG1:[0-9]+]], LC0@u(2)
-; LARGE: lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
+; LARGE: addis [[REG1:[0-9]+]], L..C0@u(2)
+; LARGE: lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])
 ; LARGE: blr
 
@@ -31,13 +31,13 @@
 }
 
 ; SMALL-LABEL: .test_store:{{$}}
-; SMALL: lwz [[REG1:[0-9]+]], LC1(2)
+; SMALL: lwz [[REG1:[0-9]+]], L..C1(2)
 ; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])
 ; SMALL: blr
 
 ; LARGE-LABEL: .test_store:{{$}}
-; LARGE: addis [[REG1:[0-9]+]], LC1@u(2)
-; LARGE: lwz [[REG2:[0-9]+]], LC1@l([[REG1]])
+; LARGE: addis [[REG1:[0-9]+]], L..C1@u(2)
+; LARGE: lwz [[REG2:[0-9]+]], L..C1@l([[REG1]])
 ; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])
 ; LARGE: blr
 
diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
--- a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
+++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll
@@ -13,13 +13,13 @@
 }
 
 ; SMALL-LABEL: .test_load:{{$}}
-; SMALL: ld [[REG1:[0-9]+]], LC0(2)
+; SMALL: ld [[REG1:[0-9]+]], L..C0(2)
 ; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])
 ; SMALL: blr
 
 ; LARGE-LABEL: .test_load:{{$}}
-; LARGE: addis [[REG1:[0-9]+]], LC0@u(2)
-; LARGE: ld [[REG2:[0-9]+]], LC0@l([[REG1]])
+; LARGE: addis [[REG1:[0-9]+]], L..C0@u(2)
+; LARGE: ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])
 ; LARGE: blr
 
@@ -31,13 +31,13 @@
 }
 
 ; SMALL-LABEL: .test_store:{{$}}
-; SMALL: ld [[REG1:[0-9]+]], LC1(2)
+; SMALL: ld [[REG1:[0-9]+]], L..C1(2)
 ; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])
 ; SMALL: blr
 
 ; LARGE-LABEL: .test_store:{{$}}
-; LARGE: addis [[REG1:[0-9]+]], LC1@u(2)
-; LARGE: ld [[REG2:[0-9]+]], LC1@l([[REG1]])
+; LARGE: addis [[REG1:[0-9]+]], L..C1@u(2)
+; LARGE: ld [[REG2:[0-9]+]], L..C1@l([[REG1]])
 ; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])
 ; LARGE: blr