diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1324,12 +1324,19 @@
       ExtraInfo |= InlineAsm::Extra_HasSideEffects;
     if (IA->isAlignStack())
       ExtraInfo |= InlineAsm::Extra_IsAlignStack;
+    if (Call->isConvergent())
+      ExtraInfo |= InlineAsm::Extra_IsConvergent;
     ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
 
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-            TII.get(TargetOpcode::INLINEASM))
-        .addExternalSymbol(IA->getAsmString().c_str())
-        .addImm(ExtraInfo);
+    MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+                                      TII.get(TargetOpcode::INLINEASM));
+    MIB.addExternalSymbol(IA->getAsmString().c_str());
+    MIB.addImm(ExtraInfo);
+
+    const MDNode *SrcLoc = Call->getMetadata("srcloc");
+    if (SrcLoc)
+      MIB.addMetadata(SrcLoc);
+
     return true;
   }
 
diff --git a/llvm/test/CodeGen/AArch64/asm-srcloc.ll b/llvm/test/CodeGen/AArch64/asm-srcloc.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/asm-srcloc.ll
@@ -0,0 +1,21 @@
+; RUN: llc -O0 -stop-after=finalize-isel -o - %s | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64"
+
+; CHECK-LABEL: name: foo
+; CHECK: INLINEASM {{.*}}, !0
+define void @foo() {
+  call void asm sideeffect "nowayisthisavalidinstruction", "r"(i32 0), !srcloc !0
+  ret void
+}
+
+; CHECK-LABEL: name: bar
+; CHECK: INLINEASM {{.*}}, !1
+define void @bar() {
+  call void asm sideeffect "nowayisthisavalidinstruction", ""(), !srcloc !1
+  ret void
+}
+
+!0 = !{i32 23}
+!1 = !{i32 91}