diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h --- a/clang/lib/Headers/altivec.h +++ b/clang/lib/Headers/altivec.h @@ -13651,66 +13651,46 @@ /* vec_splats */ -static __inline__ vector signed char __ATTRS_o_ai vec_splats(signed char __a) { - return (vector signed char)(__a); -} - -static __inline__ vector unsigned char __ATTRS_o_ai -vec_splats(unsigned char __a) { - return (vector unsigned char)(__a); -} - -static __inline__ vector short __ATTRS_o_ai vec_splats(short __a) { - return (vector short)(__a); -} - -static __inline__ vector unsigned short __ATTRS_o_ai -vec_splats(unsigned short __a) { - return (vector unsigned short)(__a); -} - -static __inline__ vector int __ATTRS_o_ai vec_splats(int __a) { - return (vector int)(__a); -} - -static __inline__ vector unsigned int __ATTRS_o_ai -vec_splats(unsigned int __a) { - return (vector unsigned int)(__a); -} - -#ifdef __VSX__ -static __inline__ vector signed long long __ATTRS_o_ai -vec_splats(signed long long __a) { - return (vector signed long long)(__a); -} - -static __inline__ vector unsigned long long __ATTRS_o_ai -vec_splats(unsigned long long __a) { - return (vector unsigned long long)(__a); -} - #if defined(__POWER8_VECTOR__) && defined(__powerpc64__) -static __inline__ vector signed __int128 __ATTRS_o_ai -vec_splats(signed __int128 __a) { - return (vector signed __int128)(__a); -} - -static __inline__ vector unsigned __int128 __ATTRS_o_ai -vec_splats(unsigned __int128 __a) { - return (vector unsigned __int128)(__a); -} - +#define vec_splats(N) \ + _Generic((N), unsigned char \ + : ((vector unsigned char)(N)), signed char \ + : ((vector signed char)(N)), unsigned short \ + : ((vector unsigned short)(N)), signed short \ + : ((vector signed short)(N)), unsigned int \ + : ((vector unsigned int)(N)), signed int \ + : ((vector signed int)(N)), unsigned long long \ + : ((vector unsigned long long)(N)), signed long long \ + : ((vector signed long long)(N)), unsigned __int128 \ + : ((vector unsigned __int128)(N)), signed __int128 \ + : ((vector signed __int128)(N)), float \ + : ((vector float)(N)), double \ + : ((vector double)(N))) +#elif defined(__VSX__) +#define vec_splats(N) \ + _Generic((N), unsigned char \ + : ((vector unsigned char)(N)), signed char \ + : ((vector signed char)(N)), unsigned short \ + : ((vector unsigned short)(N)), signed short \ + : ((vector signed short)(N)), unsigned int \ + : ((vector unsigned int)(N)), signed int \ + : ((vector signed int)(N)), unsigned long long \ + : ((vector unsigned long long)(N)), signed long long \ + : ((vector signed long long)(N)), float \ + : ((vector float)(N)), double \ + : ((vector double)(N))) +#else +#define vec_splats(N) \ + _Generic((N), unsigned char \ + : ((vector unsigned char)(N)), signed char \ + : ((vector signed char)(N)), unsigned short \ + : ((vector unsigned short)(N)), signed short \ + : ((vector signed short)(N)), unsigned int \ + : ((vector unsigned int)(N)), signed int \ + : ((vector signed int)(N)), float \ + : ((vector float)(N))) #endif -static __inline__ vector double __ATTRS_o_ai vec_splats(double __a) { - return (vector double)(__a); -} -#endif - -static __inline__ vector float __ATTRS_o_ai vec_splats(float __a) { - return (vector float)(__a); -} - /* ----------------------------- predicates --------------------------------- */ /* vec_all_eq */ diff --git a/clang/test/CodeGen/ppc-emmintrin.c b/clang/test/CodeGen/ppc-emmintrin.c --- a/clang/test/CodeGen/ppc-emmintrin.c +++ b/clang/test/CodeGen/ppc-emmintrin.c @@ -1,4 +1,3 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ @@ -246,7 +245,8 @@ // CHECK-LE: [[REG159:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG144]], align 4 // CHECK-LE-NEXT: [[REG160:[0-9a-zA-Z_%.]+]] = mul nsw i32 [[REG159]], 8 // CHECK-LE-NEXT: [[REG161:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG160]] to i8 -// CHECK-LE-NEXT: [[REG162:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG161]]) +// CHECK-LE-NEXT: [[REG162A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG161]], i32 0 +// CHECK-LE-NEXT: [[REG162:[0-9a-zA-Z_%.]+]] = shufflevector <16 x i8> [[REG162A]], <16 x i8> undef, <16 x i32> zeroinitializer // CHECK-LE-NEXT: store <16 x i8> [[REG162]], <16 x i8>* [[REG163:[0-9a-zA-Z_%.]+]], align 16 // CHECK-LE-NEXT: [[REG164:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG143]], align 16 // CHECK-LE-NEXT: [[REG165:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG164]] to <16 x i8> @@ -267,7 +267,8 @@ // CHECK-BE: [[REG171:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG144]], align 4 // CHECK-BE-NEXT: [[REG172:[0-9a-zA-Z_%.]+]] = mul nsw i32 [[REG171]], 8 // CHECK-BE-NEXT: [[REG173:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG172]] to i8 -// CHECK-BE-NEXT: [[REG174:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG173]]) +// CHECK-BE-NEXT: [[REG174A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG173]], i32 0 +// CHECK-BE-NEXT: [[REG174:[0-9a-zA-Z_%.]+]] = shufflevector <16 x i8> [[REG174A]], <16 x i8> undef, <16 x i32> zeroinitializer // CHECK-BE-NEXT: store <16 x i8> [[REG174]], <16 x i8>* [[REG175:[0-9a-zA-Z_%.]+]], align 16 // CHECK-BE-NEXT: [[REG176:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG143]], align 16 // CHECK-BE-NEXT: [[REG177:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG176]] to <16 x i8> @@ -425,11 +426,13 @@ // CHECK-NEXT: store <2 x double> [[REG229]], <2 x double>* [[REG231:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG232:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG230]], align 16 // CHECK-NEXT: [[REG233:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG232]], i32 0 -// CHECK-NEXT: [[REG234:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG233]]) +// CHECK-NEXT: [[REG234A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG233]], i32 0 +// CHECK-NEXT: [[REG234:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG234A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG234]], <2 x double>* [[REG235:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG236:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG231]], align 16 // CHECK-NEXT: [[REG237:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG236]], i32 0 -// CHECK-NEXT: [[REG238:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG237]]) +// CHECK-NEXT: [[REG238A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG237]], i32 0 +// CHECK-NEXT: [[REG238:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG238A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG238]], <2 x double>* [[REG239:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG240:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG235]], align 16 // CHECK-NEXT: [[REG241:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG239]], align 16 @@ -453,11 +456,13 @@ // CHECK-NEXT: store <2 x double> [[REG253]], <2 x double>* [[REG255:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG256:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG254]], align 16 // CHECK-NEXT: [[REG257:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG256]], i32 0 -// CHECK-NEXT: [[REG258:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG257]]) +// CHECK-NEXT: [[REG258A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG257]], i32 0 +// CHECK-NEXT: [[REG258:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG258A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG258]], <2 x double>* [[REG259:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG260:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG255]], align 16 // CHECK-NEXT: [[REG261:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG260]], i32 0 -// CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG261]]) +// CHECK-NEXT: [[REG262A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG261]], i32 0 +// CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG262A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG262]], <2 x double>* [[REG263:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG264:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG259]], align 16 // CHECK-NEXT: [[REG265:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG263]], align 16 @@ -481,11 +486,13 @@ // CHECK-NEXT: store <2 x double> [[REG277]], <2 x double>* [[REG279:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG280:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG278]], align 16 // CHECK-NEXT: [[REG281:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG280]], i32 0 -// CHECK-NEXT: [[REG282:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG281]]) +// CHECK-NEXT: [[REG282A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG281]], i32 0 +// CHECK-NEXT: [[REG282:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG282A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG282]], <2 x double>* [[REG283:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG284:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG279]], align 16 // CHECK-NEXT: [[REG285:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG284]], i32 0 -// CHECK-NEXT: [[REG286:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG285]]) +// CHECK-NEXT: [[REG286A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG285]], i32 0 +// CHECK-NEXT: [[REG286:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG286A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG286]], <2 x double>* [[REG287:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG288:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG283]], align 16 // CHECK-NEXT: [[REG289:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG287]], align 16 @@ -509,11 +516,13 @@ // CHECK-NEXT: store <2 x double> [[REG301]], <2 x double>* [[REG303:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG304:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG302]], align 16 // CHECK-NEXT: [[REG305:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG304]], i32 0 -// CHECK-NEXT: [[REG306:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG305]]) +// CHECK-NEXT: [[REG306A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG305]], i32 0 +// CHECK-NEXT: [[REG306:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG306A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG306]], <2 x double>* [[REG307:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG308:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG303]], align 16 // CHECK-NEXT: [[REG309:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG308]], i32 0 -// CHECK-NEXT: [[REG310:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG309]]) +// CHECK-NEXT: [[REG310A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG309]], i32 0 +// CHECK-NEXT: [[REG310:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG310A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG310]], <2 x double>* [[REG311:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG312:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG307]], align 16 // CHECK-NEXT: [[REG313:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG311]], align 16 @@ -537,11 +546,13 @@ // CHECK-NEXT: store <2 x double> [[REG325]], <2 x double>* [[REG327:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG328:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG326]], align 16 // CHECK-NEXT: [[REG329:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG328]], i32 0 -// CHECK-NEXT: [[REG330:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG329]]) +// CHECK-NEXT: [[REG330A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG329]], i32 0 +// CHECK-NEXT: [[REG330:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG330A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG330]], <2 x double>* [[REG331:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG332:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG327]], align 16 // CHECK-NEXT: [[REG333:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG332]], i32 0 -// CHECK-NEXT: [[REG334:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG333]]) +// CHECK-NEXT: [[REG334A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG333]], i32 0 +// CHECK-NEXT: [[REG334:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG334A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG334]], <2 x double>* [[REG335:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG336:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG331]], align 16 // CHECK-NEXT: [[REG337:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG335]], align 16 @@ -573,11 +584,13 @@ // CHECK-NEXT: store <2 x double> [[REG359]], <2 x double>* [[REG361:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG362:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG360]], align 16 // CHECK-NEXT: [[REG363:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG362]], i32 0 -// CHECK-NEXT: [[REG364:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG363]]) +// CHECK-NEXT: [[REG364A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG363]], i32 0 +// CHECK-NEXT: [[REG364:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG364A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG364]], <2 x double>* [[REG365:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG366:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG361]], align 16 // CHECK-NEXT: [[REG367:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG366]], i32 0 -// CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG367]]) +// CHECK-NEXT: [[REG368A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG367]], i32 0 +// CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG368A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG368]], <2 x double>* [[REG369:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG370:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG365]], align 16 // CHECK-NEXT: [[REG371:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG369]], align 16 @@ -605,11 +618,13 @@ // CHECK-NEXT: store <2 x double> [[REG386]], <2 x double>* [[REG388:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG389:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG387]], align 16 // CHECK-NEXT: [[REG390:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG389]], i32 0 -// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG390]]) +// CHECK-NEXT: [[REG391A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG390]], i32 0 +// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG391A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG391]], <2 x double>* [[REG392:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG393:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG388]], align 16 // CHECK-NEXT: [[REG394:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG393]], i32 0 -// CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG394]]) +// CHECK-NEXT: [[REG395A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG394]], i32 0 +// CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG395A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG395]], <2 x double>* [[REG396:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG392]], align 16 // CHECK-NEXT: [[REG398:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG396]], align 16 @@ -637,11 +652,13 @@ // CHECK-NEXT: store <2 x double> [[REG416]], <2 x double>* [[REG418:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG419:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG417]], align 16 // CHECK-NEXT: [[REG420:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG419]], i32 0 -// CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG420]]) +// CHECK-NEXT: [[REG421A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG420]], i32 0 +// CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG421A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG421]], <2 x double>* [[REG422:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG423:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG418]], align 16 // CHECK-NEXT: [[REG424:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG423]], i32 0 -// CHECK-NEXT: [[REG425:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG424]]) +// CHECK-NEXT: [[REG425A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG424]], i32 0 +// CHECK-NEXT: [[REG425:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG425A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG425]], <2 x double>* [[REG426:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG427:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG422]], align 16 // CHECK-NEXT: [[REG428:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG426]], align 16 @@ -665,11 +682,13 @@ // CHECK-NEXT: store <2 x double> [[REG440]], <2 x double>* [[REG442:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG443:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG441]], align 16 // CHECK-NEXT: [[REG444:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG443]], i32 0 -// CHECK-NEXT: [[REG445:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG444]]) +// CHECK-NEXT: [[REG445A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG444]], i32 0 +// CHECK-NEXT: [[REG445:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG445A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG445]], <2 x double>* [[REG446:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG447:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG442]], align 16 // CHECK-NEXT: [[REG448:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG447]], i32 0 -// CHECK-NEXT: [[REG449:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG448]]) +// CHECK-NEXT: [[REG449A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG448]], i32 0 +// CHECK-NEXT: [[REG449:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG449A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG449]], <2 x double>* [[REG450:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG451:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG446]], align 16 // CHECK-NEXT: [[REG452:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG450]], align 16 @@ -693,11 +712,13 @@ // CHECK-NEXT: store <2 x double> [[REG464]], <2 x double>* [[REG466:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG467:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG465]], align 16 // CHECK-NEXT: [[REG468:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG467]], i32 0 -// CHECK-NEXT: [[REG469:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG468]]) +// CHECK-NEXT: [[REG469A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG468]], i32 0 +// CHECK-NEXT: [[REG469:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG469A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG469]], <2 x double>* [[REG470:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG471:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG466]], align 16 // CHECK-NEXT: [[REG472:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG471]], i32 0 -// CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG472]]) +// CHECK-NEXT: [[REG473A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG472]], i32 0 +// CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG473A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG473]], <2 x double>* [[REG474:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG475:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG470]], align 16 // CHECK-NEXT: [[REG476:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG474]], align 16 @@ -733,10 +754,12 @@ // CHECK-NEXT: store <2 x double> [[REG502]], <2 x double>* [[REG504:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG505:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG503]], align 16 // CHECK-NEXT: [[REG506:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG505]], i32 0 -// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG506]]) +// CHECK-NEXT: [[REG507A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG506]], i32 0 +// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG507A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG508:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG504]], align 16 // CHECK-NEXT: [[REG509:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG508]], i32 0 -// CHECK-NEXT: [[REG510:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG509]]) +// CHECK-NEXT: [[REG510A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG509]], i32 0 +// CHECK-NEXT: [[REG510:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG510A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG511:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cmpord_pd(<2 x double> [[REG507]], <2 x double> [[REG510]]) // CHECK-NEXT: store <2 x double> [[REG511]], <2 x double>* [[REG512:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG513:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG512]], align 16 @@ -772,10 +795,12 @@ // CHECK-NEXT: store <2 x double> [[REG538]], <2 x double>* [[REG540:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG541:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG539]], align 16 // CHECK-NEXT: [[REG542:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG541]], i32 0 -// CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG542]]) +// CHECK-NEXT: [[REG543A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG542]], i32 0 +// CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG543A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG544:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG540]], align 16 // CHECK-NEXT: [[REG545:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG544]], i32 0 -// CHECK-NEXT: [[REG546:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG545]]) +// CHECK-NEXT: [[REG546A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG545]], i32 0 +// CHECK-NEXT: [[REG546:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG546A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cmpunord_pd(<2 x double> [[REG543]], <2 x double> [[REG546]]) // CHECK-NEXT: store <2 x double> [[REG547]], <2 x double>* [[REG548:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG549:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG548]], align 16 @@ -966,7 +991,8 @@ // CHECK: define available_externally <2 x double> @_mm_cvtpi32_pd(i64 [[REG633:[0-9a-zA-Z_%.]+]]) // CHECK: store i64 [[REG633]], i64* [[REG634:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG635:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG634]], align 8 -// CHECK-NEXT: [[REG636:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG635]]) +// CHECK-NEXT: [[REG636A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG635]], i32 0 +// CHECK-NEXT: [[REG636:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG636A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG637:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG636]] to <4 x i32> // CHECK-NEXT: store <4 x i32> [[REG637]], <4 x i32>* [[REG638:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG639:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG638]], align 16 @@ -1388,7 +1414,8 @@ // CHECK: store double* [[REG936]], double** [[REG937:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG938:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG937]], align 8 // CHECK-NEXT: [[REG939:[0-9a-zA-Z_%.]+]] = load double, double* [[REG938]], align 8 -// CHECK-NEXT: [[REG940:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG939]]) +// CHECK-NEXT: [[REG940A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG939]], i32 0 +// CHECK-NEXT: [[REG940:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG940A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: ret <2 x double> [[REG940]] // CHECK: define available_externally <2 x double> @_mm_loadh_pd(<2 x double> [[REG941:[0-9a-zA-Z_%.]+]], double* [[REG942:[0-9a-zA-Z_%.]+]]) @@ -1559,11 +1586,13 @@ // CHECK-NEXT: store <2 x double> [[REG1052]], <2 x double>* [[REG1054:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1055:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1053]], align 16 // CHECK-NEXT: [[REG1056:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1055]], i32 0 -// CHECK-NEXT: [[REG1057:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1056]]) +// CHECK-NEXT: [[REG1057A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1056]], i32 0 +// CHECK-NEXT: [[REG1057:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG1057A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG1057]], <2 x double>* [[REG1058:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1059:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1054]], align 16 // CHECK-NEXT: [[REG1060:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1059]], i32 0 -// CHECK-NEXT: [[REG1061:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1060]]) +// CHECK-NEXT: [[REG1061A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1060]], i32 0 +// CHECK-NEXT: [[REG1061:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG1061A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG1061]], <2 x double>* [[REG1062:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1063:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1058]], align 16 // CHECK-NEXT: [[REG1064:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1062]], align 16 @@ -1605,11 +1634,13 @@ // CHECK-NEXT: store <2 x double> [[REG1078]], <2 x double>* [[REG1080:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1081:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1079]], align 16 // CHECK-NEXT: [[REG1082:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1081]], i32 0 -// CHECK-NEXT: [[REG1083:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1082]]) +// CHECK-NEXT: [[REG1083A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1082]], i32 0 +// CHECK-NEXT: [[REG1083:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG1083A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG1083]], <2 x double>* [[REG1084:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1085:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1080]], align 16 // CHECK-NEXT: [[REG1086:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1085]], i32 0 -// CHECK-NEXT: [[REG1087:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1086]]) +// CHECK-NEXT: [[REG1087A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1086]], i32 0 +// CHECK-NEXT: [[REG1087:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG1087A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x double> [[REG1087]], <2 x double>* [[REG1088:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG1089:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1084]], align 16 // CHECK-NEXT: [[REG1090:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1088]], align 16 @@ -2058,9 +2089,7 @@ // CHECK-NEXT: ret <2 x double> [[REG1369]] // CHECK: define available_externally <2 x double> @_mm_setzero_pd() -// CHECK: [[REG1370:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 0) -// CHECK-NEXT: [[REG1371:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1370]] to <2 x double> -// CHECK-NEXT: ret <2 x double> [[REG1371]] +// CHECK: ret <2 x double> zeroinitializer // CHECK: define available_externally <2 x i64> @_mm_setzero_si128() // CHECK: store <4 x i32> zeroinitializer, <4 x i32>* [[REG1372:[0-9a-zA-Z_%.]+]], align 16 @@ -2342,7 +2371,8 @@ // CHECK: [[REG1562]]: // CHECK-NEXT: [[REG1568:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1552]], align 4 // CHECK-NEXT: [[REG1569:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1568]] to i16 -// CHECK-NEXT: [[REG1570:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1569]]) +// CHECK-NEXT: [[REG1570A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG1569]], i32 0 +// CHECK-NEXT: [[REG1570:[0-9a-zA-Z_%.]+]] = shufflevector <8 x i16> [[REG1570A]], <8 x i16> undef, <8 x i32> zeroinitializer // CHECK-NEXT: store <8 x i16> [[REG1570]], <8 x i16>* [[REG1566]], align 16 // CHECK-NEXT: br label %[[REG1567:[0-9a-zA-Z_%.]+]] @@ -2391,7 +2421,8 @@ // CHECK: [[REG1590]]: // CHECK-NEXT: [[REG1599:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1580]], align 4 -// CHECK-NEXT: [[REG1600:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1599]]) +// CHECK-NEXT: [[REG1600A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1599]], i32 0 +// CHECK-NEXT: [[REG1600:[0-9a-zA-Z_%.]+]] = shufflevector <4 x i32> [[REG1600A]], <4 x i32> undef, <4 x i32> zeroinitializer // CHECK-NEXT: store <4 x i32> [[REG1600]], <4 x i32>* [[REG1597]], align 16 // CHECK-NEXT: br label %[[REG1598:[0-9a-zA-Z_%.]+]] @@ -2441,7 +2472,8 @@ // CHECK: [[REG1620]]: // CHECK-NEXT: [[REG1630:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1610]], align 4 -// CHECK-NEXT: [[REG1631:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1630]]) +// CHECK-NEXT: [[REG1631A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1630]], i32 0 +// CHECK-NEXT: [[REG1631:[0-9a-zA-Z_%.]+]] = shufflevector <4 x i32> [[REG1631A]], <4 x i32> undef, <4 x i32> zeroinitializer // CHECK-NEXT: [[REG1632:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1631]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG1632]], <2 x i64>* [[REG1628]], align 16 // CHECK-NEXT: br label %[[REG1629:[0-9a-zA-Z_%.]+]] @@ -2585,7 +2617,8 @@ // CHECK: [[REG1716]]: // CHECK-NEXT: [[REG1721:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1709]], align 4 // CHECK-NEXT: [[REG1722:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1721]] to i16 -// CHECK-NEXT: [[REG1723:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1722]]) +// CHECK-NEXT: [[REG1723A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG1722]], i32 0 +// CHECK-NEXT: [[REG1723:[0-9a-zA-Z_%.]+]] = shufflevector <8 x i16> [[REG1723A]], <8 x i16> undef, <8 x i32> zeroinitializer // CHECK-NEXT: store <8 x i16> [[REG1723]], <8 x i16>* [[REG1710]], align 16 // CHECK-NEXT: br label %[[REG1720:[0-9a-zA-Z_%.]+]] @@ -2629,7 +2662,8 @@ // CHECK: [[REG1745]]: // CHECK-NEXT: [[REG1750:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1734]], align 4 -// CHECK-NEXT: [[REG1751:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1750]]) +// CHECK-NEXT: [[REG1751A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1750]], i32 0 +// CHECK-NEXT: [[REG1751:[0-9a-zA-Z_%.]+]] = shufflevector <4 x i32> [[REG1751A]], <4 x i32> undef, <4 x i32> zeroinitializer // CHECK-NEXT: store <4 x i32> [[REG1751]], <4 x i32>* [[REG1735]], align 16 // CHECK-NEXT: br label %[[REG1749:[0-9a-zA-Z_%.]+]] @@ -2638,7 +2672,8 @@ // CHECK: [[REG1741]]: // CHECK-NEXT: [[REG1753:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1734]], align 4 -// CHECK-NEXT: [[REG1754:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1753]]) +// CHECK-NEXT: [[REG1754A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1753]], i32 0 +// CHECK-NEXT: [[REG1754:[0-9a-zA-Z_%.]+]] = shufflevector <4 x i32> [[REG1754A]], <4 x i32> undef, <4 x i32> zeroinitializer // CHECK-NEXT: store <4 x i32> [[REG1754]], <4 x i32>* [[REG1735]], align 16 // CHECK-NEXT: br label %[[REG1752:[0-9a-zA-Z_%.]+]] @@ -2765,7 +2800,8 @@ // CHECK: [[REG1841]]: // CHECK-NEXT: [[REG1847:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1834]], align 4 // CHECK-NEXT: [[REG1848:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1847]] to i16 -// CHECK-NEXT: [[REG1849:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1848]]) +// CHECK-NEXT: [[REG1849A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG1848]], i32 0 +// CHECK-NEXT: [[REG1849:[0-9a-zA-Z_%.]+]] = shufflevector <8 x i16> [[REG1849A]], <8 x i16> undef, <8 x i32> zeroinitializer // CHECK-NEXT: store <8 x i16> [[REG1849]], <8 x i16>* [[REG1845]], align 16 // CHECK-NEXT: br label %[[REG1846:[0-9a-zA-Z_%.]+]] // CHECK: [[REG1846]]: @@ -2807,7 +2843,8 @@ // CHECK: [[REG1870]]: // CHECK-NEXT: [[REG1876:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1859]], align 4 -// CHECK-NEXT: [[REG1877:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1876]]) +// CHECK-NEXT: [[REG1877A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1876]], i32 0 +// CHECK-NEXT: [[REG1877:[0-9a-zA-Z_%.]+]] = shufflevector <4 x i32> [[REG1877A]], <4 x i32> undef, <4 x i32> zeroinitializer // CHECK-NEXT: store <4 x i32> [[REG1877]], <4 x i32>* [[REG1874]], align 16 // CHECK-NEXT: br label %[[REG1875:[0-9a-zA-Z_%.]+]] @@ -2816,7 +2853,8 @@ // CHECK: [[REG1866]]: // CHECK-NEXT: [[REG1879:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1859]], align 4 -// CHECK-NEXT: [[REG1880:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1879]]) +// CHECK-NEXT: [[REG1880A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1879]], i32 0 +// CHECK-NEXT: [[REG1880:[0-9a-zA-Z_%.]+]] = shufflevector <4 x i32> [[REG1880A]], <4 x i32> undef, <4 x i32> zeroinitializer // CHECK-NEXT: store <4 x i32> [[REG1880]], <4 x i32>* [[REG1874]], align 16 // CHECK-NEXT: br label %[[REG1878:[0-9a-zA-Z_%.]+]] @@ -2862,7 +2900,8 @@ // CHECK: [[REG1901]]: // CHECK-NEXT: [[REG1908:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1890]], align 4 // CHECK-NEXT: [[REG1909:[0-9a-zA-Z_%.]+]] = sext i32 [[REG1908]] to i64 -// CHECK-NEXT: [[REG1910:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG1909]]) +// CHECK-NEXT: [[REG1910A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG1909]], i32 0 +// CHECK-NEXT: [[REG1910:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG1910A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x i64> [[REG1910]], <2 x i64>* [[REG1906]], align 16 // CHECK-NEXT: br label %[[REG1907:[0-9a-zA-Z_%.]+]] @@ -2871,7 +2910,8 @@ // CHECK: [[REG1897]]: // CHECK-NEXT: [[REG1912:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1890]], align 4 -// CHECK-NEXT: [[REG1913:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1912]]) +// CHECK-NEXT: [[REG1913A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1912]], i32 0 +// CHECK-NEXT: [[REG1913:[0-9a-zA-Z_%.]+]] = shufflevector <4 x i32> [[REG1913A]], <4 x i32> undef, <4 x i32> zeroinitializer // CHECK-NEXT: [[REG1914:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1913]] to <2 x i64> // CHECK-NEXT: store <2 x i64> [[REG1914]], <2 x i64>* [[REG1906]], align 16 // CHECK-NEXT: br label %[[REG1911:[0-9a-zA-Z_%.]+]] diff --git a/clang/test/CodeGen/ppc-mmintrin.c b/clang/test/CodeGen/ppc-mmintrin.c --- a/clang/test/CodeGen/ppc-mmintrin.c +++ b/clang/test/CodeGen/ppc-mmintrin.c @@ -1,4 +1,3 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -DNO_WARN_X86_INTRINSICS %s \ @@ -34,11 +33,13 @@ // CHECK: define available_externally i64 @_mm_add_pi32 -// CHECK-P9: [[REG1:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-P9: [[REG1A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-P9-NEXT: [[REG1:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG1A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-P9-NEXT: [[REG2:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG2]], <4 x i32>* [[REG3:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG4:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-P9-NEXT: [[REG5:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-P9-NEXT: [[REG5A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-P9-NEXT: [[REG5:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG5A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-P9-NEXT: [[REG6:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG5]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG6]], <4 x i32>* [[REG7:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG8:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG3]], align 16 @@ -62,10 +63,12 @@ // CHECK-P8-NEXT: add nsw i32 [[REG20]], [[REG22]] // CHECK: define available_externally i64 @_mm_add_pi16 -// CHECK: [[REG23:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG23A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG23:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG23A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG23]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG24]], <8 x i16>* [[REG25:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG26:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG26A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG26A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG26]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* [[REG28:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG25]], align 16 @@ -73,10 +76,12 @@ // CHECK-NEXT: call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> [[REG29]], <8 x i16> [[REG30]]) // CHECK: define available_externally i64 @_mm_add_pi8 -// CHECK: [[REG31:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG31A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG31A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG32:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG31]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG32]], <16 x i8>* [[REG33:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG34:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG34A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG34:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG34A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG35:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG34]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG35]], <16 x i8>* [[REG36:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG33]], align 16 @@ -84,10 +89,12 @@ // CHECK-NEXT: call <16 x i8> @vec_add(signed char vector[16], signed char vector[16])(<16 x i8> [[REG37]], <16 x i8> [[REG38]]) // CHECK: define available_externally i64 @_mm_adds_pu16 -// CHECK: [[REG39:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG39A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG39:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG39A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG40:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG39]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG40]], <8 x i16>* [[REG41:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG42:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG42A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG42:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG42A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG43:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG42]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG43]], <8 x i16>* [[REG44:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG41]], align 16 @@ -95,10 +102,12 @@ // CHECK-NEXT: call <8 x i16> @vec_adds(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG45]], <8 x i16> [[REG46]]) // CHECK: define available_externally i64 @_mm_adds_pu8 -// CHECK: [[REG47:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG47A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG47:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG47A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG48:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG47]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG48]], <16 x i8>* [[REG49:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG50:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG50A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG50:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG50A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG51:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG50]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG51]], <16 x i8>* [[REG52:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG53:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG49]], align 16 @@ -106,10 +115,12 @@ // CHECK-NEXT: call <16 x i8> @vec_adds(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG53]], <16 x i8> [[REG54]]) // CHECK: define available_externally i64 @_mm_adds_pi16 -// CHECK: [[REG55:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG55A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG55:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG55A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG56:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG55]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG56]], <8 x i16>* [[REG57:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG58:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG58A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG58:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG58A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG59:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG58]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG59]], <8 x i16>* [[REG60:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG61:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG57]], align 16 @@ -117,10 +128,12 @@ // CHECK-NEXT: call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> [[REG61]], <8 x i16> [[REG62]]) // CHECK: define available_externally i64 @_mm_adds_pi8 -// CHECK: [[REG63:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG63A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG63:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG63A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG64:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG63]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG64]], <16 x i8>* [[REG65:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG66:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats +// CHECK: [[REG66A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG66:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG66A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG67:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG66]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG67]], <16 x i8>* [[REG68:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG69:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG65]], align 16 @@ -182,10 +195,12 @@ // CHECK: define available_externally i64 @_mm_cmpeq_pi32 -// CHECK-P9: [[REG78:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-P9: [[REG78A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-P9-NEXT: [[REG78:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG78A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-P9-NEXT: [[REG79:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG78]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG79]], <4 x i32>* [[REG80:[0-9a-zA-Z_%.]+]] -// CHECK-P9: [[REG81:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-P9: [[REG81A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-P9-NEXT: [[REG81:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG81A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-P9-NEXT: [[REG82:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG81]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG82]], <4 x i32>* [[REG83:[0-9a-zA-Z_%.]+]] // CHECK-P9-NEXT: [[REG84:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG80]] @@ -201,10 +216,12 @@ // CHECK-P8: store i32 {{[0-9a-zA-Z_%.]+}}, i32* {{[0-9a-zA-Z_%.]+}} // CHECK: define available_externally i64 @_mm_cmpeq_pi16 -// CHECK: [[REG88:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG88A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG88:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG88A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG89:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG88]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG89]], <8 x i16>* [[REG90:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG91:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG91A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG91A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG92:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG91]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG92]], <8 x i16>* [[REG93:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG94:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG90]], align 16 @@ -219,10 +236,12 @@ // CHECK: define available_externally i64 @_mm_cmpgt_pi32 -// CHECK-P9: [[REG98:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-P9: [[REG98A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-P9-NEXT: [[REG98:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG98A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-P9-NEXT: [[REG99:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG98]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG99]], <4 x i32>* [[REG100:[0-9a-zA-Z_%.]+]] -// CHECK-P9: [[REG101:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-P9: [[REG101A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-P9-NEXT: [[REG101:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG101A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-P9-NEXT: [[REG102:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG101]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG102]], <4 x i32>* [[REG103:[0-9a-zA-Z_%.]+]] // CHECK-P9-NEXT: [[REG104:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG100]] @@ -238,10 +257,12 @@ // CHECK-P8: store i32 {{[0-9a-zA-Z_%.]+}}, i32* {{[0-9a-zA-Z_%.]+}} // CHECK: define available_externally i64 @_mm_cmpgt_pi16 -// CHECK: [[REG108:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG108A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG108:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG108A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG109:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG108]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG109]], <8 x i16>* [[REG110:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG111:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG111A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG111:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG111A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG112:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG111]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG112]], <8 x i16>* [[REG113:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG114:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG110]] @@ -249,10 +270,12 @@ // CHECK-NEXT: call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> [[REG114]], <8 x i16> [[REG115]]) // CHECK: define available_externally i64 @_mm_cmpgt_pi8 -// CHECK: [[REG116:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG116A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG116:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG116A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG117:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG116]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG117]], <16 x i8>* [[REG118:[0-9a-zA-Z_%.]+]] -// CHECK: [[REG119:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG119A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG119:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG119A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG120:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG119]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG120]], <16 x i8>* [[REG121:[0-9a-zA-Z_%.]+]] // CHECK-NEXT: [[REG122:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG118]] @@ -428,10 +451,12 @@ // CHECK: define available_externally i64 @_mm_madd_pi16 // CHECK: store <4 x i32> zeroinitializer, <4 x i32>* [[REG149:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG150:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG150A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG150:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG150A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG151:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG150]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG151]], <8 x i16>* [[REG152:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG153:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG153A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG153:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG153A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG154:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG153]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG154]], <8 x i16>* [[REG155:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG156:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG152]], align 16 @@ -455,10 +480,12 @@ // CHECK: define available_externally i64 @_mm_mulhi_pi16 // CHECK-BE: store <16 x i8> , <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-LE: store <16 x i8> , <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 -// CHECK: [[REG161:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG161A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG161:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG161A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK: store <8 x i16> {{[0-9a-zA-Z_%.]+}}, <8 x i16>* [[REG162:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG163:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG164:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-NEXT: [[REG164A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG164:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG164A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG165:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG164]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG165]], <8 x i16>* [[REG166:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG167:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG162]], align 16 @@ -475,11 +502,13 @@ // CHECK-NEXT: call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG175]], <4 x i32> [[REG176]], <16 x i8> [[REG177]]) // CHECK: define available_externally i64 @_mm_mullo_pi16 -// CHECK: [[REG178:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG178A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG178:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG178A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG179:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG178]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG179]], <8 x i16>* [[REG180:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG181:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG182:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-NEXT: [[REG182A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG182:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG182A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG183:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG182]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG183]], <8 x i16>* [[REG184:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG185:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG180]], align 16 @@ -635,8 +664,9 @@ // CHECK: define available_externally i64 @_mm_set1_pi16 // CHECK-P9: [[REG247:[0-9a-zA-Z_%.]+]] = load i16, i16* {{[0-9a-zA-Z_%.]+}}, align 2 -// CHECK-P9-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext [[REG247]]) -// CHECK-P9-NEXT: store <8 x i16> %call, <8 x i16>* [[REG249:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-P9-NEXT: [[REG248A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG247]], i32 0 +// CHECK-P9-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = shufflevector <8 x i16> [[REG248A]], <8 x i16> undef, <8 x i32> zeroinitializer +// CHECK-P9-NEXT: store <8 x i16> [[REG248]], <8 x i16>* [[REG249:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG250:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG249:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG251:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG250]] to <2 x i64> // CHECK-P9-NEXT: [[REG252:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG251]], i32 0 @@ -656,10 +686,11 @@ // CHECK-P8-NEXT: store i16 [[REG258]], i16* [[REG259]], align 2 // CHECK: define available_externally i64 @_mm_set1_pi8 -// CHECK: [[REG260:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(signed char)(i8 signext {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG260A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG260:[0-9a-zA-Z_%.]+]] = shufflevector <16 x i8> [[REG260A]], <16 x i8> undef, <16 x i32> zeroinitializer // CHECK-NEXT: store <16 x i8> [[REG260]], <16 x i8>* [[REG261:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG261:[0-9a-zA-Z_%.]+]], align 16 -// CHECK-NEXT: [[REG263:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> %1 to <2 x i64> +// CHECK-NEXT: [[REG263:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> {{[0-9a-zA-Z_%.]+}} to <2 x i64> // CHECK-NEXT: [[REG264:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG263]], i32 0 // CHECK-NEXT: ret i64 [[REG264]] @@ -715,9 +746,9 @@ // CHECK: [[REG271:[0-9a-zA-Z_%.]+]] = icmp ule i64 {{[0-9a-zA-Z_%.]+}}, 15 // CHECK-NEXT: br i1 [[REG271]], label %[[REG272:[0-9a-zA-Z_.]+]], label %[[REG273:[0-9a-zA-Z_.]+]] // CHECK: [[REG272]] -// CHECK: call <2 x i64> @vec_splats(unsigned long long) +// CHECK: insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 // CHECK: trunc i64 {{[0-9a-zA-Z_%.]+}} to i16 -// CHECK-NEXT: call <8 x i16> @vec_splats(unsigned short) +// CHECK-NEXT: insertelement <8 x i16> undef, i16 {{[0-9a-zA-Z_%.]+}}, i32 0 // CHECK: call <8 x i16> @vec_sl(short vector[8], unsigned short vector[8]) // CHECK: store i64 [[REG274:[0-9a-zA-Z_%.]+]], i64* [[REG275:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: br label %[[REG276:[0-9a-zA-Z_%.]+]] @@ -828,12 +859,14 @@ // CHECK: [[REG313:[0-9a-zA-Z_%.]+]] = icmp ule i64 {{[0-9a-zA-Z_%.]+}}, 15 // CHECK-NEXT: br i1 [[REG313]], label %[[REG314:[0-9a-zA-Z_%.]+]], label %[[REG315:[0-9a-zA-Z_%.]+]] // CHECK: [[REG314]] -// CHECK: [[REG316:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG316A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG316:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG316A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG317:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG316]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG317]], <8 x i16>* [[REG318:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG319:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG320:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG319]] to i16 -// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG320]]) +// CHECK-NEXT: [[REG321A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG320]], i32 0 +// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = shufflevector <8 x i16> [[REG321A]], <8 x i16> undef, <8 x i32> zeroinitializer // CHECK-NEXT: store <8 x i16> [[REG321]], <8 x i16>* [[REG322:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG323:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG318]], align 16 // CHECK-NEXT: [[REG324:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG322]], align 16 @@ -919,12 +952,14 @@ // CHECK: [[REG349:[0-9a-zA-Z_%.]+]] = icmp ule i64 {{[0-9a-zA-Z_%.]+}}, 15 // CHECK-NEXT: br i1 [[REG349]], label %[[REG350:[0-9a-zA-Z_%.]+]], label %[[REG351:[0-9a-zA-Z_%.]+]] // CHECK: [[REG350]] -// CHECK: [[REG352:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG352A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG352:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG352A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG353:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG352]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG353]], <8 x i16>* [[REG354:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG355:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG356:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG355]] to i16 -// CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG356]]) +// CHECK-NEXT: [[REG357A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG356]], i32 0 +// CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = shufflevector <8 x i16> [[REG357A]], <8 x i16> undef, <8 x i32> zeroinitializer // CHECK-NEXT: store <8 x i16> [[REG357]], <8 x i16>* [[REG358:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG359:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG354]], align 16 // CHECK-NEXT: [[REG360:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG358]], align 16 @@ -1015,10 +1050,12 @@ // CHECK-P8-NEXT: [[REG382:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG381]], align 4 // CHECK-P8-NEXT: sub nsw i32 [[REG380]], [[REG382]] -// CHECK-P9: [[REG383:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK-P9: [[REG383A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-P9-NEXT: [[REG383:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG383A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-P9-NEXT: [[REG384:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG383]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG384]], <4 x i32>* [[REG385:[0-9a-zA-Z_%.]+]], align 16 -// CHECK-P9: [[REG386:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK-P9: [[REG386A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-P9-NEXT: [[REG386:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG386A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-P9-NEXT: [[REG387:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG386]] to <4 x i32> // CHECK-P9-NEXT: store <4 x i32> [[REG387]], <4 x i32>* [[REG388:[0-9a-zA-Z_%.]+]], align 16 // CHECK-P9-NEXT: [[REG389:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG385]], align 16 @@ -1026,10 +1063,12 @@ // CHECK-P9-NEXT: call <4 x i32> @vec_sub(int vector[4], int vector[4])(<4 x i32> [[REG389]], <4 x i32> [[REG390]]) // CHECK: define available_externally i64 @_mm_sub_pi16 -// CHECK: [[REG391:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG391A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG391A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG392:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG391]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG392]], <8 x i16>* [[REG393:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG394:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG394A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG394:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG394A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG394]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG395]], <8 x i16>* [[REG396:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG393]], align 16 @@ -1037,10 +1076,12 @@ // CHECK-NEXT: call <8 x i16> @vec_sub(short vector[8], short vector[8])(<8 x i16> [[REG397]], <8 x i16> [[REG398]]) // CHECK: define available_externally i64 @_mm_sub_pi8 -// CHECK: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG399A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG399:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG399A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG400:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG399]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG400]], <16 x i8>* [[REG401:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG402:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG402A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG402:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG402A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG403:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG402]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG403]], <16 x i8>* [[REG404:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG405:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG401]], align 16 @@ -1048,10 +1089,12 @@ // CHECK-NEXT: call <16 x i8> @vec_sub(signed char vector[16], signed char vector[16])(<16 x i8> [[REG405]], <16 x i8> [[REG406]]) // CHECK: define available_externally i64 @_mm_subs_pi16 -// CHECK: [[REG407:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG407A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG407:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG407A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG408:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG407]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG408]], <8 x i16>* [[REG409:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG410:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG410A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG410:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG410A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG411:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG410]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG411]], <8 x i16>* [[REG412:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG413:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG409]], align 16 @@ -1059,10 +1102,12 @@ // CHECK-NEXT: call <8 x i16> @vec_subs(short vector[8], short vector[8])(<8 x i16> [[REG413]], <8 x i16> [[REG414]]) // CHECK: define available_externally i64 @_mm_subs_pi8 -// CHECK: [[REG415:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG415A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG415:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG415A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG416:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG415]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG416]], <16 x i8>* [[REG417:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG418:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG418A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG418:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG418A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG419:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG418]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG419]], <16 x i8>* [[REG420:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG417]], align 16 @@ -1070,10 +1115,12 @@ // CHECK-NEXT: call <16 x i8> @vec_subs(signed char vector[16], signed char vector[16])(<16 x i8> [[REG421]], <16 x i8> [[REG422]]) // CHECK: define available_externally i64 @_mm_subs_pu16 -// CHECK: [[REG423:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG423A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG423:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG423A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG424:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG423]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG424]], <8 x i16>* [[REG425:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG426:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG426A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG426:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG426A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG427:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG426]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG427]], <8 x i16>* [[REG428:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG425]], align 16 @@ -1081,10 +1128,12 @@ // CHECK-NEXT: call <8 x i16> @vec_subs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG429]], <8 x i16> [[REG430]]) // CHECK: define available_externally i64 @_mm_subs_pu8 -// CHECK: [[REG431:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG431A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG431:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG431A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG432:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG431]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG432]], <16 x i8>* [[REG433:[0-9a-zA-Z_%.]+]], align 16 -// CHECK: [[REG434:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}}) +// CHECK: [[REG434A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG434:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG434A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG435:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG434]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG435]], <16 x i8>* [[REG436:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG437:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG433]], align 16 @@ -1175,11 +1224,13 @@ // CHECK-NEXT: store i16 [[REG465]], i16* [[REG466]], align 2 // CHECK: define available_externally i64 @_mm_unpackhi_pi8 -// CHECK: [[REG467:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG467A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG467:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG467A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG468:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG467]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG468]], <16 x i8>* [[REG469:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG470:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG471:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-NEXT: [[REG471A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG471:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG471A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG472:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG471]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG472]], <16 x i8>* [[REG473:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG474:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG469]], align 16 @@ -1215,11 +1266,13 @@ // CHECK-NEXT: store i16 [[REG492]], i16* [[REG493]], align 2 // CHECK: define available_externally i64 @_mm_unpacklo_pi8 -// CHECK: [[REG494:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG494A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG494:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG494A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG495:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG494]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG495]], <16 x i8>* [[REG496:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG497:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG498:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK-NEXT: [[REG498A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG498:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG498A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG499:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG498]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG499]], <16 x i8>* [[REG500:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG501:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG496]], align 16 diff --git a/clang/test/CodeGen/ppc-pmmintrin.c b/clang/test/CodeGen/ppc-pmmintrin.c --- a/clang/test/CodeGen/ppc-pmmintrin.c +++ b/clang/test/CodeGen/ppc-pmmintrin.c @@ -1,4 +1,3 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-gnu-linux -mcpu=pwr8 -DNO_MM_MALLOC -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ @@ -122,7 +121,8 @@ // CHECK: store double* [[REG81]], double** [[REG82:[0-9a-zA-Z_%.]+]], align 8 // CHECK-NEXT: [[REG83:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG82]], align 8 // CHECK-NEXT: [[REG84:[0-9a-zA-Z_%.]+]] = load double, double* [[REG83]], align 8 -// CHECK-NEXT: [[REG85:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG84]]) +// CHECK-NEXT: [[REG85A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG84]], i32 0 +// CHECK-NEXT: [[REG85:[0-9a-zA-Z_%.]+]] = shufflevector <2 x double> [[REG85A]], <2 x double> undef, <2 x i32> zeroinitializer // CHECK-NEXT: ret <2 x double> [[REG85]] // CHECK: define available_externally <2 x double> @_mm_movedup_pd(<2 x double> [[REG86:[0-9a-zA-Z_%.]+]]) diff --git a/clang/test/CodeGen/ppc-smmintrin.c b/clang/test/CodeGen/ppc-smmintrin.c --- a/clang/test/CodeGen/ppc-smmintrin.c +++ b/clang/test/CodeGen/ppc-smmintrin.c @@ -1,4 +1,3 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ @@ -75,7 +74,8 @@ // CHECK-NEXT: store i32 [[REG40]], i32* [[REG43:[0-9a-zA-Z_%.]+]], align 4 // CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG43]], align 4 // CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG44]] to i8 -// CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(signed char)(i8 signext [[REG45]]) +// CHECK-NEXT: [[REG45A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG45]], i32 0 +// CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = shufflevector <16 x i8> [[REG45A]], <16 x i8> undef, <16 x i32> zeroinitializer // CHECK-NEXT: store <16 x i8> [[REG46]], <16 x i8>* [[REG47:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG48:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG47]], align 16 // CHECK-NEXT: [[REG49:[0-9a-zA-Z_%.]+]] = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> [[REG48]]) @@ -101,12 +101,10 @@ // CHECK: store <2 x i64> [[REG62]], <2 x i64>* [[REG65:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG63]], <2 x i64>* [[REG66:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG64]], <2 x i64>* [[REG67:[0-9a-zA-Z_%.]+]], align 16 -// CHECK-NEXT: [[REG68:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext 7) -// CHECK-NEXT: store <16 x i8> [[REG68]], <16 x i8>* [[REG69:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <16 x i8> , <16 x i8>* [[REG68:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG70:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG67]], align 16 // CHECK-NEXT: [[REG71:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG70]] to <16 x i8> -// CHECK-NEXT: [[REG72:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG69]], align 16 -// CHECK-NEXT: [[REG73:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sra(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG71]], <16 x i8> [[REG72]]) +// CHECK-NEXT: [[REG73:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sra(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG71]], <16 x i8> ) // CHECK-NEXT: store <16 x i8> [[REG73]], <16 x i8>* [[REG74:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG75:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG65]], align 16 // CHECK-NEXT: [[REG76:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG75]] to <16 x i8> diff --git a/clang/test/CodeGen/ppc-tmmintrin.c b/clang/test/CodeGen/ppc-tmmintrin.c --- a/clang/test/CodeGen/ppc-tmmintrin.c +++ b/clang/test/CodeGen/ppc-tmmintrin.c @@ -1,4 +1,3 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-gnu-linux -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ @@ -156,7 +155,8 @@ // CHECK-NEXT: [[REG88:[0-9a-zA-Z_%.]+]] = sub i32 [[REG87]], 16 // CHECK-NEXT: [[REG89:[0-9a-zA-Z_%.]+]] = mul i32 [[REG88]], 8 // CHECK-NEXT: [[REG90:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG89]] to i8 -// CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG90]]) +// CHECK-NEXT: [[REG91A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG90]], i32 0 +// CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]] = shufflevector <16 x i8> [[REG91A]], <16 x i8> undef, <16 x i32> zeroinitializer // CHECK-NEXT: store <16 x i8> [[REG91]], <16 x i8>* [[REG92:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG93:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG65]], align 16 // CHECK-NEXT: [[REG94:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG93]] to <16 x i8> @@ -173,7 +173,8 @@ // CHECK-NEXT: [[REG100:[0-9a-zA-Z_%.]+]] = mul i32 [[REG99]], 8 // CHECK-BE: [[REG101:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG100]] to i8 -// CHECK-BE: [[REG102:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG101]]) +// CHECK-BE: [[REG102A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG101]], i32 0 +// CHECK-BE-NEXT: [[REG102:[0-9a-zA-Z_%.]+]] = shufflevector <16 x i8> [[REG102A]], <16 x i8> undef, <16 x i32> zeroinitializer // CHECK-BE: mul i32 {{[0-9a-zA-Z_%.]+}}, 8 // CHECK-BE: call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16]) // CHECK-BE: call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16]) @@ -184,7 +185,6 @@ // CHECK-LE: [[REG105:[0-9a-zA-Z_%.]+]] = mul i32 {{[0-9a-zA-Z_%.]+}}, 8 // CHECK-LE-NEXT: trunc i32 [[REG105]] to i8 -// CHECK-LE: call <16 x i8> @vec_splats(unsigned char) // CHECK-LE: call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16]) // CHECK-LE: call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16]) // CHECK-LE: [[REG106:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_or(unsigned char vector[16], unsigned char vector[16]) @@ -834,8 +834,7 @@ // CHECK: define available_externally <2 x i64> @_mm_maddubs_epi16(<2 x i64> [[REG645:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG646:[0-9a-zA-Z_%.]+]]) // CHECK: store <2 x i64> [[REG645]], <2 x i64>* [[REG647:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: store <2 x i64> [[REG646]], <2 x i64>* [[REG648:[0-9a-zA-Z_%.]+]], align 16 -// CHECK-NEXT: [[REG649:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext 255) -// CHECK-NEXT: store <8 x i16> [[REG649]], <8 x i16>* [[REG650:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <8 x i16> , <8 x i16>* [[REG650:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG651:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG647]], align 16 // CHECK-NEXT: [[REG652:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG651]] to <16 x i8> // CHECK-NEXT: [[REG653:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> [[REG652]]) @@ -895,11 +894,9 @@ // CHECK-NEXT: [[REG698:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG697]] to <16 x i8> // CHECK-NEXT: [[REG699:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> [[REG698]]) // CHECK-NEXT: store <8 x i16> [[REG699]], <8 x i16>* [[REG696]], align 16 -// CHECK-NEXT: [[REG700:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext 255) -// CHECK-NEXT: store <8 x i16> [[REG700]], <8 x i16>* [[REG701:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <8 x i16> , <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG702:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG696]], align 16 -// CHECK-NEXT: [[REG703:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG701]], align 16 -// CHECK-NEXT: [[REG704:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> [[REG702]], <8 x i16> [[REG703]]) +// CHECK-NEXT: [[REG704:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> [[REG702]], <8 x i16> ) // CHECK-NEXT: store <8 x i16> [[REG704]], <8 x i16>* [[REG696]], align 16 // CHECK-NEXT: [[REG705:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG691]], align 8 // CHECK-NEXT: [[REG706:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG705]], i32 0 @@ -971,33 +968,25 @@ // CHECK-NEXT: [[REG756:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG754]], align 16 // CHECK-NEXT: [[REG757:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> [[REG755]], <4 x i32> [[REG756]]) // CHECK-NEXT: store <4 x i32> [[REG757]], <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG758:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext 14) -// CHECK-NEXT: store <4 x i32> [[REG758]], <4 x i32>* [[REG759:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <4 x i32> , <4 x i32>* [[REG759:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG760:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 -// CHECK-NEXT: [[REG761:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG759]], align 16 -// CHECK-NEXT: [[REG762:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG760]], <4 x i32> [[REG761]]) +// CHECK-NEXT: [[REG762:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG760]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG762]], <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG763:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG764:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG759]], align 16 -// CHECK-NEXT: [[REG765:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG763]], <4 x i32> [[REG764]]) +// CHECK-NEXT: [[REG765:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG763]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG765]], <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG766:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 1) -// CHECK-NEXT: store <4 x i32> [[REG766]], <4 x i32>* [[REG767:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <4 x i32> , <4 x i32>* [[REG767:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG768:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 -// CHECK-NEXT: [[REG769:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16 -// CHECK-NEXT: [[REG770:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG768]], <4 x i32> [[REG769]]) +// CHECK-NEXT: [[REG770:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG768]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG770]], <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG771:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 -// CHECK-NEXT: [[REG772:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16 -// CHECK-NEXT: [[REG773:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG771]], <4 x i32> [[REG772]]) +// CHECK-NEXT: [[REG773:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG771]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG773]], <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG774:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG775:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16 -// CHECK-NEXT: [[REG776:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG774]], <4 x i32> [[REG775]]) +// CHECK-NEXT: [[REG776:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG774]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG776]], <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG777:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 -// CHECK-NEXT: [[REG778:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16 -// CHECK-NEXT: [[REG779:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG777]], <4 x i32> [[REG778]]) +// CHECK-NEXT: [[REG779:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG777]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG779]], <4 x i32>* [[REG744]], align 16 // CHECK-NEXT: [[REG780:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16 // CHECK-NEXT: [[REG781:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16 @@ -1036,21 +1025,16 @@ // CHECK-NEXT: [[REG811:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG806]], align 16 // CHECK-NEXT: [[REG812:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> [[REG810]], <4 x i32> [[REG811]]) // CHECK-NEXT: store <4 x i32> [[REG812]], <4 x i32>* [[REG795]], align 16 -// CHECK-NEXT: [[REG813:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext 14) -// CHECK-NEXT: store <4 x i32> [[REG813]], <4 x i32>* [[REG814:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <4 x i32> , <4 x i32>* [[REG814:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG815:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 -// CHECK-NEXT: [[REG816:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG814]], align 16 -// CHECK-NEXT: [[REG817:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG815]], <4 x i32> [[REG816]]) +// CHECK-NEXT: [[REG817:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG815]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG817]], <4 x i32>* [[REG795]], align 16 -// CHECK-NEXT: [[REG818:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 1) -// CHECK-NEXT: store <4 x i32> [[REG818]], <4 x i32>* [[REG819:[0-9a-zA-Z_%.]+]], align 16 +// CHECK-NEXT: store <4 x i32> , <4 x i32>* [[REG819:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG820:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 -// CHECK-NEXT: [[REG821:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG819]], align 16 -// CHECK-NEXT: [[REG822:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG820]], <4 x i32> [[REG821]]) +// CHECK-NEXT: [[REG822:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG820]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG822]], <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG823:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 -// CHECK-NEXT: [[REG824:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG819]], align 16 -// CHECK-NEXT: [[REG825:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG823]], <4 x i32> [[REG824]]) +// CHECK-NEXT: [[REG825:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG823]], <4 x i32> ) // CHECK-NEXT: store <4 x i32> [[REG825]], <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG826:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16 // CHECK-NEXT: [[REG827:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG806]], align 16 diff --git a/clang/test/CodeGen/ppc-xmmintrin.c b/clang/test/CodeGen/ppc-xmmintrin.c --- a/clang/test/CodeGen/ppc-xmmintrin.c +++ b/clang/test/CodeGen/ppc-xmmintrin.c @@ -1,4 +1,3 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ @@ -66,11 +65,13 @@ // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG25:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG25]]) +// CHECK-NEXT: [[REG26A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG25]], i32 0 +// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG26A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG26]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG28]]) +// CHECK-NEXT: [[REG29A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG28]], i32 0 +// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG29A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG29]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG30]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -86,11 +87,13 @@ // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG37]]) +// CHECK-NEXT: [[REG38A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG37]], i32 0 +// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG38A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG39:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG38]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG39]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG40:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG40]]) +// CHECK-NEXT: [[REG41A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG40]], i32 0 +// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG41A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG42:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG41]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG42]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG43:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -965,7 +968,8 @@ // CHECK-NEXT: ret <4 x float> [[REG472]] // CHECK: define available_externally <4 x float> @_mm_loadh_pi -// CHECK: [[REG473:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG473A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG473A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x i64> [[REG473]], <2 x i64>* [[REG474:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG475:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG474]], align 16 // CHECK-NEXT: [[REG476:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG475]], i32 1 @@ -977,7 +981,8 @@ // CHECK-NEXT: ret <4 x float> [[REG481]] // CHECK: define available_externally <4 x float> @_mm_loadl_pi -// CHECK: [[REG482:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long) +// CHECK: [[REG482A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0 +// CHECK-NEXT: [[REG482:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG482A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x i64> [[REG482]], <2 x i64>* [[REG483:[0-9a-zA-Z_%.]+]], align 16 // CHECK-NEXT: [[REG484:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG483]], align 16 // CHECK-NEXT: [[REG485:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG484]], i32 0 @@ -1080,11 +1085,13 @@ // CHECK: define available_externally i64 @_mm_max_pi16 // CHECK: [[REG530:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG531:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG530]]) +// CHECK-NEXT: [[REG531A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG530]], i32 0 +// CHECK-NEXT: [[REG531:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG531A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG532:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG531]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG532]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG533:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG534:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG533]]) +// CHECK-NEXT: [[REG534A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG533]], i32 0 +// CHECK-NEXT: [[REG534:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG534A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG535:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG534]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG535]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG536:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -1103,11 +1110,13 @@ // CHECK: define available_externally i64 @_mm_max_pu8 // CHECK: [[REG546:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG546]]) +// CHECK-NEXT: [[REG547A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG546]], i32 0 +// CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG547A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG548:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG547]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG548]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG549:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG549]]) +// CHECK-NEXT: [[REG550A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG549]], i32 0 +// CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG550A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG551:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG550]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG551]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG552:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -1176,11 +1185,13 @@ // CHECK: define available_externally i64 @_mm_min_pi16 // CHECK: [[REG581:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG582:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG581]]) +// CHECK-NEXT: [[REG582A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG581]], i32 0 +// CHECK-NEXT: [[REG582:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG582A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG583:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG582]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG583]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG584:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG585:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG584]]) +// CHECK-NEXT: [[REG585A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG584]], i32 0 +// CHECK-NEXT: [[REG585:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG585A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG586:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG585]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG586]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG587:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -1199,11 +1210,13 @@ // CHECK: define available_externally i64 @_mm_min_pu8 // CHECK: [[REG597:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG598:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG597]]) +// CHECK-NEXT: [[REG598A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG597]], i32 0 +// CHECK-NEXT: [[REG598:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG598A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG599:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG598]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG599]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG600:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: [[REG601:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG600]]) +// CHECK-NEXT: [[REG601A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG600]], i32 0 +// CHECK-NEXT: [[REG601:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG601A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG602:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG601]] to <16 x i8> // CHECK-NEXT: store <16 x i8> [[REG602]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG603:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -1390,11 +1403,13 @@ // CHECK-LE-NEXT: store <16 x i8> , <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-BE-NEXT: store <16 x i8> , <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG688:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG686]], align 8 -// CHECK-NEXT: [[REG689:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG688]]) +// CHECK-NEXT: [[REG689A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG688]], i32 0 +// CHECK-NEXT: [[REG689:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG689A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG690:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG689]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG690]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG691:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG687]], align 8 -// CHECK-NEXT: [[REG692:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG691]]) +// CHECK-NEXT: [[REG692A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG691]], i32 0 +// CHECK-NEXT: [[REG692:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG692A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: [[REG693:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG692]] to <8 x i16> // CHECK-NEXT: store <8 x i16> [[REG693]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG694:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16 @@ -1706,10 +1721,12 @@ // CHECK-NEXT: store i16 [[REG865]], i16* [[REG867]] // CHECK-NEXT: [[REG868:[0-9a-zA-Z_%.]+]] = bitcast {{[0-9a-zA-Z_%.]+}}* {{[0-9a-zA-Z_%.]+}} to i64* // CHECK-NEXT: [[REG869:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG868]], align 8 -// CHECK-NEXT: [[REG870:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG869]]) +// CHECK-NEXT: [[REG870A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG869]], i32 0 +// CHECK-NEXT: [[REG870:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG870A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x i64> [[REG870]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG871:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG831]], align 8 -// CHECK-NEXT: [[REG872:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG871]]) +// CHECK-NEXT: [[REG872A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG871]], i32 0 +// CHECK-NEXT: [[REG872:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG872A]], <2 x i64> undef, <2 x i32> zeroinitializer // CHECK-NEXT: store <2 x i64> [[REG872]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG873:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 // CHECK-NEXT: [[REG874:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16 diff --git a/clang/test/CodeGen/pr44276.c b/clang/test/CodeGen/pr44276.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/pr44276.c @@ -0,0 +1,22 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr8 %s -verify +// expected-no-diagnostics + +// Check that this compiles + +#include + +void test() { + static vector unsigned char a = vec_splats('1'); + static vector signed char b = vec_splats((signed char)'1'); + static vector unsigned short c = vec_splats((unsigned short)1U); + static vector signed short d = vec_splats((short)1); + static vector unsigned int e = vec_splats(1U); + static vector signed int f = vec_splats(1); + static vector float g = vec_splats(1.0f); + static vector unsigned long long h = vec_splats(1ULL); + static vector signed long long i = vec_splats(1LL); + static vector double j = vec_splats(1.0); + static vector unsigned __int128 k = vec_splats((__int128)1); + static vector signed __int128 l = vec_splats((__int128)1); +}