Index: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4623,13 +4623,13 @@
   if (!PredVT.isScalableVector() || PredVT.getVectorElementType() != MVT::i1)
     return EVT();
 
-  const unsigned NumElts = PredVT.getVectorNumElements();
+  ElementCount EC = PredVT.getVectorElementCount();
 
-  if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
+  if (EC.Min != 2 && EC.Min != 4 && EC.Min != 8 && EC.Min != 16)
     return EVT();
 
-  EVT ScalarVT = EVT::getIntegerVT(Ctx, AArch64::SVEBitsPerBlock / NumElts);
-  EVT MemVT = EVT::getVectorVT(Ctx, ScalarVT, NumElts, /*IsScalable=*/true);
+  EVT ScalarVT = EVT::getIntegerVT(Ctx, AArch64::SVEBitsPerBlock / EC.Min);
+  EVT MemVT = EVT::getVectorVT(Ctx, ScalarVT, EC);
   return MemVT;
 }
 
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-prfw.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-prfw.ll
@@ -0,0 +1,46 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define void @prf_nxv2i1(<vscale x 2 x i1> %pg, i8* %base) {
+; CHECK-LABEL: prf_nxv2i1:
+; CHECK:       prfd pldl1keep, p0, [x0]
+entry:
+  call void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1> %pg, i8* %base, i32 0)
+  ret void
+}
+
+define void @prf_nxv4i1(<vscale x 4 x i1> %pg, i8* %base) {
+; CHECK-LABEL: prf_nxv4i1:
+; CHECK:       prfw pldl1keep, p0, [x0]
+entry:
+  call void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1> %pg, i8* %base, i32 0)
+  ret void
+}
+
+define void @prf_nxv8i1(<vscale x 8 x i1> %pg, i8* %base) {
+; CHECK-LABEL: prf_nxv8i1:
+; CHECK:       prfh pldl1keep, p0, [x0]
+entry:
+  call void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1> %pg, i8* %base, i32 0)
+  ret void
+}
+
+define void @prf_nxv16i1(<vscale x 16 x i1> %pg, i8* %base) {
+; CHECK-LABEL: prf_nxv16i1:
+; CHECK:       prfb pldl1keep, p0, [x0]
+entry:
+  call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, i8* %base, i32 0)
+  ret void
+}
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1>, i8*, i32 immarg)
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1>, i8*, i32 immarg)
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1>, i8*, i32 immarg)
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1>, i8*, i32 immarg)
+