Index: lib/Target/AArch64/AArch64SchedA57.td
===================================================================
--- lib/Target/AArch64/AArch64SchedA57.td
+++ lib/Target/AArch64/AArch64SchedA57.td
@@ -127,6 +127,15 @@
 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
 
 
+// Shifted Register with Shift == 0
+// ----------------------------------------------------------------------------
+
+def A57WriteISReg : SchedWriteVariant<[
+       SchedVar<RegShiftedPred, [WriteISReg]>,
+       SchedVar<NoSchedPred, [WriteI]>]>;
+def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
+
+
 // Divide and Multiply Instructions
 // -----------------------------------------------------------------------------