diff --git a/lld/test/ELF/riscv-branch.s b/lld/test/ELF/riscv-branch.s
--- a/lld/test/ELF/riscv-branch.s
+++ b/lld/test/ELF/riscv-branch.s
@@ -5,17 +5,21 @@
 
 # RUN: ld.lld %t.rv32.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv32
 # RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64
-# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
-# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
-# CHECK: 63 02 00 00     beqz    zero, 4
-# CHECK: e3 1e 00 fe     bnez    zero, -4
+# RUN: llvm-objdump -d %t.rv32 | FileCheck --check-prefix=CHECK32 %s
+# RUN: llvm-objdump -d %t.rv64 | FileCheck --check-prefix=CHECK64 %s
+# CHECK32: 63 02 00 00     beqz    zero, 0x110b8
+# CHECK32: e3 1e 00 fe     bnez    zero, 0x110b4
+# CHECK64: 63 02 00 00     beqz    zero, 0x11124
+# CHECK64: e3 1e 00 fe     bnez    zero, 0x11120
 #
 # RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv32.limits
 # RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv64.limits
-# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
-# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
-# LIMITS:      e3 0f 00 7e     beqz    zero, 4094
-# LIMITS-NEXT: 63 10 00 80     bnez    zero, -4096
+# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS32 %s
+# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS64 %s
+# LIMITS32:      e3 0f 00 7e     beqz    zero, 0x120b2
+# LIMITS32-NEXT: 63 10 00 80     bnez    zero, 0x100b8
+# LIMITS64:      e3 0f 00 7e     beqz    zero, 0x1211e
+# LIMITS64-NEXT: 63 10 00 80     bnez    zero, 0x10124
 
 # RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
 # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
diff --git a/lld/test/ELF/riscv-jal.s b/lld/test/ELF/riscv-jal.s
--- a/lld/test/ELF/riscv-jal.s
+++ b/lld/test/ELF/riscv-jal.s
@@ -5,17 +5,21 @@
 
 # RUN: ld.lld %t.rv32.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv32
 # RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64
-# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
-# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
-# CHECK: 6f 00 40 00    j   4
-# CHECK: ef f0 df ff    jal -4
+# RUN: llvm-objdump -d %t.rv32 | FileCheck --check-prefix=CHECK32 %s
+# RUN: llvm-objdump -d %t.rv64 | FileCheck --check-prefix=CHECK64 %s
+# CHECK32: 6f 00 40 00    j   0x110b8
+# CHECK32: ef f0 df ff    jal 0x110b4
+# CHECK64: 6f 00 40 00    j   0x11124
+# CHECK64: ef f0 df ff    jal 0x11120
 
 # RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv32.limits
 # RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv64.limits
-# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
-# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
-# LIMITS:      6f f0 ff 7f j   1048574
-# LIMITS-NEXT: ef 00 00 80 jal -1048576
+# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS32 %s
+# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS64 %s
+# LIMITS32:      6f f0 ff 7f j   0x1110b2
+# LIMITS32-NEXT: ef 00 00 80 jal 0xfff110b8
+# LIMITS64:      6f f0 ff 7f j   0x11111e
+# LIMITS64-NEXT: ef 00 00 80 jal 0xfffffffffff11124
 
 # RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
 # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
diff --git a/lld/test/ELF/riscv-undefined-weak.s b/lld/test/ELF/riscv-undefined-weak.s
--- a/lld/test/ELF/riscv-undefined-weak.s
+++ b/lld/test/ELF/riscv-undefined-weak.s
@@ -52,15 +52,14 @@
 # PC-LABEL:    <branch>:
 # PC-NEXT:     auipc ra, 1048559
 # PC-NEXT:     jalr -368(ra)
-## FIXME: llvm-objdump -d should print the address, instead of the offset.
-# PC-NEXT:     j -70008
+# PC-NEXT:     j 0x0 <target>
 
 ## If .dynsym exists, an undefined weak symbol is preemptible.
 ## We create a PLT entry and redirect the reference to it.
 # PLT-LABEL:   <branch>:
 # PLT-NEXT:    auipc ra, 0
 # PLT-NEXT:    jalr 56(ra)
-# PLT-NEXT:    j -70448
+# PLT-NEXT:    0x0 <target>
 branch:
   call target
   jal x0, target
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -808,6 +808,7 @@
 class Operand<ValueType ty> : DAGOperand {
   ValueType Type = ty;
   string PrintMethod = "printOperand";
+  bit PrintRequiresAddr = 0;
   string EncoderMethod = "";
   bit hasCompleteDecoder = 1;
   string OperandType = "OPERAND_UNKNOWN";
@@ -837,6 +838,9 @@
   // this type. The method normally will just use an alt-name index to look
   // up the name to print. Default to the generic printOperand().
   string PrintMethod = pm;
+  // PrintRequiresAddr - The target method PrintMethod requires the program
+  // counter to print the operand.
+  bit PrintRequiresAddr = 0;
 
   // EncoderMethod - The target method name to call to encode this register
   // operand.
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -30,6 +30,9 @@
                  const MCSubtargetInfo &STI, raw_ostream &O) override;
   void printRegName(raw_ostream &O, unsigned RegNo) const override;
 
+  void printPCRelOp(const MCInst *MI, uint64_t Address, unsigned OpNo,
+                    const MCSubtargetInfo &STI, raw_ostream &O,
+                    const char *Modifier = nullptr);
   void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O, const char *Modifier = nullptr);
   void printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -82,6 +82,22 @@
   O << getRegisterName(RegNo);
 }
 
+void RISCVInstPrinter::printPCRelOp(const MCInst *MI, uint64_t Address,
+                                    unsigned OpNo, const MCSubtargetInfo &STI,
+                                    raw_ostream &O, const char *Modifier) {
+  assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
+
+  if (PrintBranchImmAsAddress && MI->getOperand(OpNo).isImm()) {
+    uint64_t TargetAddress = Address + MI->getOperand(OpNo).getImm();
+    if (!STI.getFeatureBits()[RISCV::Feature64Bit])
+      TargetAddress &= 0xffffffff;
+    O << formatHex(TargetAddress);
+    return;
+  }
+
+  printOperand(MI, OpNo, STI, O, Modifier);
+}
+
 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                     const MCSubtargetInfo &STI, raw_ostream &O,
                                     const char *Modifier) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -163,6 +163,8 @@
   let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
+  let PrintMethod = "printPCRelOp";
+  let PrintRequiresAddr = 1;
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
@@ -202,6 +204,8 @@
   let ParserMatchClass = Simm21Lsb0JALAsmOperand;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
+  let PrintMethod = "printPCRelOp";
+  let PrintRequiresAddr = 1;
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -142,6 +142,8 @@
   let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
+  let PrintMethod = "printPCRelOp";
+  let PrintRequiresAddr = 1;
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
@@ -202,6 +204,8 @@
   let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
+  let PrintMethod = "printPCRelOp";
+  let PrintRequiresAddr = 1;
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
diff --git a/llvm/test/CodeGen/RISCV/compress.ll b/llvm/test/CodeGen/RISCV/compress.ll
--- a/llvm/test/CodeGen/RISCV/compress.ll
+++ b/llvm/test/CodeGen/RISCV/compress.ll
@@ -50,34 +50,34 @@
 define i32 @select(i32 %a, i32 *%b) #0 {
 ; RV32IC-LABEL: <select>:
 ; RV32IC:         c.lw a2, 0(a1)
-; RV32IC-NEXT:    c.beqz a2, 4
+; RV32IC-NEXT:    c.beqz a2, 0x18
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a2, 0(a1)
-; RV32IC-NEXT:    c.bnez a2, 4
+; RV32IC-NEXT:    c.bnez a2, 0x1e
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a2, 0(a1)
-; RV32IC-NEXT:    bltu a2, a0, 6
+; RV32IC-NEXT:    bltu a2, a0, 0x26
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a2, 0(a1)
-; RV32IC-NEXT:    bgeu a0, a2, 6
+; RV32IC-NEXT:    bgeu a0, a2, 0x2e
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a2, 0(a1)
-; RV32IC-NEXT:    bltu a0, a2, 6
+; RV32IC-NEXT:    bltu a0, a2, 0x36
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a2, 0(a1)
-; RV32IC-NEXT:    bgeu a2, a0, 6
+; RV32IC-NEXT:    bgeu a2, a0, 0x3e
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a2, 0(a1)
-; RV32IC-NEXT:    blt a2, a0, 6
+; RV32IC-NEXT:    blt a2, a0, 0x46
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a2, 0(a1)
-; RV32IC-NEXT:    bge a0, a2, 6
+; RV32IC-NEXT:    bge a0, a2, 0x4e
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a2, 0(a1)
-; RV32IC-NEXT:    blt a0, a2, 6
+; RV32IC-NEXT:    blt a0, a2, 0x56
 ; RV32IC-NEXT:    c.mv a0, a2
 ; RV32IC-NEXT:    c.lw a1, 0(a1)
-; RV32IC-NEXT:    bge a1, a0, 6
+; RV32IC-NEXT:    bge a1, a0, 0x5e
 ; RV32IC-NEXT:    c.mv a0, a1
 ; RV32IC-NEXT:    c.jr ra
   %val1 = load volatile i32, i32* %b
diff --git a/llvm/test/MC/Disassembler/RISCV/branch-targets.txt b/llvm/test/MC/Disassembler/RISCV/branch-targets.txt
--- a/llvm/test/MC/Disassembler/RISCV/branch-targets.txt
+++ b/llvm/test/MC/Disassembler/RISCV/branch-targets.txt
@@ -15,13 +15,13 @@
   bnez a0, label1
   bnez a0, label2
 # CHECK-LABEL: <label1>:
-# CHECK-NEXT: jal zero, 0 <label1>
-# CHECK-NEXT: jal zero, 20 <label2>
-# CHECK-NEXT: bne a0, zero, -8 <label1>
-# CHECK-NEXT: bne a0, zero, 12 <label2>
-# CHECK-NEXT: c.j -16 <label1>
-# CHECK-NEXT: c.j 6 <label2>
-# CHECK-NEXT: c.bnez a0, -20 <label1>
-# CHECK-NEXT: c.bnez a0, 2 <label2>
+# CHECK-NEXT: jal zero, 0x0 <label1>
+# CHECK-NEXT: jal zero, 0x18 <label2>
+# CHECK-NEXT: bne a0, zero, 0x0 <label1>
+# CHECK-NEXT: bne a0, zero, 0x18 <label2>
+# CHECK-NEXT: c.j 0x0 <label1>
+# CHECK-NEXT: c.j 0x18 <label2>
+# CHECK-NEXT: c.bnez a0, 0x0 <label1>
+# CHECK-NEXT: c.bnez a0, 0x18 <label2>
 
 label2:
diff --git a/llvm/test/MC/RISCV/compress-cjal.s b/llvm/test/MC/RISCV/compress-cjal.s
--- a/llvm/test/MC/RISCV/compress-cjal.s
+++ b/llvm/test/MC/RISCV/compress-cjal.s
@@ -1,17 +1,19 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS-ASM %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \
-# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST-ASM %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
 # RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS-OBJ %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
 # RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST-OBJ %s
 
 # c.jal is an rv32 only instruction.
 jal ra, 2046
 # CHECK-BYTES: fd 2f
-# CHECK-ALIAS: jal 2046
-# CHECK-INST: c.jal 2046
+# CHECK-ALIAS-ASM: jal 2046
+# CHECK-ALIAS-OBJ: jal 0x7fe
+# CHECK-INST-ASM: c.jal 2046
+# CHECK-INST-OBJ: c.jal 0x7fe
 # CHECK:  # encoding: [0xfd,0x2f]
diff --git a/llvm/test/MC/RISCV/compress-rv32i.s b/llvm/test/MC/RISCV/compress-rv32i.s
--- a/llvm/test/MC/RISCV/compress-rv32i.s
+++ b/llvm/test/MC/RISCV/compress-rv32i.s
@@ -1,24 +1,24 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS,CHECK-ALIAS-ASM %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -show-encoding \
-# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-INST-ASM %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
 # RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS,CHECK-ALIAS-OBJ %s
 # RUN: llvm-mc -triple riscv32 -mattr=+c -filetype=obj < %s \
 # RUN: | llvm-objdump  --triple=riscv32 --mattr=+c -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INST-OBJ %s
 
 # RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS,CHECK-ALIAS-ASM %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c -show-encoding \
-# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: -riscv-no-aliases <%s | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-INST-ASM %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
 # RUN: | llvm-objdump  --triple=riscv64 --mattr=+c -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS,CHECK-ALIAS-OBJ %s
 # RUN: llvm-mc -triple riscv64 -mattr=+c -filetype=obj < %s \
 # RUN: | llvm-objdump  --triple=riscv64 --mattr=+c -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INST-OBJ %s
 
 # CHECK-BYTES: 2e 85
 # CHECK-ALIAS: add a0, zero, a1
@@ -135,20 +135,26 @@
 and s0, a5, s0
 
 # CHECK-BYTES: 01 b0
-# CHECK-ALIAS: j -2048
-# CHECK-INST: c.j -2048
+# CHECK-ALIAS-ASM: j -2048
+# CHECK-ALIAS-OBJ: j 0xfffff
+# CHECK-INST-ASM: c.j -2048
+# CHECK-INST-OBJ: c.j 0xfffff
 # CHECK:  # encoding: [0x01,0xb0]
 jal zero, -2048
 
 # CHECK-BYTES: 01 d0
-# CHECK-ALIAS: beqz s0, -256
-# CHECK-INST: c.beqz s0, -256
+# CHECK-ALIAS-ASM: beqz s0, -256
+# CHECK-ALIAS-OBJ: beqz s0, 0xffffff
+# CHECK-INST-ASM: c.beqz s0, -256
+# CHECK-INST-OBJ: c.beqz s0, 0xffffff
 # CHECK: # encoding: [0x01,0xd0]
 beq s0, zero, -256
 
 # CHECK-BYTES: 7d ec
-# CHECk-ALIAS: bnez s0, 254
-# CHECK-INST: c.bnez s0, 254
+# CHECK-ALIAS-ASM: bnez s0, 254
+# CHECK-ALIAS-OBJ: bnez s0, 0x128
+# CHECK-INST-ASM: c.bnez s0, 254
+# CHECK-INST-OBJ: c.bnez s0, 0x128
 # CHECK: # encoding: [0x7d,0xec]
 bne s0, zero, 254
 
diff --git a/llvm/test/MC/RISCV/fixups-compressed.s b/llvm/test/MC/RISCV/fixups-compressed.s
--- a/llvm/test/MC/RISCV/fixups-compressed.s
+++ b/llvm/test/MC/RISCV/fixups-compressed.s
@@ -7,16 +7,16 @@
 
 .LBB0_2:
 # CHECK-FIXUP:   fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_jump
-# CHECK-INSTR: c.j     0
+# CHECK-INSTR: c.j     0x0
 c.j     .LBB0_2
 # CHECK:   fixup A - offset: 0, value: func1, kind: fixup_riscv_rvc_jump
-# CHECK-INSTR: c.jal   6
+# CHECK-INSTR: c.jal   0x8
 c.jal   func1
 # CHECK-FIXUP:   fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_branch
-# CHECK-INSTR: c.beqz  a3, -4
+# CHECK-INSTR: c.beqz  a3, 0x0
 c.beqz  a3, .LBB0_2
 # CHECK-FIXUP:   fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_branch
-# CHECK-INSTR: c.bnez  a5, -6
+# CHECK-INSTR: c.bnez  a5, 0x0
 c.bnez  a5, .LBB0_2
 
 func1:
diff --git a/llvm/test/MC/RISCV/fixups.s b/llvm/test/MC/RISCV/fixups.s
--- a/llvm/test/MC/RISCV/fixups.s
+++ b/llvm/test/MC/RISCV/fixups.s
@@ -37,16 +37,16 @@
 
 jal zero, .LBB0
 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB0, kind: fixup_riscv_jal
-# CHECK-INSTR: jal zero, -28
+# CHECK-INSTR: jal zero, 0x0
 jal zero, .LBB2
 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB2, kind: fixup_riscv_jal
-# CHECK-INSTR: jal zero, 330996
+# CHECK-INSTR: jal zero, 0x50d14
 beq a0, a1, .LBB0
 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB0, kind: fixup_riscv_branch
-# CHECK-INSTR: beq a0, a1, -36
+# CHECK-INSTR: beq a0, a1, 0x0
 blt a0, a1, .LBB1
 # CHECK-FIXUP: fixup A - offset: 0, value: .LBB1, kind: fixup_riscv_branch
-# CHECK-INSTR: blt a0, a1, 1108
+# CHECK-INSTR: blt a0, a1, 0x47c
 
 .fill 1104
 
diff --git a/llvm/test/MC/RISCV/rv32-relaxation.s b/llvm/test/MC/RISCV/rv32-relaxation.s
--- a/llvm/test/MC/RISCV/rv32-relaxation.s
+++ b/llvm/test/MC/RISCV/rv32-relaxation.s
@@ -18,103 +18,103 @@
 
 start:
   c.bnez a0, NEAR
-#INSTR: c.bnez a0, 72
-#RELAX-INSTR: c.bnez a0, 0
+#INSTR: c.bnez a0, 0x91e
+#RELAX-INSTR: c.bnez a0, 0x8d8
 #RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.bnez a0, NEAR_NEGATIVE
-#INSTR: c.bnez a0, -4
-#RELAX-INSTR: c.bnez a0, 0
+#INSTR: c.bnez a0, 0x8d4
+#RELAX-INSTR: c.bnez a0, 0x8da
 #RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.bnez a0, FAR_BRANCH
-#INSTR-NEXT: bne a0, zero, 326
-#RELAX-INSTR-NEXT: bne a0, zero, 0
+#INSTR-NEXT: bne a0, zero, 0xa20
+#RELAX-INSTR-NEXT: bne a0, zero, 0x8dc
 #RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: bne a0, zero, -268
-#RELAX-INSTR-NEXT: bne a0, zero, 0
+#INSTR-NEXT: bne a0, zero, 0x7d2
+#RELAX-INSTR-NEXT: bne a0, zero, 0x8e0
 #RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_JUMP
-#INSTR-NEXT: bne a0, zero, 2320
-#RELAX-INSTR-NEXT: bne a0, zero, 0
+#INSTR-NEXT: bne a0, zero, 0x11f2
+#RELAX-INSTR-NEXT: bne a0, zero, 0x8e4
 #RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_JUMP_NEGATIVE
-#INSTR-NEXT: bne a0, zero, -2278
-#RELAX-INSTR-NEXT: bne a0, zero, 0
+#INSTR-NEXT: bne a0, zero, 0x0
+#RELAX-INSTR-NEXT: bne a0, zero, 0x8e8
 #RELAX-RELOC: R_RISCV_BRANCH
 
   c.beqz a0, NEAR
-#INSTR-NEXT: c.beqz a0, 52
-#RELAX-INSTR-NEXT: c.beqz a0, 0
+#INSTR-NEXT: c.beqz a0, 0x91e
+#RELAX-INSTR-NEXT: c.beqz a0, 0x8ec
 #RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.beqz a0, NEAR_NEGATIVE
-#INSTR-NEXT: c.beqz a0, -24
-#RELAX-INSTR-NEXT: c.beqz a0, 0
+#INSTR-NEXT: c.beqz a0, 0x8d4
+#RELAX-INSTR-NEXT: c.beqz a0, 0x8ee
 #RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.beqz a0, FAR_BRANCH
-#INSTR-NEXT: beq a0, zero, 306
-#RELAX-INSTR-NEXT: beq a0, zero, 0
+#INSTR-NEXT: beq a0, zero, 0xa20
+#RELAX-INSTR-NEXT: beq a0, zero, 0x8f0
 #RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: beq a0, zero, -288
-#RELAX-INSTR-NEXT: beq a0, zero, 0
+#INSTR-NEXT: beq a0, zero, 0x7d2
+#RELAX-INSTR-NEXT: beq a0, zero, 0x8f4
 #RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_JUMP
-#INSTR-NEXT: beq a0, zero, 2300
-#RELAX-INSTR-NEXT: beq a0, zero, 0
+#INSTR-NEXT: beq a0, zero, 0x11f2
+#RELAX-INSTR-NEXT: beq a0, zero, 0x8f8
 #RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_JUMP_NEGATIVE
-#INSTR-NEXT: beq a0, zero, -2298
-#RELAX-INSTR-NEXT: beq a0, zero, 0
+#INSTR-NEXT: beq a0, zero, 0x0
+#RELAX-INSTR-NEXT: beq a0, zero, 0x8fc
 #RELAX-RELOC: R_RISCV_BRANCH
 
   c.j NEAR
-#INSTR-NEXT: c.j 32
-#RELAX-INSTR-NEXT: c.j 0
+#INSTR-NEXT: c.j 0x91e
+#RELAX-INSTR-NEXT: c.j 0x900
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j NEAR_NEGATIVE
-#INSTR-NEXT: c.j -44
-#RELAX-INSTR-NEXT: c.j 0
+#INSTR-NEXT: c.j 0x8d4
+#RELAX-INSTR-NEXT: c.j 0x902
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_BRANCH
-#INSTR-NEXT: c.j 286
-#RELAX-INSTR-NEXT: c.j 0
+#INSTR-NEXT: c.j 0xa20
+#RELAX-INSTR-NEXT: c.j 0x904
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: c.j -306
-#RELAX-INSTR-NEXT: c.j 0
+#INSTR-NEXT: c.j 0x7d2
+#RELAX-INSTR-NEXT: c.j 0x906
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_JUMP
-#INSTR-NEXT: jal zero, 2284
-#RELAX-INSTR-NEXT: jal zero, 0
+#INSTR-NEXT: jal zero, 0x11f2
+#RELAX-INSTR-NEXT: jal zero, 0x908
 #RELAX-RELOC: R_RISCV_JAL
   c.j FAR_JUMP_NEGATIVE
-#INSTR-NEXT: jal zero, -2314
-#RELAX-INSTR-NEXT: jal zero, 0
+#INSTR-NEXT: jal zero, 0x0
+#RELAX-INSTR-NEXT: jal zero, 0x90c
 #RELAX-RELOC: R_RISCV_JAL
 
   c.jal NEAR
-#INSTR: c.jal 16
-#RELAX-INSTR: c.jal 0
+#INSTR: c.jal 0x91e
+#RELAX-INSTR: c.jal 0x910
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.jal NEAR_NEGATIVE
-#INSTR: c.jal -60
-#RELAX-INSTR: c.jal 0
+#INSTR: c.jal 0x8d4
+#RELAX-INSTR: c.jal 0x912
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.jal FAR_BRANCH
-#INSTR-NEXT: c.jal 270
-#RELAX-INSTR-NEXT: c.jal 0
+#INSTR-NEXT: c.jal 0xa20
+#RELAX-INSTR-NEXT: c.jal 0x914
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.jal FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: c.jal -322
-#RELAX-INSTR-NEXT: c.jal 0
+#INSTR-NEXT: c.jal 0x7d2
+#RELAX-INSTR-NEXT: c.jal 0x916
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.jal FAR_JUMP
-#INSTR-NEXT: jal ra, 2268
-#RELAX-INSTR-NEXT: jal ra, 0
+#INSTR-NEXT: jal ra, 0x11f2
+#RELAX-INSTR-NEXT: jal ra, 0x918
 #RELAX-RELOC: R_RISCV_JAL
   c.jal FAR_JUMP_NEGATIVE
-#INSTR-NEXT: jal ra, -2330
-#RELAX-INSTR-NEXT: jal ra, 0
+#INSTR-NEXT: jal ra, 0x0
+#RELAX-INSTR-NEXT: jal ra, 0x91c
 #RELAX-RELOC: R_RISCV_JAL
 
 NEAR:
diff --git a/llvm/test/MC/RISCV/rv32c-only-valid.s b/llvm/test/MC/RISCV/rv32c-only-valid.s
--- a/llvm/test/MC/RISCV/rv32c-only-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-only-valid.s
@@ -1,8 +1,8 @@
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \
 # RUN:     | llvm-objdump --mattr=+c -M no-aliases -d -r - \
-# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ %s
 #
 # RUN: not llvm-mc -triple riscv32 \
 # RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
@@ -14,7 +14,8 @@
 # RUN:     -riscv-no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-RV32-AND-EXT %s
 
-# CHECK-ASM-AND-OBJ: c.jal 2046
+# CHECK-ASM: c.jal 2046
+# CHECK-OBJ: c.jal 0x7fe
 # CHECK-ASM: encoding: [0xfd,0x2f]
 # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
 # CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32c-valid.s b/llvm/test/MC/RISCV/rv32c-valid.s
--- a/llvm/test/MC/RISCV/rv32c-valid.s
+++ b/llvm/test/MC/RISCV/rv32c-valid.s
@@ -24,7 +24,8 @@
 # CHECK-ASM: encoding: [0xfc,0xde]
 c.sw a5, 124(a3)
 
-# CHECK-ASM-AND-OBJ: c.j -2048
+# CHECK-ASM: c.j -2048
+# CHECK-OBJ: c.j 0xfffff
 # CHECK-ASM: encoding: [0x01,0xb0]
 c.j -2048
 # CHECK-ASM-AND-OBJ: c.jr a7
@@ -33,10 +34,12 @@
 # CHECK-ASM-AND-OBJ: c.jalr a1
 # CHECK-ASM: encoding: [0x82,0x95]
 c.jalr a1
-# CHECK-ASM-AND-OBJ: c.beqz a3, -256
+# CHECK-ASM: c.beqz a3, -256
+# CHECK-OBJ: c.beqz a3, 0xffffff
 # CHECK-ASM: encoding: [0x81,0xd2]
 c.beqz a3, -256
-# CHECK-ASM-AND-OBJ: c.bnez a5, 254
+# CHECK-ASM: c.bnez a5, 254
+# CHECK-OBJ: c.bnez a5, 0x10e
 # CHECK-ASM: encoding: [0xfd,0xef]
 c.bnez a5,  254
 
diff --git a/llvm/test/MC/RISCV/rv32e-valid.s b/llvm/test/MC/RISCV/rv32e-valid.s
--- a/llvm/test/MC/RISCV/rv32e-valid.s
+++ b/llvm/test/MC/RISCV/rv32e-valid.s
@@ -1,8 +1,8 @@
 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \
-# RUN:     | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ,CHECK-ASM %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \
 # RUN:     | llvm-objdump -M no-aliases -d -r - \
-# RUN:     | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ,CHECK-OBJ %s
 
 # This file provides a basic sanity check for RV32E, checking that the expected
 # set of registers and instructions are accepted.
@@ -12,20 +12,26 @@
 # CHECK-ASM-AND-OBJ: auipc ra, 2
 auipc x1, 2
 
-# CHECK-ASM-AND-OBJ: jal sp, 4
+# CHECK-ASM: jal sp, 4
+# CHECK-OBJ: jal sp, 0xc
 jal x2, 4
 # CHECK-ASM-AND-OBJ: jalr gp, 4(gp)
 jalr x3, x3, 4
 
-# CHECK-ASM-AND-OBJ: beq tp, t0, 8
+# CHECK-ASM: beq tp, t0, 8
+# CHECK-OBJ: beq tp, t0, 0x18
 beq x4, x5, 8
-# CHECK-ASM-AND-OBJ: bne t1, t2, 12
+# CHECK-ASM: bne t1, t2, 12
+# CHECK-OBJ: bne t1, t2, 0x20
 bne x6, x7, 12
-# CHECK-ASM-AND-OBJ: blt s0, s1, 16
+# CHECK-ASM: blt s0, s1, 16
+# CHECK-OBJ: blt s0, s1, 0x28
 blt x8, x9, 16
-# CHECK-ASM-AND-OBJ: bge a0, a1, 20
+# CHECK-ASM: bge a0, a1, 20
+# CHECK-OBJ: bge a0, a1, 0x30
 bge x10, x11, 20
-# CHECK-ASM-AND-OBJ: bgeu a2, a3, 24
+# CHECK-ASM: bgeu a2, a3, 24
+# CHECK-OBJ: bgeu a2, a3, 0x38
 bgeu x12, x13, 24
 
 # CHECK-ASM-AND-OBJ: lb a4, 25(a5)
diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s
--- a/llvm/test/MC/RISCV/rv32i-valid.s
+++ b/llvm/test/MC/RISCV/rv32i-valid.s
@@ -68,33 +68,38 @@
 # CHECK-ASM: encoding: [0x17,0xe5,0x01,0x00]
 auipc a0, CONST
 
-# CHECK-ASM-AND-OBJ: jal a2, 1048574
+# CHECK-ASM: jal a2, 1048574
+# CHECK-OBJ: jal a2, 0x100042
 # CHECK-ASM: encoding: [0x6f,0xf6,0xff,0x7f]
 jal a2, 1048574
-# CHECK-ASM-AND-OBJ: jal a3, 256
+# CHECK-ASM: jal a3, 256
+# CHECK-OBJ: jal a3, 0x148
 # CHECK-ASM: encoding: [0xef,0x06,0x00,0x10]
 jal a3, 256
 # CHECK-ASM: jal a0, foo
 # CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
-# CHECK-OBJ: jal a0, 0
+# CHECK-OBJ: jal a0, 0x4c
 # CHECK-OBJ: R_RISCV_JAL foo
 jal a0, foo
 # CHECK-ASM: jal a0, a0
 # CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
-# CHECK-OBJ: jal a0, 0
+# CHECK-OBJ: jal a0, 0x50
 # CHECK-OBJ: R_RISCV_JAL a0
 jal a0, a0
-# CHECK-ASM-AND-OBJ: jal a0, 30
+# CHECK-ASM: jal a0, 30
+# CHECK-OBJ: jal a0, 0x72
 # CHECK-ASM: encoding: [0x6f,0x05,0xe0,0x01]
 jal a0, CONST
-# CHECK-ASM-AND-OBJ: jal s0, 0
+# CHECK-ASM: jal s0, 0
+# CHECK-OBJ: jal s0, 0x58
 # CHECK-ASM: encoding: [0x6f,0x04,0x00,0x00]
 jal s0, (0)
-# CHECK-ASM-AND-OBJ: jal s0, 156
+# CHECK-ASM: jal s0, 156
+# CHECK-OBJ: jal s0, 0xf8
 # CHECK-ASM: encoding: [0x6f,0x04,0xc0,0x09]
 jal s0, (0xff-99)
 # CHECK-ASM: encoding: [0x6f,0bAAAA0000,A,A]
-# CHECK-OBJ: jal zero, 0
+# CHECK-OBJ: jal zero, 0x60
 jal zero, .
 
 # CHECK-ASM-AND-OBJ: jalr a0, -2048(a1)
@@ -113,25 +118,32 @@
 # CHECK-ASM: encoding: [0xe7,0x05,0xe6,0x01]
 jalr a1, CONST(a2)
 
-# CHECK-ASM-AND-OBJ: beq s1, s1, 102
+# CHECK-ASM: beq s1, s1, 102
+# CHECK-OBJ: beq s1, s1, 0xde
 # CHECK-ASM: encoding: [0x63,0x83,0x94,0x06]
 beq s1, s1, 102
-# CHECK-ASM-AND-OBJ: bne a4, a5, -4096
+# CHECK-ASM: bne a4, a5, -4096
+# CHECK-OBJ: bne a4, a5, 0xfffff
 # CHECK-ASM: encoding: [0x63,0x10,0xf7,0x80]
 bne a4, a5, -4096
-# CHECK-ASM-AND-OBJ: blt sp, gp, 4094
+# CHECK-ASM: blt sp, gp, 4094
+# CHECK-OBJ: blt sp, gp, 0x107e
 # CHECK-ASM: encoding: [0xe3,0x4f,0x31,0x7e]
 blt sp, gp, 4094
-# CHECK-ASM-AND-OBJ: bge s2, ra, -224
+# CHECK-ASM: bge s2, ra, -224
+# CHECK-OBJ: bge s2, ra, 0xfffff
 # CHECK-ASM: encoding: [0xe3,0x50,0x19,0xf2]
 bge s2, ra, -224
-# CHECK-ASM-AND-OBJ: bltu zero, zero, 0
+# CHECK-ASM: bltu zero, zero, 0
+# CHECK-OBJ: bltu zero, zero, 0x88
 # CHECK-ASM: encoding: [0x63,0x60,0x00,0x00]
 bltu zero, zero, 0
-# CHECK-ASM-AND-OBJ: bgeu s8, sp, 512
+# CHECK-ASM: bgeu s8, sp, 512
+# CHECK-OBJ: bgeu s8, sp, 0x28c
 # CHECK-ASM: encoding: [0x63,0x70,0x2c,0x20]
 bgeu s8, sp, 512
-# CHECK-ASM-AND-OBJ: bgeu t0, t1, 30
+# CHECK-ASM: bgeu t0, t1, 30
+# CHECK-OBJ: bgeu t0, t1, 0xae
 # CHECK-ASM: encoding: [0x63,0xff,0x62,0x00]
 bgeu t0, t1, CONST
 
diff --git a/llvm/test/MC/RISCV/rv64-relax-all.s b/llvm/test/MC/RISCV/rv64-relax-all.s
--- a/llvm/test/MC/RISCV/rv64-relax-all.s
+++ b/llvm/test/MC/RISCV/rv64-relax-all.s
@@ -1,15 +1,19 @@
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c %s | llvm-objdump -d -M no-aliases --no-show-raw-insn - | FileCheck %s --check-prefix=INSTR
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c %s \
+# RUN:     | llvm-objdump -d -M no-aliases --no-show-raw-insn - \
+# RUN:     | FileCheck %s --check-prefix=INSTR
 
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c %s --mc-relax-all | llvm-objdump -d -M no-aliases --no-show-raw-insn - | FileCheck %s --check-prefix=RELAX-INSTR
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c %s --mc-relax-all \
+# RUN:     | llvm-objdump -d -M no-aliases --no-show-raw-insn - \
+# RUN:     | FileCheck %s --check-prefix=RELAX-INSTR
 
 ## Check the instructions are relaxed correctly
 
 NEAR:
 
-# INSTR:           c.beqz    a0, 0 <NEAR>
-# RELAX-INSTR:     beq    a0, zero, 0 <NEAR>
+# INSTR:           c.beqz    a0, 0x0 <NEAR>
+# RELAX-INSTR:     beq    a0, zero, 0x0 <NEAR>
 c.beqz a0, NEAR
 
-# INSTR:           c.j    -2 <NEAR>
-# RELAX-INSTR:     jal    zero, -4 <NEAR>
+# INSTR:           c.j    0x0 <NEAR>
+# RELAX-INSTR:     jal    zero, 0x0 <NEAR>
 c.j NEAR
diff --git a/llvm/test/MC/RISCV/rv64-relaxation.s b/llvm/test/MC/RISCV/rv64-relaxation.s
--- a/llvm/test/MC/RISCV/rv64-relaxation.s
+++ b/llvm/test/MC/RISCV/rv64-relaxation.s
@@ -18,78 +18,78 @@
 
 start:
   c.bnez a0, NEAR
-#INSTR: c.bnez a0, 56
-#RELAX-INSTR: c.bnez a0, 0
+#INSTR: c.bnez a0, 0x90e
+#RELAX-INSTR: c.bnez a0, 0x8d8
 #RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.bnez a0, NEAR_NEGATIVE
-#INSTR: c.bnez a0, -4
-#RELAX-INSTR: c.bnez a0, 0
+#INSTR: c.bnez a0, 0x8d4
+#RELAX-INSTR: c.bnez a0, 0x8da
 #RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.bnez a0, FAR_BRANCH
-#INSTR-NEXT: bne a0, zero, 310
-#RELAX-INSTR-NEXT: bne a0, zero, 0
+#INSTR-NEXT: bne a0, zero, 0xa10
+#RELAX-INSTR-NEXT: bne a0, zero, 0x8dc
 #RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: bne a0, zero, -268
-#RELAX-INSTR-NEXT: bne a0, zero, 0
+#INSTR-NEXT: bne a0, zero, 0x7d2
+#RELAX-INSTR-NEXT: bne a0, zero, 0x8e0
 #RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_JUMP
-#INSTR-NEXT: bne a0, zero, 2304
-#RELAX-INSTR-NEXT: bne a0, zero, 0
+#INSTR-NEXT: bne a0, zero, 0x11e2
+#RELAX-INSTR-NEXT: bne a0, zero, 0x8e4
 #RELAX-RELOC: R_RISCV_BRANCH
   c.bnez a0, FAR_JUMP_NEGATIVE
-#INSTR-NEXT: bne a0, zero, -2278
-#RELAX-INSTR-NEXT: bne a0, zero, 0
+#INSTR-NEXT: bne a0, zero, 0x0
+#RELAX-INSTR-NEXT: bne a0, zero, 0x8e8
 #RELAX-RELOC: R_RISCV_BRANCH
 
   c.beqz a0, NEAR
-#INSTR-NEXT: c.beqz a0, 36
-#RELAX-INSTR-NEXT: c.beqz a0, 0
+#INSTR-NEXT: c.beqz a0, 0x90e
+#RELAX-INSTR-NEXT: c.beqz a0, 0x8ec
 #RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.beqz a0, NEAR_NEGATIVE
-#INSTR-NEXT: c.beqz a0, -24
-#RELAX-INSTR-NEXT: c.beqz a0, 0
+#INSTR-NEXT: c.beqz a0, 0x8d4
+#RELAX-INSTR-NEXT: c.beqz a0, 0x8ee
 #RELAX-RELOC: R_RISCV_RVC_BRANCH
   c.beqz a0, FAR_BRANCH
-#INSTR-NEXT: beq a0, zero, 290
-#RELAX-INSTR-NEXT: beq a0, zero, 0
+#INSTR-NEXT: beq a0, zero, 0xa10
+#RELAX-INSTR-NEXT: beq a0, zero, 0x8f0
 #RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: beq a0, zero, -288
-#RELAX-INSTR-NEXT: beq a0, zero, 0
+#INSTR-NEXT: beq a0, zero, 0x7d2
+#RELAX-INSTR-NEXT: beq a0, zero, 0x8f4
 #RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_JUMP
-#INSTR-NEXT: beq a0, zero, 2284
-#RELAX-INSTR-NEXT: beq a0, zero, 0
+#INSTR-NEXT: beq a0, zero, 0x11e2
+#RELAX-INSTR-NEXT: beq a0, zero, 0x8f8
 #RELAX-RELOC: R_RISCV_BRANCH
   c.beqz a0, FAR_JUMP_NEGATIVE
-#INSTR-NEXT: beq a0, zero, -2298
-#RELAX-INSTR-NEXT: beq a0, zero, 0
+#INSTR-NEXT: beq a0, zero, 0x0
+#RELAX-INSTR-NEXT: beq a0, zero, 0x8fc
 #RELAX-RELOC: R_RISCV_BRANCH
 
   c.j NEAR
-#INSTR-NEXT: c.j 16
-#RELAX-INSTR-NEXT: c.j 0
+#INSTR-NEXT: c.j 0x90e
+#RELAX-INSTR-NEXT: c.j 0x900
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j NEAR_NEGATIVE
-#INSTR-NEXT: c.j -44
-#RELAX-INSTR-NEXT: c.j 0
+#INSTR-NEXT: c.j 0x8d4
+#RELAX-INSTR-NEXT: c.j 0x902
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_BRANCH
-#INSTR-NEXT: c.j 270
-#RELAX-INSTR-NEXT: c.j 0
+#INSTR-NEXT: c.j 0xa10
+#RELAX-INSTR-NEXT: c.j 0x904
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_BRANCH_NEGATIVE
-#INSTR-NEXT: c.j -306
-#RELAX-INSTR-NEXT: c.j 0
+#INSTR-NEXT: c.j 0x7d2
+#RELAX-INSTR-NEXT: c.j 0x906
 #RELAX-RELOC: R_RISCV_RVC_JUMP
   c.j FAR_JUMP
-#INSTR-NEXT: jal zero, 2268
-#RELAX-INSTR-NEXT: jal zero, 0
+#INSTR-NEXT: jal zero, 0x11e2
+#RELAX-INSTR-NEXT: jal zero, 0x908
 #RELAX-RELOC: R_RISCV_JAL
   c.j FAR_JUMP_NEGATIVE
-#INSTR-NEXT: jal zero, -2314
-#RELAX-INSTR-NEXT: jal zero, 0
+#INSTR-NEXT: jal zero, 0x0
+#RELAX-INSTR-NEXT: jal zero, 0x90c
 #RELAX-RELOC: R_RISCV_JAL
 
 NEAR:
diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
--- a/llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -1,23 +1,23 @@
 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \
-# RUN:     | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS-ASM %s
 # RUN: llvm-mc %s -triple=riscv32 \
-# RUN:     | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ,CHECK-S-OBJ-ASM %s
 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases\
-# RUN:     | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS-ASM %s
 # RUN: llvm-mc %s -triple=riscv64 \
-# RUN:     | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ,CHECK-S-OBJ-ASM %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d -r -M no-aliases - \
-# RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d -r - \
-# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ,CHECK-S-OBJ-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d -r -M no-aliases - \
-# RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d -r - \
-# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ,CHECK-S-OBJ-OBJ %s
 
 # The following check prefixes are used in this test:
 # CHECK-S                 Match the .s output with aliases enabled
@@ -28,6 +28,8 @@
 #                         aliases enabled
 # CHECK-S-OBJ-NOALIAS     Match both the .s and objdumped object output with
 #                         aliases disabled
+# For *-OBJ prefixes, -OBJ and -ASM suffixes are used to differentiate between
+# llvm-objdump and llvm-mc output respectively
 
 # TODO la
 # TODO lb lh lw
@@ -69,74 +71,108 @@
 # CHECK-S-OBJ: sltu tp, t1, t0
 sgtu x4, x5, x6
 
-# CHECK-S-OBJ-NOALIAS: beq a0, zero, 512
-# CHECK-S-OBJ: beqz a0, 512
+# CHECK-S-OBJ-NOALIAS-ASM: beq a0, zero, 512
+# CHECK-S-OBJ-ASM: beqz a0, 512
+# CHECK-S-OBJ-NOALIAS-OBJ: beq a0, zero, 0x22c
+# CHECK-S-OBJ-OBJ: beqz a0, 0x22c
 beqz x10, 512
-# CHECK-S-OBJ-NOALIAS: bne a1, zero, 1024
-# CHECK-S-OBJ: bnez a1, 1024
+# CHECK-S-OBJ-NOALIAS-ASM: bne a1, zero, 1024
+# CHECK-S-OBJ-ASM: bnez a1, 1024
+# CHECK-S-OBJ-NOALIAS-OBJ: bne a1, zero, 0x430
+# CHECK-S-OBJ-OBJ: bnez a1, 0x430
 bnez x11, 1024
-# CHECK-S-OBJ-NOALIAS: bge zero, a2, 4
-# CHECK-S-OBJ: blez a2, 4
+# CHECK-S-OBJ-NOALIAS-ASM: bge zero, a2, 4
+# CHECK-S-OBJ-ASM: blez a2, 4
+# CHECK-S-OBJ-NOALIAS-OBJ: bge zero, a2, 0x38
+# CHECK-S-OBJ-OBJ: blez a2, 0x38
 blez x12, 4
-# CHECK-S-OBJ-NOALIAS: bge a3, zero, 8
-# CHECK-S-OBJ: bgez a3, 8
+# CHECK-S-OBJ-NOALIAS-ASM: bge a3, zero, 8
+# CHECK-S-OBJ-ASM: bgez a3, 8
+# CHECK-S-OBJ-NOALIAS-OBJ: bge a3, zero, 0x40
+# CHECK-S-OBJ-OBJ: bgez a3, 0x40
 bgez x13, 8
-# CHECK-S-OBJ-NOALIAS: blt a4, zero, 12
-# CHECK-S-OBJ: bltz a4, 12
+# CHECK-S-OBJ-NOALIAS-ASM: blt a4, zero, 12
+# CHECK-S-OBJ-ASM: bltz a4, 12
+# CHECK-S-OBJ-NOALIAS-OBJ: blt a4, zero, 0x48
+# CHECK-S-OBJ-OBJ: bltz a4, 0x48
 bltz x14, 12
-# CHECK-S-OBJ-NOALIAS: blt zero, a5, 16
-# CHECK-S-OBJ: bgtz a5, 16
+# CHECK-S-OBJ-NOALIAS-ASM: blt zero, a5, 16
+# CHECK-S-OBJ-ASM: bgtz a5, 16
+# CHECK-S-OBJ-NOALIAS-OBJ: blt zero, a5, 0x50
+# CHECK-S-OBJ-OBJ: bgtz a5, 0x50
 bgtz x15, 16
 
 # Always output the canonical mnemonic for the pseudo branch instructions.
-# CHECK-S-OBJ-NOALIAS: blt a6, a5, 20
-# CHECK-S-OBJ: blt a6, a5, 20
+# CHECK-S-OBJ-NOALIAS-ASM: blt a6, a5, 20
+# CHECK-S-OBJ-ASM: blt a6, a5, 20
+# CHECK-S-OBJ-NOALIAS-OBJ: blt a6, a5, 0x58
+# CHECK-S-OBJ-OBJ: blt a6, a5, 0x58
 bgt x15, x16, 20
-# CHECK-S-OBJ-NOALIAS: bge a7, a6, 24
-# CHECK-S-OBJ: bge a7, a6, 24
+# CHECK-S-OBJ-NOALIAS-ASM: bge a7, a6, 24
+# CHECK-S-OBJ-ASM: bge a7, a6, 24
+# CHECK-S-OBJ-NOALIAS-OBJ: bge a7, a6, 0x60
+# CHECK-S-OBJ-OBJ: bge a7, a6, 0x60
 ble x16, x17, 24
-# CHECK-S-OBJ-NOALIAS: bltu s2, a7, 28
-# CHECK-S-OBJ: bltu s2, a7, 28
+# CHECK-S-OBJ-NOALIAS-ASM: bltu s2, a7, 28
+# CHECK-S-OBJ-ASM: bltu s2, a7, 28
+# CHECK-S-OBJ-NOALIAS-OBJ: bltu s2, a7, 0x68
+# CHECK-S-OBJ-OBJ: bltu s2, a7, 0x68
 bgtu x17, x18, 28
-# CHECK-S-OBJ-NOALIAS: bgeu s3, s2, 32
-# CHECK-S-OBJ: bgeu s3, s2, 32
+# CHECK-S-OBJ-NOALIAS-ASM: bgeu s3, s2, 32
+# CHECK-S-OBJ-ASM: bgeu s3, s2, 32
+# CHECK-S-OBJ-NOALIAS-OBJ: bgeu s3, s2, 0x70
+# CHECK-S-OBJ-OBJ: bgeu s3, s2, 0x70
 bleu x18, x19, 32
 
-# CHECK-S-OBJ-NOALIAS: jal zero, 2044
-# CHECK-S-OBJ: j 2044
+# CHECK-S-OBJ-NOALIAS-ASM: jal zero, 2044
+# CHECK-S-OBJ-ASM: j 2044
+# CHECK-S-OBJ-NOALIAS-OBJ: jal zero, 0x850
+# CHECK-S-OBJ-OBJ: j 0x850
 j 2044
 # CHECK-S-NOALIAS: jal zero, foo
 # CHECK-S: j foo
-# CHECK-OBJ-NOALIAS: jal zero, 0
-# CHECK-OBJ: j 0
+# CHECK-OBJ-NOALIAS-ASM: jal zero, 0
+# CHECK-OBJ-ASM: j 0
+# CHECK-OBJ-NOALIAS-OBJ: jal zero, 0x58
+# CHECK-OBJ-OBJ: j 0x58
 # CHECK-OBJ: R_RISCV_JAL foo
 j foo
 # CHECK-S-NOALIAS: jal zero, a0
 # CHECK-S: j a0
-# CHECK-OBJ-NOALIAS: jal zero, 0
-# CHECK-OBJ: j 0
+# CHECK-OBJ-NOALIAS-ASM: jal zero, 0
+# CHECK-OBJ-ASM: j 0
+# CHECK-OBJ-NOALIAS-OBJ: jal zero, 0x5c
+# CHECK-OBJ-OBJ: j 0x5c
 # CHECK-OBJ: R_RISCV_JAL a0
 j a0
 # CHECK-S-NOALIAS: [[LABEL:.L[[:alnum:]_]+]]:
 # CHECK-S-NOALIAS-NEXT: jal zero, [[LABEL]]
 # CHECK-S: [[LABEL:.L[[:alnum:]_]+]]:
 # CHECK-S-NEXT: j [[LABEL]]
-# CHECK-OBJ-NOALIAS: jal zero, 0
-# CHECK-OBJ: j 0
+# CHECK-OBJ-NOALIAS-ASM: jal zero, 0
+# CHECK-OBJ-ASM: j 0
+# CHECK-OBJ-NOALIAS-OBJ: jal zero, 0x60
+# CHECK-OBJ-OBJ: j 0x60
 j .
-# CHECK-S-OBJ-NOALIAS: jal ra, 2040
-# CHECK-S-OBJ: jal 2040
+# CHECK-S-OBJ-NOALIAS-ASM: jal ra, 2040
+# CHECK-S-OBJ-ASM: jal 2040
+# CHECK-S-OBJ-NOALIAS-OBJ: jal ra, 0x85c
+# CHECK-S-OBJ-OBJ: jal 0x85c
 jal 2040
 # CHECK-S-NOALIAS: jal ra, foo
 # CHECK-S: jal foo
-# CHECK-OBJ-NOALIAS: jal ra, 0
-# CHECK-OBJ: jal 0
+# CHECK-OBJ-NOALIAS-ASM: jal ra, 0
+# CHECK-OBJ-ASM: jal 0
+# CHECK-OBJ-NOALIAS-OBJ: jal ra, 0x68
+# CHECK-OBJ-OBJ: jal 0x68
 # CHECK-OBJ: R_RISCV_JAL foo
 jal foo
 # CHECK-S-NOALIAS: jal ra, a0
 # CHECK-S: jal a0
-# CHECK-OBJ-NOALIAS: jal ra, 0
-# CHECK-OBJ: jal 0
+# CHECK-OBJ-NOALIAS-ASM: jal ra, 0
+# CHECK-OBJ-ASM: jal 0
+# CHECK-OBJ-NOALIAS-OBJ: jal ra, 0x6c
+# CHECK-OBJ-OBJ: jal 0x6c
 # CHECK-OBJ: R_RISCV_JAL a0
 jal a0
 # CHECK-S-OBJ-NOALIAS: jalr zero, 0(s4)
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -855,8 +855,9 @@
           if (Rec->isSubClassOf("RegisterOperand") ||
               Rec->isSubClassOf("Operand")) {
             StringRef PrintMethod = Rec->getValueAsString("PrintMethod");
-            bool IsPCRel =
-                Rec->getValueAsString("OperandType") == "OPERAND_PCREL";
+            bool RequiresAddr =
+                Rec->getValueAsString("OperandType") == "OPERAND_PCREL" ||
+                Rec->getValueAsBit("PrintRequiresAddr");
             if (PrintMethod != "" && PrintMethod != "printOperand") {
               PrintMethodIdx = llvm::find_if(PrintMethods,
                                              [&](auto &X) {
@@ -864,7 +865,8 @@
                                              }) -
                                PrintMethods.begin();
               if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
-                PrintMethods.emplace_back(std::string(PrintMethod), IsPCRel);
+                PrintMethods.emplace_back(std::string(PrintMethod),
+                                          RequiresAddr);
             }
           }
 
diff --git a/llvm/utils/TableGen/AsmWriterInst.cpp b/llvm/utils/TableGen/AsmWriterInst.cpp
--- a/llvm/utils/TableGen/AsmWriterInst.cpp
+++ b/llvm/utils/TableGen/AsmWriterInst.cpp
@@ -183,7 +183,8 @@
         unsigned MIOp = OpInfo.MIOperandNo;
         Operands.emplace_back(OpInfo.PrinterMethodName, MIOp, Modifier,
                               AsmWriterOperand::isMachineInstrOperand,
-                              OpInfo.OperandType == "MCOI::OPERAND_PCREL");
+                              OpInfo.OperandType == "MCOI::OPERAND_PCREL" ||
+                                  OpInfo.PrintRequiresAddr);
       }
       LastEmitted = VarEnd;
     }
diff --git a/llvm/utils/TableGen/CodeGenInstruction.h b/llvm/utils/TableGen/CodeGenInstruction.h
--- a/llvm/utils/TableGen/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/CodeGenInstruction.h
@@ -86,6 +86,10 @@
       /// the asmprinter.
       std::string PrinterMethodName;
 
+      /// PrinterMethodRequiresAddr - The method used to print operands of this
+      /// type requires the program address to print.
+      bool PrintRequiresAddr;
+
       /// EncoderMethodName - The method used to get the machine operand value
       /// for binary encoding. "getMachineOpValue" by default.
       std::string EncoderMethodName;
@@ -117,12 +121,11 @@
       std::vector<ConstraintInfo> Constraints;
 
       OperandInfo(Record *R, const std::string &N, const std::string &PMN,
-                  const std::string &EMN, const std::string &OT, unsigned MION,
-                  unsigned MINO, DagInit *MIOI)
-      : Rec(R), Name(N), PrinterMethodName(PMN), EncoderMethodName(EMN),
-        OperandType(OT), MIOperandNo(MION), MINumOperands(MINO),
-        MIOperandInfo(MIOI) {}
-
+                  bool PRA, const std::string &EMN, const std::string &OT,
+                  unsigned MION, unsigned MINO, DagInit *MIOI)
+          : Rec(R), Name(N), PrinterMethodName(PMN), PrintRequiresAddr(PRA),
+            EncoderMethodName(EMN), OperandType(OT), MIOperandNo(MION),
+            MINumOperands(MINO), MIOperandInfo(MIOI) {}
 
       /// getTiedOperand - If this operand is tied to another one, return the
       /// other operand number.  Otherwise, return -1.
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/CodeGenInstruction.cpp
--- a/llvm/utils/TableGen/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/CodeGenInstruction.cpp
@@ -74,6 +74,7 @@
 
     Record *Rec = Arg->getDef();
     std::string PrintMethod = "printOperand";
+    bool PrintRequiresAddr = false;
     std::string EncoderMethod;
     std::string OperandType = "OPERAND_UNKNOWN";
     std::string OperandNamespace = "MCOI";
@@ -86,6 +87,7 @@
       EncoderMethod = std::string(Rec->getValueAsString("EncoderMethod"));
     } else if (Rec->isSubClassOf("Operand")) {
       PrintMethod = std::string(Rec->getValueAsString("PrintMethod"));
+      PrintRequiresAddr = Rec->getValueAsBit("PrintRequiresAddr");
       OperandType = std::string(Rec->getValueAsString("OperandType"));
       OperandNamespace = std::string(Rec->getValueAsString("OperandNamespace"));
       // If there is an explicit encoder method, use it.
@@ -131,7 +133,7 @@
                           " has the same name as a previous operand!");
 
     OperandList.emplace_back(
-        Rec, std::string(ArgName), std::string(PrintMethod),
+        Rec, std::string(ArgName), std::string(PrintMethod), PrintRequiresAddr,
         std::string(EncoderMethod), OperandNamespace + "::" + OperandType,
         MIOperandNo, NumOps, MIOpInfo);
     MIOperandNo += NumOps;