Index: llvm/docs/LangRef.rst =================================================================== --- llvm/docs/LangRef.rst +++ llvm/docs/LangRef.rst @@ -14826,6 +14826,122 @@ %r2 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) ; yields float:r2 = (a * b) + c +Hardware-Loop Intrinsics +------------------------ + +LLVM support several intrinsics to mark a loop as a hardware-loop. They are +hints to the backend which are required to lower these intrinsics further to target +specific instructions, or revert the hardware-loop to a normal loop if +restriction are not met and a hardware-loop can't be generated. + + +'``llvm.set.loop.iterations.*``' Intrinsic +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Syntax: +""""""" +This is an overloaded intrinsic. + +:: + + declare void @llvm.set.loop.iterations.i32(i32) + declare void @llvm.set.loop.iterations.i64(i64) + +Overview: +""""""""" + +These intrinsics can be used to specify the number of iterations that the next +(vector) loop will execute. They are placed in the loop preheader, and are marked +as ``IntrNoDuplicate`` to avoid optimizers duplicating these instructions. + +Arguments: +"""""""""" +The integer operand is the loop iteration count of the hardware-loop. I.e., +the number of executions of the loop body, and not e.g. the loop back-edge +taken count. + + +'``llvm.test.set.loop.iterations.*``' Intrinsic +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Syntax: +""""""" +This is an overloaded intrinsic. + +:: + + declare void @llvm.test.set.loop.iterations.i32(i32) + declare void @llvm.tetst.set.loop.iterations.i64(i64) + +Overview: +""""""""" + +These intrinsics can be used to specify the number of iterations that the next +(vector) loop will execute, and also test that the given count is not zero, +allowing it to control entry to a while-loop. They are placed in the loop +preheader, and are marked as ``IntrNoDuplicate`` to avoid optimizers +duplicating these instructions. + +Arguments: +"""""""""" +The integer operand is the loop iteration count of the hardware-loop. I.e., +the number of executions of the loop body, and not e.g. the loop back-edge +taken count. + + +'``llvm.loop.decrement.reg.*``' Intrinsic +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Syntax: +""""""" +This is an overloaded intrinsic. + +:: + + declare i32 @llvm.loop.decrement.reg.i32(i32, i32) + declare i64 @llvm.loop.decrement.reg.i64(i64, i64) + +Overview: +""""""""" + +The '``llvm.loop.decrement.reg..*``' intrinsics do an integer ``SUB`` of its +two operands. They return the remaining number of iterations still to be executed, +and can be used together with a ``PHI``, ``ICMP`` and ``BR`` to control the number +of iterations executed. Any optimisations are allowed to treat it is a ``SUB``, and +it is supported by SCEV, so it's the backends responsibility to handle cases where it +may be optimised, but are not allowed to duplicate these intrinsic calls. + + +Arguments: +"""""""""" +Like a ``SUB`` instruction, both arguments must have identical integer types. +The first operand is the loop iteration counter. The second operand is the +maximum number of elements processed in an iteration. + + +'``llvm.loop.decrement.*``' Intrinsic +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Syntax: +""""""" +This is an overloaded intrinsic. + +:: + + declare i1 @llvm.loop.decrement.reg.i32(i32) + declare i1 @llvm.loop.decrement.reg.i64(i64) + +Overview: +""""""""" + +The '``llvm.loop.decrement.*``' intrinsics decrement the loop iteration counter +and return false if the loop should exit. + +Arguments: +"""""""""" +The integer argument is used to decrement the loop iteration counter. + + Experimental Vector Reduction Intrinsics ---------------------------------------- Index: llvm/include/llvm/IR/Intrinsics.td =================================================================== --- llvm/include/llvm/IR/Intrinsics.td +++ llvm/include/llvm/IR/Intrinsics.td @@ -1413,32 +1413,18 @@ //===---------- Intrinsics to control hardware supported loops ----------===// -// Specify that the value given is the number of iterations that the next loop -// will execute. def int_set_loop_iterations : Intrinsic<[], [llvm_anyint_ty], [IntrNoDuplicate]>; -// Specify that the value given is the number of iterations that the next loop -// will execute. Also test that the given count is not zero, allowing it to -// control entry to a 'while' loop. def int_test_set_loop_iterations : Intrinsic<[llvm_i1_ty], [llvm_anyint_ty], [IntrNoDuplicate]>; -// Decrement loop counter by the given argument. Return false if the loop -// should exit. def int_loop_decrement : Intrinsic<[llvm_i1_ty], [llvm_anyint_ty], [IntrNoDuplicate]>; -// Decrement the first operand (the loop counter) by the second operand (the -// maximum number of elements processed in an iteration). Return the remaining -// number of iterations still to be executed. This is effectively a sub which -// can be used with a phi, icmp and br to control the number of iterations -// executed, as usual. Any optimisations are allowed to treat it is a sub, and -// it's scevable, so it's the backends responsibility to handle cases where it -// may be optimised. def int_loop_decrement_reg : Intrinsic<[llvm_anyint_ty], - [llvm_anyint_ty, llvm_anyint_ty], [IntrNoDuplicate]>; + [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoDuplicate]>; //===----- Intrinsics that are used to provide predicate information -----===// Index: llvm/lib/CodeGen/HardwareLoops.cpp =================================================================== --- llvm/lib/CodeGen/HardwareLoops.cpp +++ llvm/lib/CodeGen/HardwareLoops.cpp @@ -475,9 +475,7 @@ Function *DecFunc = Intrinsic::getDeclaration(M, Intrinsic::loop_decrement_reg, - { EltsRem->getType(), EltsRem->getType(), - LoopDecrement->getType() - }); + { EltsRem->getType() }); Value *Ops[] = { EltsRem, LoopDecrement }; Value *Call = CondBuilder.CreateCall(DecFunc, Ops); Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/clear-maskedinsts.ll =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/clear-maskedinsts.ll +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/clear-maskedinsts.ll @@ -33,7 +33,7 @@ ; CHECK-NEXT: [[TMP7]] = sub i32 [[TMP5]], 4 ; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[BROADCAST_SPLAT72]], <4 x i32>* [[LSR_IV911]], i32 4, <4 x i1> [[TMP6]]) ; CHECK-NEXT: [[SCEVGEP10]] = getelementptr i32, i32* [[LSR_IV9]], i32 4 -; CHECK-NEXT: [[TMP8]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP4]], i32 1) +; CHECK-NEXT: [[TMP8]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP4]], i32 1) ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 ; CHECK-NEXT: br i1 [[TMP9]], label [[VECTOR_BODY]], label [[FOR_COND_CLEANUP]] ; CHECK: vector.body75: @@ -59,7 +59,7 @@ ; CHECK-NEXT: [[SCEVGEP]] = getelementptr i32, i32* [[LSR_IV]], i32 4 ; CHECK-NEXT: [[SCEVGEP4]] = getelementptr i32, i32* [[LSR_IV3]], i32 4 ; CHECK-NEXT: [[SCEVGEP7]] = getelementptr i32, i32* [[LSR_IV6]], i32 4 -; CHECK-NEXT: [[TMP15]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP10]], i32 1) +; CHECK-NEXT: [[TMP15]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP10]], i32 1) ; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 ; CHECK-NEXT: br i1 [[TMP16]], label [[VECTOR_BODY75]], label [[FOR_COND_CLEANUP]] ; CHECK: for.cond.cleanup: @@ -104,7 +104,7 @@ call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %broadcast.splat72, <4 x i32>* %lsr.iv911, i32 4, <4 x i1> %7) %index.next = add i32 %index, 4 %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 4 - %8 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %4, i32 1) + %8 = call i32 @llvm.loop.decrement.reg.i32(i32 %4, i32 1) %9 = icmp ne i32 %8, 0 br i1 %9, label %vector.body, label %for.cond.cleanup @@ -131,7 +131,7 @@ %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 %scevgep4 = getelementptr i32, i32* %lsr.iv3, i32 4 %scevgep7 = getelementptr i32, i32* %lsr.iv6, i32 4 - %15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %10, i32 1) + %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %10, i32 1) %16 = icmp ne i32 %15, 0 br i1 %16, label %vector.body75, label %for.cond.cleanup @@ -142,4 +142,4 @@ declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) declare void @llvm.set.loop.iterations.i32(i32) -declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) +declare i32 @llvm.loop.decrement.reg.i32(i32, i32) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll @@ -40,7 +40,7 @@ ; CHECK-NEXT: [[TMP13:%.*]] = mul nsw <4 x i32> [[TMP12]], [[TMP9]] ; CHECK-NEXT: [[TMP14]] = add nsw <4 x i32> [[TMP13]], [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4 -; CHECK-NEXT: [[TMP15]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP5]], i32 1) +; CHECK-NEXT: [[TMP15]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP5]], i32 1) ; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 ; CHECK-NEXT: br i1 [[TMP16]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK]] ; CHECK: middle.block: @@ -97,7 +97,7 @@ %tmp13 = mul nsw <4 x i32> %tmp12, %tmp9 %tmp14 = add nsw <4 x i32> %tmp13, %vec.phi %index.next = add i32 %index, 4 - %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp5, i32 1) + %tmp15 = call i32 @llvm.loop.decrement.reg.i32(i32 %tmp5, i32 1) %tmp16 = icmp ne i32 %tmp15, 0 br i1 %tmp16, label %vector.body, label %middle.block @@ -150,7 +150,7 @@ ; CHECK-NEXT: [[TMP11:%.*]] = mul nsw <4 x i32> [[WIDE_MASKED_LOAD29]], [[WIDE_MASKED_LOAD]] ; CHECK-NEXT: [[TMP12]] = add nsw <4 x i32> [[VEC_PHI]], [[TMP11]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4 -; CHECK-NEXT: [[TMP13]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP5]], i32 1) +; CHECK-NEXT: [[TMP13]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP5]], i32 1) ; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 ; CHECK-NEXT: br i1 [[TMP14]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK]] ; CHECK: middle.block: @@ -205,7 +205,7 @@ %tmp11 = mul nsw <4 x i32> %wide.masked.load29, %wide.masked.load %tmp12 = add nsw <4 x i32> %vec.phi, %tmp11 %index.next = add i32 %index, 4 - %tmp13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp5, i32 1) + %tmp13 = call i32 @llvm.loop.decrement.reg.i32(i32 %tmp5, i32 1) %tmp14 = icmp ne i32 %tmp13, 0 br i1 %tmp14, label %vector.body, label %middle.block @@ -234,7 +234,7 @@ declare void @llvm.set.loop.iterations.i32(i32) #2 ; Function Attrs: noduplicate nounwind -declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 +declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #2 attributes #0 = { argmemonly nounwind readonly willreturn } attributes #1 = { nounwind readnone willreturn } Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-const.ll =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-const.ll +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-const.ll @@ -24,7 +24,7 @@ ; CHECK-NEXT: [[SCEVGEP]] = getelementptr i32, i32* [[LSR_IV]], i32 4 ; CHECK-NEXT: [[SCEVGEP12]] = getelementptr i32, i32* [[LSR_IV11]], i32 4 ; CHECK-NEXT: [[SCEVGEP15]] = getelementptr i32, i32* [[LSR_IV14]], i32 4 -; CHECK-NEXT: [[TMP5]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP0]], i32 1) +; CHECK-NEXT: [[TMP5]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP0]], i32 1) ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 ; CHECK-NEXT: br i1 [[TMP6]], label [[VECTOR_BODY]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: for.cond.cleanup: @@ -55,7 +55,7 @@ %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 %scevgep12 = getelementptr i32, i32* %lsr.iv11, i32 4 %scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4 - %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) + %3 = call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) %4 = icmp ne i32 %3, 0 br i1 %4, label %vector.body, label %for.cond.cleanup @@ -86,7 +86,7 @@ ; CHECK-NEXT: [[SCEVGEP]] = getelementptr i32, i32* [[LSR_IV]], i32 4 ; CHECK-NEXT: [[SCEVGEP12]] = getelementptr i32, i32* [[LSR_IV11]], i32 4 ; CHECK-NEXT: [[SCEVGEP15]] = getelementptr i32, i32* [[LSR_IV14]], i32 4 -; CHECK-NEXT: [[TMP2]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP0]], i32 1) +; CHECK-NEXT: [[TMP2]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP0]], i32 1) ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[TMP3]], label [[VECTOR_BODY]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: for.cond.cleanup: @@ -111,7 +111,7 @@ %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 %scevgep12 = getelementptr i32, i32* %lsr.iv11, i32 4 %scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4 - %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) + %2 = call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) %3 = icmp ne i32 %2, 0 br i1 %3, label %vector.body, label %for.cond.cleanup @@ -146,7 +146,7 @@ ; CHECK-NEXT: [[SCEVGEP]] = getelementptr i32, i32* [[LSR_IV]], i32 4 ; CHECK-NEXT: [[SCEVGEP12]] = getelementptr i32, i32* [[LSR_IV11]], i32 4 ; CHECK-NEXT: [[SCEVGEP15]] = getelementptr i32, i32* [[LSR_IV14]], i32 4 -; CHECK-NEXT: [[TMP3]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP0]], i32 1) +; CHECK-NEXT: [[TMP3]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP0]], i32 1) ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 ; CHECK-NEXT: br i1 [[TMP4]], label [[VECTOR_BODY]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: for.cond.cleanup: @@ -179,7 +179,7 @@ %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 %scevgep12 = getelementptr i32, i32* %lsr.iv11, i32 4 %scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4 - %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) + %3 = call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) %4 = icmp ne i32 %3, 0 br i1 %4, label %vector.body, label %for.cond.cleanup @@ -215,7 +215,7 @@ ; CHECK-NEXT: [[SCEVGEP]] = getelementptr i32, i32* [[LSR_IV]], i32 4 ; CHECK-NEXT: [[SCEVGEP12]] = getelementptr i32, i32* [[LSR_IV11]], i32 4 ; CHECK-NEXT: [[SCEVGEP15]] = getelementptr i32, i32* [[LSR_IV14]], i32 4 -; CHECK-NEXT: [[TMP3]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP0]], i32 1) +; CHECK-NEXT: [[TMP3]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP0]], i32 1) ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 ; CHECK-NEXT: br i1 [[TMP4]], label [[VECTOR_BODY]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: for.cond.cleanup: @@ -248,7 +248,7 @@ %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 %scevgep12 = getelementptr i32, i32* %lsr.iv11, i32 4 %scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4 - %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) + %3 = call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) %4 = icmp ne i32 %3, 0 br i1 %4, label %vector.body, label %for.cond.cleanup @@ -282,7 +282,7 @@ ; CHECK-NEXT: [[SCEVGEP]] = getelementptr i32, i32* [[LSR_IV]], i32 4 ; CHECK-NEXT: [[SCEVGEP12]] = getelementptr i32, i32* [[LSR_IV11]], i32 4 ; CHECK-NEXT: [[SCEVGEP15]] = getelementptr i32, i32* [[LSR_IV14]], i32 4 -; CHECK-NEXT: [[TMP3]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[TMP0]], i32 1) +; CHECK-NEXT: [[TMP3]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP0]], i32 1) ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 ; CHECK-NEXT: br i1 [[TMP4]], label [[VECTOR_BODY]], label [[FOR_COND_CLEANUP:%.*]] ; CHECK: for.cond.cleanup: @@ -315,7 +315,7 @@ %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 %scevgep12 = getelementptr i32, i32* %lsr.iv11, i32 4 %scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4 - %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) + %3 = call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) %4 = icmp ne i32 %3, 0 br i1 %4, label %vector.body, label %for.cond.cleanup @@ -325,5 +325,5 @@ declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #1 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #2 -declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 , i32 ) +declare i32 @llvm.loop.decrement.reg.i32(i32 , i32 ) declare void @llvm.set.loop.iterations.i32(i32) Index: llvm/test/Transforms/HardwareLoops/ARM/calls.ll =================================================================== --- llvm/test/Transforms/HardwareLoops/ARM/calls.ll +++ llvm/test/Transforms/HardwareLoops/ARM/calls.ll @@ -39,7 +39,7 @@ ; CHECK-LABEL: test_target_specific ; CHECK: call void @llvm.set.loop.iterations.i32(i32 50) ; CHECK: [[COUNT:%[^ ]+]] = phi i32 [ 50, %entry ], [ [[LOOP_DEC:%[^ ]+]], %loop ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[COUNT]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[COUNT]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %loop, label %exit @@ -133,7 +133,7 @@ ; CHECK-MVE-NOT: call void @llvm.set.loop.iterations ; CHECK-MVEFP: call void @llvm.set.loop.iterations.i32(i32 100) ; CHECK-MVEFP: [[COUNT:%[^ ]+]] = phi i32 [ 100, %entry ], [ [[LOOP_DEC:%[^ ]+]], %loop ] -; CHECK-MVEFP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[COUNT]], i32 1) +; CHECK-MVEFP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[COUNT]], i32 1) ; CHECK-MVEFP: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-MVEFP: br i1 [[CMP]], label %loop, label %exit define <4 x float> @test_fabs_vec(<4 x float>* %a) { @@ -201,7 +201,7 @@ ; CHECK-FP: call void @llvm.set.loop.iterations ; CHECK-MVEFP: call void @llvm.set.loop.iterations.i32(i32 100) ; CHECK-MVEFP: [[COUNT:%[^ ]+]] = phi i32 [ 100, %entry ], [ [[LOOP_DEC:%[^ ]+]], %loop ] -; CHECK-MVEFP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[COUNT]], i32 1) +; CHECK-MVEFP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[COUNT]], i32 1) ; CHECK-MVEFP: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-MVEFP: br i1 [[CMP]], label %loop, label %exit define void @test_sqrt(float* %a, float* %b) { @@ -313,7 +313,7 @@ ; CHECK-MVEFP: call void @llvm.set.loop.iterations ; CHECK-MVE: call void @llvm.set.loop.iterations.i32(i32 100) ; CHECK-MVE: [[COUNT:%[^ ]+]] = phi i32 [ 100, %entry ], [ [[LOOP_DEC:%[^ ]+]], %loop ] -; CHECK-MVE: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[COUNT]], i32 1) +; CHECK-MVE: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[COUNT]], i32 1) ; CHECK-MVE: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-MVE: br i1 [[CMP]], label %loop, label %exit define arm_aapcs_vfpcc void @test_masked_i32(<4 x i1> %mask, <4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c, <4 x i32> %passthru) { @@ -340,7 +340,7 @@ ; CHECK-MVEFP: call void @llvm.set.loop.iterations ; CHECK-MVE: call void @llvm.set.loop.iterations.i32(i32 100) ; CHECK-MVE: [[COUNT:%[^ ]+]] = phi i32 [ 100, %entry ], [ [[LOOP_DEC:%[^ ]+]], %loop ] -; CHECK-MVE: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[COUNT]], i32 1) +; CHECK-MVE: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[COUNT]], i32 1) ; CHECK-MVE: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-MVE: br i1 [[CMP]], label %loop, label %exit define arm_aapcs_vfpcc void @test_masked_f32(<4 x i1> %mask, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float> %passthru) { @@ -367,7 +367,7 @@ ; CHECK-MVEFP: call void @llvm.set.loop.iterations ; CHECK-MVE: call void @llvm.set.loop.iterations.i32(i32 100) ; CHECK-MVE: [[COUNT:%[^ ]+]] = phi i32 [ 100, %entry ], [ [[LOOP_DEC:%[^ ]+]], %loop ] -; CHECK-MVE: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[COUNT]], i32 1) +; CHECK-MVE: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[COUNT]], i32 1) ; CHECK-MVE: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-MVE: br i1 [[CMP]], label %loop, label %exit define arm_aapcs_vfpcc void @test_gather_scatter(<4 x i1> %mask, <4 x float*> %a, <4 x float*> %b, <4 x float*> %c, <4 x float> %passthru) { Index: llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll =================================================================== --- llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll +++ llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll @@ -12,7 +12,7 @@ ; CHECK: while.body: ; CHECK: [[REM:%[^ ]+]] = phi i32 [ %n, %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %while.end.loopexit @@ -51,7 +51,7 @@ ; CHECK: while.body: ; CHECK: [[REM:%[^ ]+]] = phi i32 [ %n, %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %while.end.loopexit @@ -90,7 +90,7 @@ ; CHECK: while.body: ; CHECK: [[REM:%[^ ]+]] = phi i32 [ %n, %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %while.end.loopexit @@ -129,7 +129,7 @@ ; CHECK: while.body: ; CHECK: [[REM:%[^ ]+]] = phi i32 [ %n, %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %while.end.loopexit Index: llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll =================================================================== --- llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll +++ llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll @@ -13,7 +13,7 @@ ; CHECK-FP-NEXT: br label %while.body ; CHECK-FP: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %if.end4 ] -; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK-FP: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-FP: br i1 [[CMP]], label %while.body, label %cleanup.loopexit @@ -63,7 +63,7 @@ ; CHECK-FP-NEXT: br label %while.body ; CHECK-FP: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %if.end4 ] -; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK-FP: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-FP: br i1 [[CMP]], label %while.body, label %cleanup.loopexit @@ -115,7 +115,7 @@ ; CHECK-NEXT: br label %while.body ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %if.end4 ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %cleanup.loopexit @@ -167,7 +167,7 @@ ; CHECK-SOFT-NOT: call i32 @llvm.loop.decrement ; CHECK-FP: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %if.end4 ] -; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK-FP: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK-FP: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-FP: br i1 [[CMP]], label %while.body, label %cleanup.loopexit Index: llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll =================================================================== --- llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll +++ llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll @@ -12,7 +12,7 @@ ; CHECK: br label %while.body ; CHECK: [[REM:%[^ ]+]] = phi i32 [ %n, %entry ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %while.end @@ -53,7 +53,7 @@ ; CHECK: br label %while.body ; CHECK: [[REM:%[^ ]+]] = phi i32 [ %n, %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %while.end.loopexit @@ -103,7 +103,7 @@ ; CHECK: br label %while.body ; CHECK: while.body: ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %while.end.loopexit @@ -156,7 +156,7 @@ ; CHECK: br label %while.body ; CHECK: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.lr.ph ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body, label %while.end.loopexit Index: llvm/test/Transforms/HardwareLoops/ARM/structure.ll =================================================================== --- llvm/test/Transforms/HardwareLoops/ARM/structure.ll +++ llvm/test/Transforms/HardwareLoops/ARM/structure.ll @@ -58,7 +58,7 @@ ; CHECK: br label %while.body3.us ; CHECK: [[REM:%[^ ]+]] = phi i32 [ %N, %while.cond1.preheader.us ], [ [[LOOP_DEC:%[^ ]+]], %while.body3.us ] -; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %while.body3.us, label %while.cond1.while.end_crit_edge.us @@ -105,7 +105,7 @@ ; CHECK-LABEL: pre_existing ; CHECK: llvm.set.loop.iterations ; CHECK-NOT: llvm.set.loop.iterations -; CHECK: call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) +; CHECK: call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) ; CHECK-NOT: call i32 @llvm.loop.decrement.reg define i32 @pre_existing(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) { entry: @@ -120,7 +120,7 @@ %1 = load i32, i32* %q.addr.05, align 4 %incdec.ptr1 = getelementptr inbounds i32, i32* %p.addr.04, i32 1 store i32 %1, i32* %p.addr.04, align 4 - %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) + %2 = call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) %3 = icmp ne i32 %2, 0 br i1 %3, label %while.body, label %while.end @@ -131,7 +131,7 @@ ; CHECK-LABEL: pre_existing_test_set ; CHECK: call i1 @llvm.test.set.loop.iterations ; CHECK-NOT: llvm.set{{.*}}.loop.iterations -; CHECK: call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) +; CHECK: call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) ; CHECK-NOT: call i32 @llvm.loop.decrement.reg define i32 @pre_existing_test_set(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) { entry: @@ -149,7 +149,7 @@ %1 = load i32, i32* %q.addr.05, align 4 %incdec.ptr1 = getelementptr inbounds i32, i32* %p.addr.04, i32 1 store i32 %1, i32* %p.addr.04, align 4 - %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) + %2 = call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) %3 = icmp ne i32 %2, 0 br i1 %3, label %while.body, label %while.end @@ -161,7 +161,7 @@ ; CHECK-NOT: llvm.set.loop.iterations ; CHECK: while.cond1.preheader.us: ; CHECK: call void @llvm.set.loop.iterations.i32(i32 %N) -; CHECK: call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) +; CHECK: call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) ; CHECK: br i1 ; CHECK-NOT: call i32 @llvm.loop.decrement define void @pre_existing_inner(i32* nocapture %A, i32 %N) { @@ -182,7 +182,7 @@ %arrayidx.us = getelementptr inbounds i32, i32* %A, i32 %add.us store i32 %add.us, i32* %arrayidx.us, align 4 %inc.us = add nuw i32 %j.019.us, 1 - %1 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) + %1 = call i32 @llvm.loop.decrement.reg.i32(i32 %0, i32 1) %2 = icmp ne i32 %1, 0 br i1 %2, label %while.body3.us, label %while.cond1.while.end_crit_edge.us @@ -278,7 +278,7 @@ ; CHECK: br label %for.body ; CHECK: for.body: ; CHECK: for.inc: -; CHECK: [[LOOP_DEC:%[^ ]+]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32 +; CHECK: [[LOOP_DEC:%[^ ]+]] = call i32 @llvm.loop.decrement.reg.i32( ; CHECK: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK: br i1 [[CMP]], label %for.body, label %for.cond.cleanup define i32 @search(i8* nocapture readonly %c, i32 %N) { @@ -323,7 +323,7 @@ ; CHECK-LABEL: unroll_inc_int ; CHECK: call void @llvm.set.loop.iterations.i32(i32 %N) -; CHECK: call i32 @llvm.loop.decrement.reg.i32.i32.i32( +; CHECK: call i32 @llvm.loop.decrement.reg.i32( ; TODO: We should be able to support the unrolled loop body. ; CHECK-UNROLL-LABEL: unroll_inc_int @@ -361,7 +361,7 @@ ; CHECK-LABEL: unroll_inc_unsigned ; CHECK: call i1 @llvm.test.set.loop.iterations.i32(i32 %N) -; CHECK: call i32 @llvm.loop.decrement.reg.i32.i32.i32( +; CHECK: call i32 @llvm.loop.decrement.reg.i32( ; CHECK-LLC-LABEL: unroll_inc_unsigned: ; CHECK-LLC: wls lr, r3, [[EXIT:.LBB[0-9_]+]] @@ -405,7 +405,7 @@ ; CHECK-LABEL: unroll_dec_int ; CHECK: call void @llvm.set.loop.iterations.i32(i32 %N) -; CHECK: call i32 @llvm.loop.decrement.reg.i32.i32.i32( +; CHECK: call i32 @llvm.loop.decrement.reg.i32( ; TODO: An unnecessary register is being held to hold COUNT, lr should just ; be used instead. @@ -449,5 +449,5 @@ declare void @llvm.set.loop.iterations.i32(i32) #0 declare i1 @llvm.test.set.loop.iterations.i32(i32) #0 -declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 +declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #0 Index: llvm/test/Transforms/HardwareLoops/scalar-while.ll =================================================================== --- llvm/test/Transforms/HardwareLoops/scalar-while.ll +++ llvm/test/Transforms/HardwareLoops/scalar-while.ll @@ -21,7 +21,7 @@ ; CHECK: br label %while.body ; CHECK-REGDEC: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK-REGDEC: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK-REGDEC: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK-REGDEC: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-REGDEC: br i1 [[CMP]], label %while.body, label %while.end @@ -47,7 +47,7 @@ ; CHECK: br label %while.body ; CHECK-REGDEC: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK-REGDEC: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK-REGDEC: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK-REGDEC: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-REGDEC: br i1 [[CMP]], label %while.body, label %while.end @@ -92,7 +92,7 @@ ; CHECK: br label %while.body ; CHECK-REGDEC: [[REM:%[^ ]+]] = phi i32 [ [[COUNT]], %while.body.preheader ], [ [[LOOP_DEC:%[^ ]+]], %while.body ] -; CHECK-REGDEC: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK-REGDEC: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK-REGDEC: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-REGDEC: br i1 [[CMP]], label %while.body, label %while.end @@ -200,7 +200,7 @@ ; CHECK-DEC: [[LOOP_DEC:%[^ ]+]] = call i1 @llvm.loop.decrement.i32(i32 1) ; CHECK-REGDEC: [[REM:%[^ ]+]] = phi i32 [ %N, %while.cond1.preheader.us ], [ [[LOOP_DEC:%[^ ]+]], %while.body3.us ] -; CHECK-REGDEC: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[REM]], i32 1) +; CHECK-REGDEC: [[LOOP_DEC]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[REM]], i32 1) ; CHECK-REGDEC: [[CMP:%[^ ]+]] = icmp ne i32 [[LOOP_DEC]], 0 ; CHECK-REGDEC: br i1 [[CMP]], label %while.body3.us, label %while.cond1.while.end_crit_edge.us Index: llvm/test/Transforms/IndVarSimplify/lftr.ll =================================================================== --- llvm/test/Transforms/IndVarSimplify/lftr.ll +++ llvm/test/Transforms/IndVarSimplify/lftr.ll @@ -159,7 +159,7 @@ ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[I:%.*]] = phi i32 [ 10, [[ENTRY:%.*]] ], [ [[I_NEXT:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[I_NEXT]] = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 [[I]], i32 1) +; CHECK-NEXT: [[I_NEXT]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[I]], i32 1) ; CHECK-NEXT: store i32 [[I]], i32* @A ; CHECK-NEXT: [[I2:%.*]] = mul i32 [[I]], [[I]] ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp sgt i32 [[I2]], 0 @@ -172,7 +172,7 @@ loop: %i = phi i32 [ 10, %entry ], [ %i.next, %loop ] - %i.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %i, i32 1) + %i.next = call i32 @llvm.loop.decrement.reg.i32(i32 %i, i32 1) store i32 %i, i32* @A %i2 = mul i32 %i, %i %c = icmp sgt i32 %i2, 0 @@ -657,5 +657,5 @@ } -declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) +declare i32 @llvm.loop.decrement.reg.i32(i32, i32)