Index: llvm/include/llvm/CodeGen/MachineFunction.h =================================================================== --- llvm/include/llvm/CodeGen/MachineFunction.h +++ llvm/include/llvm/CodeGen/MachineFunction.h @@ -99,9 +99,10 @@ /// supplied allocator. /// /// This function can be overridden in a derive class. - template - static Ty *create(BumpPtrAllocator &Allocator, MachineFunction &MF) { - return new (Allocator.Allocate()) Ty(MF); + template + static Ty *create(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) { + return new (Allocator.Allocate()) Ty(F, STI); } template @@ -753,14 +754,12 @@ /// template Ty *getInfo() { - if (!MFInfo) - MFInfo = Ty::template create(Allocator, *this); return static_cast(MFInfo); } template const Ty *getInfo() const { - return const_cast(this)->getInfo(); + return static_cast(MFInfo); } template Ty *cloneInfo(const Ty &Old) { Index: llvm/include/llvm/Target/TargetMachine.h =================================================================== --- llvm/include/llvm/Target/TargetMachine.h +++ llvm/include/llvm/Target/TargetMachine.h @@ -18,6 +18,8 @@ #include "llvm/ADT/Triple.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/PassManager.h" +#include "llvm/Pass.h" +#include "llvm/Support/Allocator.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Error.h" #include "llvm/Support/PGOOptions.h" @@ -64,6 +66,7 @@ } using legacy::PassManagerBase; +struct MachineFunctionInfo; namespace yaml { struct MachineFunctionInfo; } @@ -137,6 +140,13 @@ return nullptr; } + /// Create the target's instance of MachineFunctionInfo + virtual MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return nullptr; + } + /// Allocate and return a default initialized instance of the YAML /// representation for the MachineFunctionInfo. virtual yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const { Index: llvm/lib/CodeGen/MachineFunction.cpp =================================================================== --- llvm/lib/CodeGen/MachineFunction.cpp +++ llvm/lib/CodeGen/MachineFunction.cpp @@ -186,7 +186,8 @@ else RegInfo = nullptr; - MFInfo = nullptr; + MFInfo = Target.createMachineFunctionInfo(Allocator, F, STI); + // We can realign the stack if the target supports it and the user hasn't // explicitly asked us not to. bool CanRealignSP = STI->getFrameLowering()->isStackRealignable() && Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -611,7 +611,7 @@ BuildMI(MBB, InsertPt, DL, CFIDesc).addCFIIndex(CFIIndex); // Flip the RA sign state. - if (MFI.shouldSignReturnAddress()) { + if (MFI.shouldSignReturnAddress(MF)) { CFIIndex = MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr)); BuildMI(MBB, InsertPt, DL, CFIDesc).addCFIIndex(CFIIndex); } @@ -1363,7 +1363,7 @@ .addImm(-8) .setMIFlag(MachineInstr::FrameDestroy); - if (MF.getInfo()->needsAsyncDwarfUnwindInfo()) { + if (MF.getInfo()->needsAsyncDwarfUnwindInfo(MF)) { unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, 18)); BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -1382,7 +1382,7 @@ const TargetInstrInfo *TII = Subtarget.getInstrInfo(); MachineModuleInfo &MMI = MF.getMMI(); AArch64FunctionInfo *AFI = MF.getInfo(); - bool EmitCFI = AFI->needsDwarfUnwindInfo(); + bool EmitCFI = AFI->needsDwarfUnwindInfo(MF); bool HasFP = hasFP(MF); bool NeedsWinCFI = needsWinCFI(MF); bool HasWinCFI = false; @@ -1402,9 +1402,9 @@ const auto &MFnI = *MF.getInfo(); if (needsShadowCallStackPrologueEpilogue(MF)) emitShadowCallStackPrologue(*TII, MF, MBB, MBBI, DL, NeedsWinCFI, - MFnI.needsDwarfUnwindInfo()); + MFnI.needsDwarfUnwindInfo(MF)); - if (MFnI.shouldSignReturnAddress()) { + if (MFnI.shouldSignReturnAddress(MF)) { unsigned PACI; if (MFnI.shouldSignWithBKey()) { BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY)) @@ -1876,7 +1876,7 @@ static void InsertReturnAddressAuth(MachineFunction &MF, MachineBasicBlock &MBB, bool NeedsWinCFI, bool *HasWinCFI) { const auto &MFI = *MF.getInfo(); - if (!MFI.shouldSignReturnAddress()) + if (!MFI.shouldSignReturnAddress(MF)) return; const AArch64Subtarget &Subtarget = MF.getSubtarget(); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); @@ -1936,7 +1936,8 @@ const TargetInstrInfo *TII = Subtarget.getInstrInfo(); DebugLoc DL; bool NeedsWinCFI = needsWinCFI(MF); - bool EmitCFI = MF.getInfo()->needsAsyncDwarfUnwindInfo(); + bool EmitCFI = + MF.getInfo()->needsAsyncDwarfUnwindInfo(MF); bool HasWinCFI = false; bool IsFunclet = false; auto WinCFI = make_scope_exit([&]() { assert(HasWinCFI == MF.hasWinCFI()); }); @@ -3748,11 +3749,12 @@ EndOffset = Instr.Offset + Instr.Size; } + MachineFunction *MF = MBB->getParent(); + // Multiple FP/SP updates in a loop cannot be described by CFI instructions. - TSE.emitCode(InsertI, TFI, /*TryMergeSPUpdate = */ - !MBB->getParent() - ->getInfo() - ->needsAsyncDwarfUnwindInfo()); + TSE.emitCode( + InsertI, TFI, /*TryMergeSPUpdate = */ + !MF->getInfo()->needsAsyncDwarfUnwindInfo(*MF)); return InsertI; } Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -7784,7 +7784,7 @@ .addReg(AArch64::SP, RegState::InternalRead); MI.setMIFlag(MachineInstr::FrameSetup); - if (MF.getInfo()->needsDwarfUnwindInfo()) { + if (MF.getInfo()->needsDwarfUnwindInfo(MF)) { unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr)); BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::CFI_INSTRUCTION)) @@ -7883,7 +7883,7 @@ .addImm(-16); It = MBB.insert(It, STRXpre); - if (MF.getInfo()->needsDwarfUnwindInfo()) { + if (MF.getInfo()->needsDwarfUnwindInfo(MF)) { const TargetSubtargetInfo &STI = MF.getSubtarget(); const MCRegisterInfo *MRI = STI.getRegisterInfo(); unsigned DwarfReg = MRI->getDwarfRegNum(AArch64::LR, true); Index: llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h +++ llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h @@ -36,9 +36,6 @@ /// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and /// contains private AArch64-specific information for each MachineFunction. class AArch64FunctionInfo final : public MachineFunctionInfo { - /// Backreference to the machine function. - MachineFunction *MF; - /// Number of bytes of arguments this function has on the stack. If the callee /// is expected to restore the argument stack this should be a multiple of 16, /// all usable during a tail call. @@ -199,7 +196,8 @@ mutable Optional NeedsAsyncDwarfUnwindInfo; public: - explicit AArch64FunctionInfo(MachineFunction &MF); + explicit AArch64FunctionInfo(const Function &F, + const TargetSubtargetInfo *STI); MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, @@ -433,7 +431,7 @@ CalleeSaveBaseToFrameRecordOffset = Offset; } - bool shouldSignReturnAddress() const; + bool shouldSignReturnAddress(const MachineFunction &MF) const; bool shouldSignReturnAddress(bool SpillsLR) const; bool shouldSignWithBKey() const { return SignWithBKey; } @@ -451,8 +449,8 @@ } int getSwiftAsyncContextFrameIdx() const { return SwiftAsyncContextFrameIdx; } - bool needsDwarfUnwindInfo() const; - bool needsAsyncDwarfUnwindInfo() const; + bool needsDwarfUnwindInfo(const MachineFunction &MF) const; + bool needsAsyncDwarfUnwindInfo(const MachineFunction &MF) const; private: // Hold the lists of LOHs. Index: llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp +++ llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp @@ -66,12 +66,12 @@ return {true, false}; } -static bool ShouldSignWithBKey(const Function &F, const MachineFunction &MF) { +static bool ShouldSignWithBKey(const Function &F, const TargetSubtargetInfo &STI) { if (!F.hasFnAttribute("sign-return-address-key")) { if (const auto *BKey = mdconst::extract_or_null( F.getParent()->getModuleFlag("sign-return-address-with-bkey"))) return BKey->getZExtValue(); - if (MF.getTarget().getTargetTriple().isOSWindows()) + if (STI.getTargetTriple().isOSWindows()) return true; return false; } @@ -82,15 +82,16 @@ return Key.equals_insensitive("b_key"); } -AArch64FunctionInfo::AArch64FunctionInfo(MachineFunction &MF_) : MF(&MF_) { +AArch64FunctionInfo::AArch64FunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) { // If we already know that the function doesn't have a redzone, set // HasRedZone here. - if (MF->getFunction().hasFnAttribute(Attribute::NoRedZone)) + if (F.hasFnAttribute(Attribute::NoRedZone)) HasRedZone = false; - const Function &F = MF->getFunction(); std::tie(SignReturnAddress, SignReturnAddressAll) = GetSignReturnAddress(F); - SignWithBKey = ShouldSignWithBKey(F, *MF); + + SignWithBKey = ShouldSignWithBKey(F, *STI); // TODO: skip functions that have no instrumented allocas for optimization IsMTETagged = F.hasFnAttribute(Attribute::SanitizeMemTag); @@ -112,9 +113,7 @@ BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap &Src2DstMBB) const { - AArch64FunctionInfo *InfoClone = DestMF.cloneInfo(*this); - InfoClone->MF = &DestMF; - return InfoClone; + return DestMF.cloneInfo(*this); } bool AArch64FunctionInfo::shouldSignReturnAddress(bool SpillsLR) const { @@ -125,27 +124,30 @@ return SpillsLR; } -bool AArch64FunctionInfo::shouldSignReturnAddress() const { +bool AArch64FunctionInfo::shouldSignReturnAddress( + const MachineFunction &MF) const { return shouldSignReturnAddress(llvm::any_of( - MF->getFrameInfo().getCalleeSavedInfo(), + MF.getFrameInfo().getCalleeSavedInfo(), [](const auto &Info) { return Info.getReg() == AArch64::LR; })); } -bool AArch64FunctionInfo::needsDwarfUnwindInfo() const { +bool AArch64FunctionInfo::needsDwarfUnwindInfo( + const MachineFunction &MF) const { if (!NeedsDwarfUnwindInfo) - NeedsDwarfUnwindInfo = MF->needsFrameMoves() && - !MF->getTarget().getMCAsmInfo()->usesWindowsCFI(); + NeedsDwarfUnwindInfo = MF.needsFrameMoves() && + !MF.getTarget().getMCAsmInfo()->usesWindowsCFI(); return *NeedsDwarfUnwindInfo; } -bool AArch64FunctionInfo::needsAsyncDwarfUnwindInfo() const { +bool AArch64FunctionInfo::needsAsyncDwarfUnwindInfo( + const MachineFunction &MF) const { if (!NeedsAsyncDwarfUnwindInfo) { - const Function &F = MF->getFunction(); + const Function &F = MF.getFunction(); // The check got "minsize" is because epilogue unwind info is not emitted // (yet) for homogeneous epilogues, outlined functions, and functions // outlined from. - NeedsAsyncDwarfUnwindInfo = needsDwarfUnwindInfo() && + NeedsAsyncDwarfUnwindInfo = needsDwarfUnwindInfo(MF) && F.getUWTableKind() == UWTableKind::Async && !F.hasMinSize(); } Index: llvm/lib/Target/AArch64/AArch64TargetMachine.h =================================================================== --- llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -47,6 +47,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override; Index: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -828,6 +828,12 @@ addPass(createUnpackMachineBundles(nullptr)); } +MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return AArch64FunctionInfo::create(Allocator, F, STI); +} + yaml::MachineFunctionInfo * AArch64TargetMachine::createDefaultFuncInfoYAML() const { return new yaml::AArch64FunctionInfo(); Index: llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h +++ llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h @@ -20,6 +20,9 @@ namespace llvm { +class AMDGPUSubtarget; +class GCNSubtarget; + class AMDGPUMachineFunction : public MachineFunctionInfo { /// A map to keep track of local memory objects and their offsets within the /// local memory space. @@ -61,7 +64,7 @@ bool WaveLimiter = false; public: - AMDGPUMachineFunction(const MachineFunction &MF); + AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST); uint64_t getExplicitKernArgSize() const { return ExplicitKernArgSize; Index: llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp @@ -16,17 +16,16 @@ using namespace llvm; -AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) - : IsEntryFunction(AMDGPU::isEntryFunctionCC( - MF.getFunction().getCallingConv())), +AMDGPUMachineFunction::AMDGPUMachineFunction(const Function &F, + const AMDGPUSubtarget &ST) + : MachineFunctionInfo(), + IsEntryFunction( + AMDGPU::isEntryFunctionCC(F.getCallingConv())), IsModuleEntryFunction( - AMDGPU::isModuleEntryFunctionCC(MF.getFunction().getCallingConv())), - NoSignedZerosFPMath(MF.getTarget().Options.NoSignedZerosFPMath) { - const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF); - + AMDGPU::isModuleEntryFunctionCC(F.getCallingConv())), + NoSignedZerosFPMath(false) { // FIXME: Should initialize KernArgSize based on ExplicitKernelArgOffset, // except reserved size is not correctly aligned. - const Function &F = MF.getFunction(); Attribute MemBoundAttr = F.getFnAttribute("amdgpu-memory-bound"); MemoryBound = MemBoundAttr.getValueAsBool(); @@ -46,6 +45,11 @@ CallingConv::ID CC = F.getCallingConv(); if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) ExplicitKernArgSize = ST.getExplicitKernArgSize(F, MaxKernArgAlign); + + // FIXME: Shouldn't be target specific + Attribute NSZAttr = F.getFnAttribute("no-signed-zeros-fp-math"); + NoSignedZerosFPMath = NSZAttr.isStringAttribute() && + NSZAttr.getValueAsString() == "true"; } unsigned AMDGPUMachineFunction::allocateLDSGlobal(const DataLayout &DL, Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -92,6 +92,10 @@ return true; } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override; Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -24,6 +24,7 @@ #include "GCNSchedStrategy.h" #include "GCNVOPDUtils.h" #include "R600.h" +#include "R600MachineFunctionInfo.h" #include "R600TargetMachine.h" #include "SIMachineFunctionInfo.h" #include "SIMachineScheduler.h" @@ -1157,6 +1158,13 @@ return DAG; } +MachineFunctionInfo *R600TargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return R600MachineFunctionInfo::create(Allocator, F, + STI); +} + //===----------------------------------------------------------------------===// // GCN Pass Setup //===----------------------------------------------------------------------===// @@ -1473,6 +1481,13 @@ return new GCNPassConfig(*this, PM); } +MachineFunctionInfo *GCNTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return SIMachineFunctionInfo::create(Allocator, F, + STI); +} + yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const { return new yaml::SIMachineFunctionInfo(); } Index: llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h +++ llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h @@ -18,7 +18,7 @@ class R600MachineFunctionInfo final : public AMDGPUMachineFunction { public: - R600MachineFunctionInfo(const MachineFunction &MF); + R600MachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); unsigned CFStackSize; }; Index: llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp +++ llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp @@ -8,8 +8,11 @@ //===----------------------------------------------------------------------===// #include "R600MachineFunctionInfo.h" +#include "R600Subtarget.h" using namespace llvm; -R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF) - : AMDGPUMachineFunction(MF) { } +R600MachineFunctionInfo::R600MachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) + : AMDGPUMachineFunction(F, static_cast(*STI)) { +} Index: llvm/lib/Target/AMDGPU/R600TargetMachine.h =================================================================== --- llvm/lib/Target/AMDGPU/R600TargetMachine.h +++ llvm/lib/Target/AMDGPU/R600TargetMachine.h @@ -41,6 +41,10 @@ TargetTransformInfo getTargetTransformInfo(const Function &F) const override; bool isMachineVerifierClean() const override { return false; } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; } // end namespace llvm Index: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -538,8 +538,8 @@ bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg); public: - SIMachineFunctionInfo(const MachineFunction &MF); SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default; + SIMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, Index: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -29,12 +29,18 @@ using namespace llvm; -SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) - : AMDGPUMachineFunction(MF), - Mode(MF.getFunction()), - BufferPSV(static_cast(MF.getTarget())), - ImagePSV(static_cast(MF.getTarget())), - GWSResourcePSV(static_cast(MF.getTarget())), +const GCNTargetMachine &getTM(const TargetSubtargetInfo *STI) { + const SITargetLowering *TLI = static_cast(STI)->getTargetLowering(); + return static_cast(TLI->getTargetMachine()); +} + +SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) + : AMDGPUMachineFunction(F, static_cast(*STI)), + Mode(F), + BufferPSV(getTM(STI)), + ImagePSV(getTM(STI)), + GWSResourcePSV(getTM(STI)), PrivateSegmentBuffer(false), DispatchPtr(false), QueuePtr(false), @@ -54,8 +60,8 @@ ImplicitArgPtr(false), GITPtrHigh(0xffffffff), HighBitsOf32BitAddress(0) { - const GCNSubtarget &ST = MF.getSubtarget(); - const Function &F = MF.getFunction(); + const GCNSubtarget &ST = *static_cast(STI); + FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F); WavesPerEU = ST.getWavesPerEU(F); Index: llvm/lib/Target/ARC/ARCMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/ARC/ARCMachineFunctionInfo.h +++ llvm/lib/Target/ARC/ARCMachineFunctionInfo.h @@ -27,11 +27,7 @@ unsigned ReturnStackOffset; public: - ARCFunctionInfo() - : ReturnStackOffsetSet(false), VarArgsFrameIndex(0), - ReturnStackOffset(-1U), MaxCallStackReq(0) {} - - explicit ARCFunctionInfo(MachineFunction &MF) + explicit ARCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) : ReturnStackOffsetSet(false), VarArgsFrameIndex(0), ReturnStackOffset(-1U), MaxCallStackReq(0) {} ~ARCFunctionInfo() {} Index: llvm/lib/Target/ARC/ARCTargetMachine.cpp =================================================================== --- llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -78,6 +78,12 @@ addPass(createARCOptAddrMode()); } +MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return ARCFunctionInfo::create(Allocator, F, STI); +} + // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() { RegisterTargetMachine X(getTheARCTarget()); Index: llvm/lib/Target/ARM/ARMMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMMachineFunctionInfo.h +++ llvm/lib/Target/ARM/ARMMachineFunctionInfo.h @@ -157,7 +157,7 @@ public: ARMFunctionInfo() = default; - explicit ARMFunctionInfo(MachineFunction &MF); + explicit ARMFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, Index: llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp +++ llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp @@ -13,12 +13,10 @@ void ARMFunctionInfo::anchor() {} -static bool GetBranchTargetEnforcement(MachineFunction &MF) { - const auto &Subtarget = MF.getSubtarget(); +static bool GetBranchTargetEnforcement(const Function &F, const ARMSubtarget &Subtarget) { if (!Subtarget.isMClass() || !Subtarget.hasV7Ops()) return false; - const Function &F = MF.getFunction(); if (!F.hasFnAttribute("branch-target-enforcement")) { if (const auto *BTE = mdconst::extract_or_null( F.getParent()->getModuleFlag("branch-target-enforcement"))) @@ -61,17 +59,18 @@ return {true, false}; } -ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF) - : isThumb(MF.getSubtarget().isThumb()), - hasThumb2(MF.getSubtarget().hasThumb2()), - IsCmseNSEntry(MF.getFunction().hasFnAttribute("cmse_nonsecure_entry")), - IsCmseNSCall(MF.getFunction().hasFnAttribute("cmse_nonsecure_call")), - BranchTargetEnforcement(GetBranchTargetEnforcement(MF)) { +ARMFunctionInfo::ARMFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) + : isThumb(static_cast(STI)->isThumb()), + hasThumb2(static_cast(STI)->hasThumb2()), + IsCmseNSEntry(F.hasFnAttribute("cmse_nonsecure_entry")), + IsCmseNSCall(F.hasFnAttribute("cmse_nonsecure_call")), + BranchTargetEnforcement(GetBranchTargetEnforcement(F, *static_cast(STI))) { - const auto &Subtarget = MF.getSubtarget(); + const auto &Subtarget = *static_cast(STI); if (Subtarget.isMClass() && Subtarget.hasV7Ops()) std::tie(SignReturnAddress, SignReturnAddressAll) = - GetSignReturnAddress(MF.getFunction()); + GetSignReturnAddress(F); } MachineFunctionInfo * Index: llvm/lib/Target/ARM/ARMTargetMachine.h =================================================================== --- llvm/lib/Target/ARM/ARMTargetMachine.h +++ llvm/lib/Target/ARM/ARMTargetMachine.h @@ -73,6 +73,10 @@ bool targetSchedulesPostRAScheduling() const override { return true; }; + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + /// Returns true if a cast between SrcAS and DestAS is a noop. bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { // Addrspacecasts are always noops. Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -11,6 +11,7 @@ #include "ARMTargetMachine.h" #include "ARM.h" +#include "ARMMachineFunctionInfo.h" #include "ARMMacroFusion.h" #include "ARMSubtarget.h" #include "ARMTargetObjectFile.h" @@ -264,6 +265,12 @@ ARMBaseTargetMachine::~ARMBaseTargetMachine() = default; +MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return ARMFunctionInfo::create(Allocator, F, STI); +} + const ARMSubtarget * ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); Index: llvm/lib/Target/AVR/AVRMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AVR/AVRMachineFunctionInfo.h +++ llvm/lib/Target/AVR/AVRMachineFunctionInfo.h @@ -45,20 +45,16 @@ int VarArgsFrameIndex; public: - AVRMachineFunctionInfo() - : HasSpills(false), HasAllocas(false), HasStackArgs(false), - IsInterruptHandler(false), IsSignalHandler(false), - CalleeSavedFrameSize(0), VarArgsFrameIndex(0) {} - - explicit AVRMachineFunctionInfo(MachineFunction &MF) + explicit AVRMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : HasSpills(false), HasAllocas(false), HasStackArgs(false), CalleeSavedFrameSize(0), VarArgsFrameIndex(0) { - unsigned CallConv = MF.getFunction().getCallingConv(); + CallingConv::ID CallConv = F.getCallingConv(); this->IsInterruptHandler = CallConv == CallingConv::AVR_INTR || - MF.getFunction().hasFnAttribute("interrupt"); + F.hasFnAttribute("interrupt"); this->IsSignalHandler = CallConv == CallingConv::AVR_SIGNAL || - MF.getFunction().hasFnAttribute("signal"); + F.hasFnAttribute("signal"); } MachineFunctionInfo * Index: llvm/lib/Target/AVR/AVRTargetMachine.h =================================================================== --- llvm/lib/Target/AVR/AVRTargetMachine.h +++ llvm/lib/Target/AVR/AVRTargetMachine.h @@ -41,6 +41,13 @@ TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + bool isMachineVerifierClean() const override { + return false; + } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; private: std::unique_ptr TLOF; AVRSubtarget SubTarget; Index: llvm/lib/Target/AVR/AVRTargetMachine.cpp =================================================================== --- llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -19,6 +19,7 @@ #include "llvm/MC/TargetRegistry.h" #include "AVR.h" +#include "AVRMachineFunctionInfo.h" #include "AVRTargetObjectFile.h" #include "MCTargetDesc/AVRMCTargetDesc.h" #include "TargetInfo/AVRTargetInfo.h" @@ -103,6 +104,13 @@ return &SubTarget; } +MachineFunctionInfo *AVRTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return AVRMachineFunctionInfo::create(Allocator, F, + STI); +} + //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// Index: llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -40,8 +40,8 @@ public: HexagonMachineFunctionInfo() = default; - - HexagonMachineFunctionInfo(MachineFunction &MF) {} + HexagonMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) {} MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap &Src2DstMBB) Index: llvm/lib/Target/Hexagon/HexagonTargetMachine.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -44,6 +44,10 @@ HexagonTargetObjectFile *getObjFileLowering() const override { return static_cast(TLOF.get()); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; } // end namespace llvm Index: llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -14,6 +14,7 @@ #include "Hexagon.h" #include "HexagonISelLowering.h" #include "HexagonLoopIdiomRecognition.h" +#include "HexagonMachineFunctionInfo.h" #include "HexagonMachineScheduler.h" #include "HexagonTargetObjectFile.h" #include "HexagonTargetTransformInfo.h" @@ -304,6 +305,13 @@ HexagonTargetMachine::~HexagonTargetMachine() = default; +MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return HexagonMachineFunctionInfo::create( + Allocator, F, STI); +} + namespace { /// Hexagon Code Generator Pass Configuration Options. class HexagonPassConfig : public TargetPassConfig { Index: llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h +++ llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h @@ -38,7 +38,8 @@ int VarArgsFrameIndex; public: - explicit LanaiMachineFunctionInfo(MachineFunction &MF) + explicit LanaiMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : VarArgsFrameIndex(0) {} MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, Index: llvm/lib/Target/Lanai/LanaiTargetMachine.h =================================================================== --- llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -47,6 +47,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isMachineVerifierClean() const override { return false; } Index: llvm/lib/Target/Lanai/LanaiTargetMachine.cpp =================================================================== --- llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -13,6 +13,7 @@ #include "LanaiTargetMachine.h" #include "Lanai.h" +#include "LanaiMachineFunctionInfo.h" #include "LanaiTargetObjectFile.h" #include "LanaiTargetTransformInfo.h" #include "TargetInfo/LanaiTargetInfo.h" @@ -72,6 +73,13 @@ return TargetTransformInfo(LanaiTTIImpl(this, F)); } +MachineFunctionInfo *LanaiTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return LanaiMachineFunctionInfo::create(Allocator, + F, STI); +} + namespace { // Lanai Code Generator Pass Configuration Options. class LanaiPassConfig : public TargetPassConfig { Index: llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h +++ llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h @@ -40,7 +40,8 @@ public: MSP430MachineFunctionInfo() = default; - explicit MSP430MachineFunctionInfo(MachineFunction &MF) + explicit MSP430MachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {} MachineFunctionInfo * Index: llvm/lib/Target/MSP430/MSP430TargetMachine.h =================================================================== --- llvm/lib/Target/MSP430/MSP430TargetMachine.h +++ llvm/lib/Target/MSP430/MSP430TargetMachine.h @@ -41,6 +41,10 @@ TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; // MSP430TargetMachine. } // end namespace llvm Index: llvm/lib/Target/MSP430/MSP430TargetMachine.cpp =================================================================== --- llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -12,6 +12,7 @@ #include "MSP430TargetMachine.h" #include "MSP430.h" +#include "MSP430MachineFunctionInfo.h" #include "TargetInfo/MSP430TargetInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -71,6 +72,13 @@ return new MSP430PassConfig(*this, PM); } +MachineFunctionInfo *MSP430TargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return MSP430MachineFunctionInfo::create(Allocator, + F, STI); +} + bool MSP430PassConfig::addInstSelector() { // Install an instruction selector. addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel())); Index: llvm/lib/Target/Mips/MipsMachineFunction.h =================================================================== --- llvm/lib/Target/Mips/MipsMachineFunction.h +++ llvm/lib/Target/Mips/MipsMachineFunction.h @@ -24,7 +24,7 @@ /// Mips target-specific information for each MachineFunction. class MipsFunctionInfo : public MachineFunctionInfo { public: - MipsFunctionInfo(MachineFunction &MF) {} + MipsFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {} MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, Index: llvm/lib/Target/Mips/MipsTargetMachine.h =================================================================== --- llvm/lib/Target/Mips/MipsTargetMachine.h +++ llvm/lib/Target/Mips/MipsTargetMachine.h @@ -63,6 +63,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + /// Returns true if a cast between SrcAS and DestAS is a noop. bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { // Mips doesn't have any special address spaces so we just reserve Index: llvm/lib/Target/Mips/MipsTargetMachine.cpp =================================================================== --- llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -15,6 +15,7 @@ #include "MCTargetDesc/MipsMCTargetDesc.h" #include "Mips.h" #include "Mips16ISelDAGToDAG.h" +#include "MipsMachineFunction.h" #include "MipsSEISelDAGToDAG.h" #include "MipsSubtarget.h" #include "MipsTargetObjectFile.h" @@ -291,6 +292,12 @@ return TargetTransformInfo(MipsTTIImpl(this, F)); } +MachineFunctionInfo *MipsTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return MipsFunctionInfo::create(Allocator, F, STI); +} + // Implemented by targets that want to run passes immediately before // machine code is emitted. void MipsPassConfig::addPreEmitPass() { Index: llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h +++ llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h @@ -24,7 +24,7 @@ SmallVector ImageHandleList; public: - NVPTXMachineFunctionInfo(MachineFunction &MF) {} + NVPTXMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {} MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, Index: llvm/lib/Target/NVPTX/NVPTXTargetMachine.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXTargetMachine.h +++ llvm/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -62,6 +62,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + void adjustPassManager(PassManagerBuilder &) override; void registerPassBuilderCallbacks(PassBuilder &PB) override; Index: llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -15,6 +15,7 @@ #include "NVPTXAllocaHoisting.h" #include "NVPTXAtomicLower.h" #include "NVPTXLowerAggrCopies.h" +#include "NVPTXMachineFunctionInfo.h" #include "NVPTXTargetObjectFile.h" #include "NVPTXTargetTransformInfo.h" #include "TargetInfo/NVPTXTargetInfo.h" @@ -201,6 +202,13 @@ return new NVPTXPassConfig(*this, PM); } +MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return NVPTXMachineFunctionInfo::create(Allocator, + F, STI); +} + void NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) { Builder.addExtension( PassManagerBuilder::EP_EarlyAsPossible, Index: llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h +++ llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h @@ -151,7 +151,7 @@ std::vector> LiveInAttrs; public: - explicit PPCFunctionInfo(const MachineFunction &MF); + explicit PPCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, Index: llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp +++ llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp @@ -20,7 +20,8 @@ cl::init(false), cl::Hidden); void PPCFunctionInfo::anchor() {} -PPCFunctionInfo::PPCFunctionInfo(const MachineFunction &MF) +PPCFunctionInfo::PPCFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : DisableNonVolatileCR(PPCDisableNonVolatileCR) {} MachineFunctionInfo * Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetMachine.h +++ llvm/lib/Target/PowerPC/PPCTargetMachine.h @@ -56,6 +56,11 @@ TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; } bool isPPC64() const { const Triple &TT = getTargetTriple(); Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -13,6 +13,7 @@ #include "PPCTargetMachine.h" #include "MCTargetDesc/PPCMCTargetDesc.h" #include "PPC.h" +#include "PPCMachineFunctionInfo.h" #include "PPCMachineScheduler.h" #include "PPCMacroFusion.h" #include "PPCSubtarget.h" @@ -28,7 +29,6 @@ #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h" -#include "llvm/CodeGen/GlobalISel/Localizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/Passes.h" @@ -581,6 +581,12 @@ return TargetTransformInfo(PPCTTIImpl(this, F)); } +MachineFunctionInfo *PPCTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return PPCFunctionInfo::create(Allocator, F, STI); +} + bool PPCTargetMachine::isLittleEndian() const { assert(Endianness != Endian::NOT_DETECTED && "Unable to determine endianness"); Index: llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h +++ llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h @@ -70,7 +70,7 @@ SmallVector SExt32Registers; public: - RISCVMachineFunctionInfo(const MachineFunction &MF) {} + RISCVMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {} MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, Index: llvm/lib/Target/RISCV/RISCVTargetMachine.h =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -42,6 +42,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + TargetTransformInfo getTargetTransformInfo(const Function &F) const override; bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override; Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -130,6 +130,13 @@ return I.get(); } +MachineFunctionInfo *RISCVTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return RISCVMachineFunctionInfo::create(Allocator, + F, STI); +} + TargetTransformInfo RISCVTargetMachine::getTargetTransformInfo(const Function &F) const { return TargetTransformInfo(RISCVTTIImpl(this, F)); Index: llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h +++ llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h @@ -34,7 +34,8 @@ SparcMachineFunctionInfo() : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0), IsLeafProc(false) {} - explicit SparcMachineFunctionInfo(MachineFunction &MF) + explicit SparcMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0), IsLeafProc(false) {} Index: llvm/lib/Target/Sparc/SparcTargetMachine.h =================================================================== --- llvm/lib/Target/Sparc/SparcTargetMachine.h +++ llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -39,6 +39,10 @@ TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; /// Sparc 32-bit target machine Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp =================================================================== --- llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -12,6 +12,7 @@ #include "SparcTargetMachine.h" #include "LeonPasses.h" #include "Sparc.h" +#include "SparcMachineFunctionInfo.h" #include "SparcTargetObjectFile.h" #include "TargetInfo/SparcTargetInfo.h" #include "llvm/CodeGen/Passes.h" @@ -134,6 +135,13 @@ return I.get(); } +MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return SparcMachineFunctionInfo::create(Allocator, + F, STI); +} + namespace { /// Sparc Code Generator Pass Configuration Options. class SparcPassConfig : public TargetPassConfig { Index: llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h +++ llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h @@ -37,7 +37,8 @@ unsigned NumLocalDynamics; public: - explicit SystemZMachineFunctionInfo(MachineFunction &MF) + explicit SystemZMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : VarArgsFirstGPR(0), VarArgsFirstFPR(0), VarArgsFrameIndex(0), RegSaveFrameIndex(0), FramePointerSaveIndex(0), NumLocalDynamics(0) {} Index: llvm/lib/Target/SystemZ/SystemZTargetMachine.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -50,6 +50,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool targetSchedulesPostRAScheduling() const override { return true; }; }; Index: llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -9,6 +9,7 @@ #include "SystemZTargetMachine.h" #include "MCTargetDesc/SystemZMCTargetDesc.h" #include "SystemZ.h" +#include "SystemZMachineFunctionInfo.h" #include "SystemZMachineScheduler.h" #include "SystemZTargetTransformInfo.h" #include "TargetInfo/SystemZTargetInfo.h" @@ -310,3 +311,10 @@ SystemZTargetMachine::getTargetTransformInfo(const Function &F) const { return TargetTransformInfo(SystemZTTIImpl(this, F)); } + +MachineFunctionInfo *SystemZTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return SystemZMachineFunctionInfo::create( + Allocator, F, STI); +} Index: llvm/lib/Target/VE/VEMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/VE/VEMachineFunctionInfo.h +++ llvm/lib/Target/VE/VEMachineFunctionInfo.h @@ -30,7 +30,8 @@ public: VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {} - explicit VEMachineFunctionInfo(MachineFunction &MF) + explicit VEMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : VarArgsFrameOffset(0), IsLeafProc(false) {} MachineFunctionInfo * Index: llvm/lib/Target/VE/VETargetMachine.h =================================================================== --- llvm/lib/Target/VE/VETargetMachine.h +++ llvm/lib/Target/VE/VETargetMachine.h @@ -47,6 +47,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isMachineVerifierClean() const override { return false; } TargetTransformInfo getTargetTransformInfo(const Function &F) const override; Index: llvm/lib/Target/VE/VETargetMachine.cpp =================================================================== --- llvm/lib/Target/VE/VETargetMachine.cpp +++ llvm/lib/Target/VE/VETargetMachine.cpp @@ -12,6 +12,7 @@ #include "VETargetMachine.h" #include "TargetInfo/VETargetInfo.h" #include "VE.h" +#include "VEMachineFunctionInfo.h" #include "VETargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -97,6 +98,13 @@ return TargetTransformInfo(VETTIImpl(this, F)); } +MachineFunctionInfo *VETargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return VEMachineFunctionInfo::create(Allocator, F, + STI); +} + namespace { /// VE Code Generator Pass Configuration Options. class VEPassConfig : public TargetPassConfig { Index: llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h +++ llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h @@ -65,7 +65,8 @@ bool CFGStackified = false; public: - explicit WebAssemblyFunctionInfo(MachineFunction &) {} + explicit WebAssemblyFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) {} ~WebAssemblyFunctionInfo() override; MachineFunctionInfo * Index: llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp +++ llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp @@ -129,7 +129,6 @@ // MFI.getWasmEHFuncInfo() is non-null only for functions with the // personality function. - if (auto *EHInfo = MF.getWasmEHFuncInfo()) { // SrcToUnwindDest can contain stale mappings in case BBs are removed in // optimizations, in case, for example, they are unreachable. We should not Index: llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h +++ llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h @@ -46,6 +46,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + TargetTransformInfo getTargetTransformInfo(const Function &F) const override; bool usesPhysRegsForValues() const override { return false; } Index: llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -336,6 +336,13 @@ }; } // end anonymous namespace +MachineFunctionInfo *WebAssemblyTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return WebAssemblyFunctionInfo::create(Allocator, F, + STI); +} + TargetTransformInfo WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) const { return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); Index: llvm/lib/Target/X86/X86MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/X86/X86MachineFunctionInfo.h +++ llvm/lib/Target/X86/X86MachineFunctionInfo.h @@ -133,7 +133,8 @@ public: X86MachineFunctionInfo() = default; - explicit X86MachineFunctionInfo(MachineFunction &MF) {} + explicit X86MachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) {} explicit X86MachineFunctionInfo(const X86MachineFunctionInfo &) = default; MachineFunctionInfo * Index: llvm/lib/Target/X86/X86TargetMachine.h =================================================================== --- llvm/lib/Target/X86/X86TargetMachine.h +++ llvm/lib/Target/X86/X86TargetMachine.h @@ -53,6 +53,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isJIT() const { return IsJIT; } bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; Index: llvm/lib/Target/X86/X86TargetMachine.cpp =================================================================== --- llvm/lib/Target/X86/X86TargetMachine.cpp +++ llvm/lib/Target/X86/X86TargetMachine.cpp @@ -16,6 +16,7 @@ #include "X86.h" #include "X86CallLowering.h" #include "X86LegalizerInfo.h" +#include "X86MachineFunctionInfo.h" #include "X86MacroFusion.h" #include "X86Subtarget.h" #include "X86TargetObjectFile.h" @@ -425,6 +426,13 @@ return new X86PassConfig(*this, PM); } +MachineFunctionInfo *X86TargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return X86MachineFunctionInfo::create(Allocator, F, + STI); +} + void X86PassConfig::addIRPasses() { addPass(createAtomicExpandPass()); Index: llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h +++ llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h @@ -43,7 +43,8 @@ public: XCoreFunctionInfo() = default; - explicit XCoreFunctionInfo(MachineFunction &MF) {} + explicit XCoreFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) {} MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, Index: llvm/lib/Target/XCore/XCoreTargetMachine.h =================================================================== --- llvm/lib/Target/XCore/XCoreTargetMachine.h +++ llvm/lib/Target/XCore/XCoreTargetMachine.h @@ -47,6 +47,10 @@ TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; } // end namespace llvm Index: llvm/lib/Target/XCore/XCoreTargetMachine.cpp =================================================================== --- llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -13,6 +13,7 @@ #include "MCTargetDesc/XCoreMCTargetDesc.h" #include "TargetInfo/XCoreTargetInfo.h" #include "XCore.h" +#include "XCoreMachineFunctionInfo.h" #include "XCoreTargetObjectFile.h" #include "XCoreTargetTransformInfo.h" #include "llvm/ADT/Optional.h" @@ -111,3 +112,9 @@ XCoreTargetMachine::getTargetTransformInfo(const Function &F) const { return TargetTransformInfo(XCoreTTIImpl(this, F)); } + +MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return XCoreFunctionInfo::create(Allocator, F, STI); +}