Index: llvm/include/llvm/CodeGen/MachineFunction.h =================================================================== --- llvm/include/llvm/CodeGen/MachineFunction.h +++ llvm/include/llvm/CodeGen/MachineFunction.h @@ -99,9 +99,10 @@ /// supplied allocator. /// /// This function can be overridden in a derive class. - template - static Ty *create(BumpPtrAllocator &Allocator, MachineFunction &MF) { - return new (Allocator.Allocate()) Ty(MF); + template + static Ty *create(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) { + return new (Allocator.Allocate()) Ty(F, STI); } }; @@ -615,14 +616,12 @@ /// template Ty *getInfo() { - if (!MFInfo) - MFInfo = Ty::template create(Allocator, *this); return static_cast(MFInfo); } template const Ty *getInfo() const { - return const_cast(this)->getInfo(); + return static_cast(MFInfo); } /// Returns the denormal handling type for the default rounding mode of the Index: llvm/include/llvm/Target/TargetMachine.h =================================================================== --- llvm/include/llvm/Target/TargetMachine.h +++ llvm/include/llvm/Target/TargetMachine.h @@ -17,6 +17,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/IR/DataLayout.h" #include "llvm/Pass.h" +#include "llvm/Support/Allocator.h" #include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetOptions.h" #include @@ -52,6 +53,7 @@ } using legacy::PassManagerBase; +struct MachineFunctionInfo; namespace yaml { struct MachineFunctionInfo; } @@ -121,6 +123,13 @@ return nullptr; } + /// Create the target's instance of MachineFunctionInfo + virtual MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return nullptr; + } + /// Allocate and return a default initialized instance of the YAML /// representation for the MachineFunctionInfo. virtual yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const { Index: llvm/lib/CodeGen/MachineFunction.cpp =================================================================== --- llvm/lib/CodeGen/MachineFunction.cpp +++ llvm/lib/CodeGen/MachineFunction.cpp @@ -161,7 +161,8 @@ else RegInfo = nullptr; - MFInfo = nullptr; + MFInfo = Target.createMachineFunctionInfo(Allocator, F, STI); + // We can realign the stack if the target supports it and the user hasn't // explicitly asked us not to. bool CanRealignSP = STI->getFrameLowering()->isStackRealignable() && Index: llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h +++ llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h @@ -138,12 +138,11 @@ public: AArch64FunctionInfo() = default; - explicit AArch64FunctionInfo(MachineFunction &MF) { - (void)MF; - + explicit AArch64FunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) { // If we already know that the function doesn't have a redzone, set // HasRedZone here. - if (MF.getFunction().hasFnAttribute(Attribute::NoRedZone)) + if (F.hasFnAttribute(Attribute::NoRedZone)) HasRedZone = false; } void initializeBaseYamlFields(const yaml::AArch64FunctionInfo &YamlMFI); Index: llvm/lib/Target/AArch64/AArch64TargetMachine.h =================================================================== --- llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -49,6 +49,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override; Index: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -678,6 +678,12 @@ addPass(createUnpackMachineBundles(nullptr)); } +MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return AArch64FunctionInfo::create(Allocator, F, STI); +} + yaml::MachineFunctionInfo * AArch64TargetMachine::createDefaultFuncInfoYAML() const { return new yaml::AArch64FunctionInfo(); Index: llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h +++ llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h @@ -15,6 +15,7 @@ namespace llvm { +class AMDGPUSubtarget; class GCNSubtarget; class AMDGPUMachineFunction : public MachineFunctionInfo { @@ -45,7 +46,7 @@ bool WaveLimiter = false; public: - AMDGPUMachineFunction(const MachineFunction &MF); + AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST); uint64_t getExplicitKernArgSize() const { return ExplicitKernArgSize; Index: llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp @@ -13,16 +13,15 @@ using namespace llvm; -AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) : +AMDGPUMachineFunction::AMDGPUMachineFunction(const Function &F, + const AMDGPUSubtarget &ST) : MachineFunctionInfo(), - Mode(MF.getFunction()), - IsEntryFunction(AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv())), - NoSignedZerosFPMath(MF.getTarget().Options.NoSignedZerosFPMath) { - const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF); + Mode(F), + IsEntryFunction(AMDGPU::isEntryFunctionCC(F.getCallingConv())), + NoSignedZerosFPMath(false) { // FIXME: Should initialize KernArgSize based on ExplicitKernelArgOffset, // except reserved size is not correctly aligned. - const Function &F = MF.getFunction(); Attribute MemBoundAttr = F.getFnAttribute("amdgpu-memory-bound"); MemoryBound = MemBoundAttr.isStringAttribute() && @@ -35,6 +34,11 @@ CallingConv::ID CC = F.getCallingConv(); if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) ExplicitKernArgSize = ST.getExplicitKernArgSize(F, MaxKernArgAlign); + + // FIXME: Shouldn't be target specific + Attribute NSZAttr = F.getFnAttribute("no-signed-zeros-fp-math"); + NoSignedZerosFPMath = NSZAttr.isStringAttribute() && + NSZAttr.getValueAsString() == "true"; } unsigned AMDGPUMachineFunction::allocateLDSGlobal(const DataLayout &DL, Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -87,6 +87,10 @@ bool isMachineVerifierClean() const override { return false; } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; //===----------------------------------------------------------------------===// @@ -113,6 +117,10 @@ return true; } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override; Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -25,6 +25,7 @@ #include "GCNIterativeScheduler.h" #include "GCNSchedStrategy.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" +#include "R600MachineFunctionInfo.h" #include "R600MachineScheduler.h" #include "SIMachineFunctionInfo.h" #include "SIMachineScheduler.h" @@ -846,6 +847,13 @@ return new R600PassConfig(*this, PM); } +MachineFunctionInfo *R600TargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return R600MachineFunctionInfo::create(Allocator, F, + STI); +} + //===----------------------------------------------------------------------===// // GCN Pass Setup //===----------------------------------------------------------------------===// @@ -1061,6 +1069,13 @@ return new GCNPassConfig(*this, PM); } +MachineFunctionInfo *GCNTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return SIMachineFunctionInfo::create(Allocator, F, + STI); +} + yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const { return new yaml::SIMachineFunctionInfo(); } Index: llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h +++ llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h @@ -18,7 +18,7 @@ class R600MachineFunctionInfo final : public AMDGPUMachineFunction { public: - R600MachineFunctionInfo(const MachineFunction &MF); + R600MachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); unsigned CFStackSize; }; Index: llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp +++ llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.cpp @@ -8,8 +8,11 @@ //===----------------------------------------------------------------------===// #include "R600MachineFunctionInfo.h" +#include "AMDGPUSubtarget.h" using namespace llvm; -R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF) - : AMDGPUMachineFunction(MF) { } +R600MachineFunctionInfo::R600MachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) + : AMDGPUMachineFunction(F, static_cast(*STI)) { +} Index: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -494,7 +494,7 @@ bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg); public: - SIMachineFunctionInfo(const MachineFunction &MF); + SIMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI); Index: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -27,8 +27,9 @@ using namespace llvm; -SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) - : AMDGPUMachineFunction(MF), +SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) + : AMDGPUMachineFunction(F, static_cast(*STI)), PrivateSegmentBuffer(false), DispatchPtr(false), QueuePtr(false), @@ -48,8 +49,7 @@ GITPtrHigh(0xffffffff), HighBitsOf32BitAddress(0), GDSSize(0) { - const GCNSubtarget &ST = MF.getSubtarget(); - const Function &F = MF.getFunction(); + const GCNSubtarget &ST = *static_cast(STI); FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F); WavesPerEU = ST.getWavesPerEU(F); Index: llvm/lib/Target/ARC/ARCMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/ARC/ARCMachineFunctionInfo.h +++ llvm/lib/Target/ARC/ARCMachineFunctionInfo.h @@ -27,11 +27,7 @@ unsigned ReturnStackOffset; public: - ARCFunctionInfo() - : ReturnStackOffsetSet(false), VarArgsFrameIndex(0), - ReturnStackOffset(-1U), MaxCallStackReq(0) {} - - explicit ARCFunctionInfo(MachineFunction &MF) + explicit ARCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) : ReturnStackOffsetSet(false), VarArgsFrameIndex(0), ReturnStackOffset(-1U), MaxCallStackReq(0) {} Index: llvm/lib/Target/ARC/ARCTargetMachine.cpp =================================================================== --- llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -80,6 +80,12 @@ addPass(createARCOptAddrMode()); } +MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return ARCFunctionInfo::create(Allocator, F, STI); +} + // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() { RegisterTargetMachine X(getTheARCTarget()); Index: llvm/lib/Target/ARM/ARMMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMMachineFunctionInfo.h +++ llvm/lib/Target/ARM/ARMMachineFunctionInfo.h @@ -139,7 +139,7 @@ public: ARMFunctionInfo() = default; - explicit ARMFunctionInfo(MachineFunction &MF); + explicit ARMFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); bool isThumbFunction() const { return isThumb; } bool isThumb1OnlyFunction() const { return isThumb && !hasThumb2; } Index: llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp +++ llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp @@ -13,8 +13,9 @@ void ARMFunctionInfo::anchor() {} -ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF) - : isThumb(MF.getSubtarget().isThumb()), - hasThumb2(MF.getSubtarget().hasThumb2()), - IsCmseNSEntry(MF.getFunction().hasFnAttribute("cmse_nonsecure_entry")), - IsCmseNSCall(MF.getFunction().hasFnAttribute("cmse_nonsecure_call")) {} +ARMFunctionInfo::ARMFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) + : isThumb(static_cast(STI)->isThumb()), + hasThumb2(static_cast(STI)->hasThumb2()), + IsCmseNSEntry(F.hasFnAttribute("cmse_nonsecure_entry")), + IsCmseNSCall(F.hasFnAttribute("cmse_nonsecure_call")) {} Index: llvm/lib/Target/ARM/ARMTargetMachine.h =================================================================== --- llvm/lib/Target/ARM/ARMTargetMachine.h +++ llvm/lib/Target/ARM/ARMTargetMachine.h @@ -72,6 +72,10 @@ } bool targetSchedulesPostRAScheduling() const override { return true; }; + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; /// ARM/Thumb little endian target machine. Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -11,6 +11,7 @@ #include "ARMTargetMachine.h" #include "ARM.h" +#include "ARMMachineFunctionInfo.h" #include "ARMMacroFusion.h" #include "ARMSubtarget.h" #include "ARMTargetObjectFile.h" @@ -256,6 +257,12 @@ ARMBaseTargetMachine::~ARMBaseTargetMachine() = default; +MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return ARMFunctionInfo::create(Allocator, F, STI); +} + const ARMSubtarget * ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); Index: llvm/lib/Target/AVR/AVRMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AVR/AVRMachineFunctionInfo.h +++ llvm/lib/Target/AVR/AVRMachineFunctionInfo.h @@ -45,18 +45,16 @@ int VarArgsFrameIndex; public: - AVRMachineFunctionInfo() - : HasSpills(false), HasAllocas(false), HasStackArgs(false), - IsInterruptHandler(false), IsSignalHandler(false), - CalleeSavedFrameSize(0), VarArgsFrameIndex(0) {} - - explicit AVRMachineFunctionInfo(MachineFunction &MF) + explicit AVRMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : HasSpills(false), HasAllocas(false), HasStackArgs(false), CalleeSavedFrameSize(0), VarArgsFrameIndex(0) { - unsigned CallConv = MF.getFunction().getCallingConv(); + CallingConv::ID CallConv = F.getCallingConv(); - this->IsInterruptHandler = CallConv == CallingConv::AVR_INTR || MF.getFunction().hasFnAttribute("interrupt"); - this->IsSignalHandler = CallConv == CallingConv::AVR_SIGNAL || MF.getFunction().hasFnAttribute("signal"); + this->IsInterruptHandler = CallConv == CallingConv::AVR_INTR || + F.hasFnAttribute("interrupt"); + this->IsSignalHandler = CallConv == CallingConv::AVR_SIGNAL || + F.hasFnAttribute("signal"); } bool getHasSpills() const { return HasSpills; } Index: llvm/lib/Target/AVR/AVRTargetMachine.h =================================================================== --- llvm/lib/Target/AVR/AVRTargetMachine.h +++ llvm/lib/Target/AVR/AVRTargetMachine.h @@ -46,6 +46,10 @@ return false; } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + private: std::unique_ptr TLOF; AVRSubtarget SubTarget; Index: llvm/lib/Target/AVR/AVRTargetMachine.cpp =================================================================== --- llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -19,6 +19,7 @@ #include "llvm/Support/TargetRegistry.h" #include "AVR.h" +#include "AVRMachineFunctionInfo.h" #include "AVRTargetObjectFile.h" #include "MCTargetDesc/AVRMCTargetDesc.h" #include "TargetInfo/AVRTargetInfo.h" @@ -93,6 +94,13 @@ return &SubTarget; } +MachineFunctionInfo *AVRTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return AVRMachineFunctionInfo::create(Allocator, F, + STI); +} + //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// Index: llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -41,7 +41,8 @@ public: HexagonMachineFunctionInfo() = default; - HexagonMachineFunctionInfo(MachineFunction &MF) {} + HexagonMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) {} unsigned getSRetReturnReg() const { return SRetReturnReg; } void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } Index: llvm/lib/Target/Hexagon/HexagonTargetMachine.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -43,6 +43,10 @@ HexagonTargetObjectFile *getObjFileLowering() const override { return static_cast(TLOF.get()); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; } // end namespace llvm Index: llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -13,6 +13,7 @@ #include "HexagonTargetMachine.h" #include "Hexagon.h" #include "HexagonISelLowering.h" +#include "HexagonMachineFunctionInfo.h" #include "HexagonMachineScheduler.h" #include "HexagonTargetObjectFile.h" #include "HexagonTargetTransformInfo.h" @@ -275,6 +276,12 @@ return TargetTransformInfo(HexagonTTIImpl(this, F)); } +MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return HexagonMachineFunctionInfo::create( + Allocator, F, STI); +} HexagonTargetMachine::~HexagonTargetMachine() {} Index: llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h +++ llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h @@ -38,7 +38,8 @@ int VarArgsFrameIndex; public: - explicit LanaiMachineFunctionInfo(MachineFunction &MF) + explicit LanaiMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : VarArgsFrameIndex(0) {} Register getSRetReturnReg() const { return SRetReturnReg; } Index: llvm/lib/Target/Lanai/LanaiTargetMachine.h =================================================================== --- llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -49,6 +49,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isMachineVerifierClean() const override { return false; } Index: llvm/lib/Target/Lanai/LanaiTargetMachine.cpp =================================================================== --- llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -13,6 +13,7 @@ #include "LanaiTargetMachine.h" #include "Lanai.h" +#include "LanaiMachineFunctionInfo.h" #include "LanaiTargetObjectFile.h" #include "LanaiTargetTransformInfo.h" #include "TargetInfo/LanaiTargetInfo.h" @@ -74,6 +75,13 @@ return TargetTransformInfo(LanaiTTIImpl(this, F)); } +MachineFunctionInfo *LanaiTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return LanaiMachineFunctionInfo::create(Allocator, + F, STI); +} + namespace { // Lanai Code Generator Pass Configuration Options. class LanaiPassConfig : public TargetPassConfig { Index: llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h +++ llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h @@ -40,7 +40,8 @@ public: MSP430MachineFunctionInfo() = default; - explicit MSP430MachineFunctionInfo(MachineFunction &MF) + explicit MSP430MachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {} unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; } Index: llvm/lib/Target/MSP430/MSP430TargetMachine.h =================================================================== --- llvm/lib/Target/MSP430/MSP430TargetMachine.h +++ llvm/lib/Target/MSP430/MSP430TargetMachine.h @@ -41,6 +41,10 @@ TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; // MSP430TargetMachine. } // end namespace llvm Index: llvm/lib/Target/MSP430/MSP430TargetMachine.cpp =================================================================== --- llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -12,6 +12,7 @@ #include "MSP430TargetMachine.h" #include "MSP430.h" +#include "MSP430MachineFunctionInfo.h" #include "TargetInfo/MSP430TargetInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -73,6 +74,13 @@ return new MSP430PassConfig(*this, PM); } +MachineFunctionInfo *MSP430TargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return MSP430MachineFunctionInfo::create(Allocator, + F, STI); +} + bool MSP430PassConfig::addInstSelector() { // Install an instruction selector. addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel())); Index: llvm/lib/Target/Mips/MipsMachineFunction.h =================================================================== --- llvm/lib/Target/Mips/MipsMachineFunction.h +++ llvm/lib/Target/Mips/MipsMachineFunction.h @@ -24,7 +24,7 @@ /// Mips target-specific information for each MachineFunction. class MipsFunctionInfo : public MachineFunctionInfo { public: - MipsFunctionInfo(MachineFunction &MF) {} + MipsFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {} ~MipsFunctionInfo() override; Index: llvm/lib/Target/Mips/MipsTargetMachine.h =================================================================== --- llvm/lib/Target/Mips/MipsTargetMachine.h +++ llvm/lib/Target/Mips/MipsTargetMachine.h @@ -63,6 +63,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isLittleEndian() const { return isLittle; } const MipsABIInfo &getABI() const { return ABI; } }; Index: llvm/lib/Target/Mips/MipsTargetMachine.cpp =================================================================== --- llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -15,6 +15,7 @@ #include "MCTargetDesc/MipsMCTargetDesc.h" #include "Mips.h" #include "Mips16ISelDAGToDAG.h" +#include "MipsMachineFunction.h" #include "MipsSEISelDAGToDAG.h" #include "MipsSubtarget.h" #include "MipsTargetObjectFile.h" @@ -294,6 +295,12 @@ return TargetTransformInfo(BasicTTIImpl(this, F)); } +MachineFunctionInfo *MipsTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return MipsFunctionInfo::create(Allocator, F, STI); +} + // Implemented by targets that want to run passes immediately before // machine code is emitted. return true if -print-machineinstrs should // print out the code after the passes. Index: llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h +++ llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h @@ -24,7 +24,7 @@ SmallVector ImageHandleList; public: - NVPTXMachineFunctionInfo(MachineFunction &MF) {} + NVPTXMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {} /// Returns the index for the symbol \p Symbol. If the symbol was previously, /// added, the same index is returned. Otherwise, the symbol is added and the Index: llvm/lib/Target/NVPTX/NVPTXTargetMachine.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXTargetMachine.h +++ llvm/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -63,6 +63,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + void adjustPassManager(PassManagerBuilder &) override; TargetTransformInfo getTargetTransformInfo(const Function &F) override; Index: llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -14,6 +14,7 @@ #include "NVPTX.h" #include "NVPTXAllocaHoisting.h" #include "NVPTXLowerAggrCopies.h" +#include "NVPTXMachineFunctionInfo.h" #include "NVPTXTargetObjectFile.h" #include "NVPTXTargetTransformInfo.h" #include "TargetInfo/NVPTXTargetInfo.h" @@ -196,6 +197,13 @@ return new NVPTXPassConfig(*this, PM); } +MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return NVPTXMachineFunctionInfo::create(Allocator, + F, STI); +} + void NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) { Builder.addExtension( PassManagerBuilder::EP_EarlyAsPossible, Index: llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h +++ llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h @@ -126,7 +126,7 @@ std::vector> LiveInAttrs; public: - explicit PPCFunctionInfo(const MachineFunction &MF); + explicit PPCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI); int getFramePointerSaveIndex() const { return FramePointerSaveIndex; } void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; } Index: llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp +++ llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp @@ -19,7 +19,8 @@ cl::init(false), cl::Hidden); void PPCFunctionInfo::anchor() {} -PPCFunctionInfo::PPCFunctionInfo(const MachineFunction &MF) +PPCFunctionInfo::PPCFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : DisableNonVolatileCR(PPCDisableNonVolatileCR) {} MCSymbol *PPCFunctionInfo::getPICOffsetSymbol(MachineFunction &MF) const { Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetMachine.h +++ llvm/lib/Target/PowerPC/PPCTargetMachine.h @@ -53,6 +53,11 @@ TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; } bool isPPC64() const { const Triple &TT = getTargetTriple(); Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -13,6 +13,7 @@ #include "PPCTargetMachine.h" #include "MCTargetDesc/PPCMCTargetDesc.h" #include "PPC.h" +#include "PPCMachineFunctionInfo.h" #include "PPCMachineScheduler.h" #include "PPCMacroFusion.h" #include "PPCSubtarget.h" @@ -24,9 +25,9 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Triple.h" #include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetPassConfig.h" -#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Function.h" @@ -541,6 +542,12 @@ return TargetTransformInfo(PPCTTIImpl(this, F)); } +MachineFunctionInfo *PPCTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return PPCFunctionInfo::create(Allocator, F, STI); +} + static MachineSchedRegistry PPCPreRASchedRegistry("ppc-prera", "Run PowerPC PreRA specific scheduler", Index: llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h +++ llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h @@ -34,7 +34,7 @@ unsigned LibCallStackSize = 0; public: - RISCVMachineFunctionInfo(const MachineFunction &MF) {} + RISCVMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {} int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } Index: llvm/lib/Target/RISCV/RISCVTargetMachine.h =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -42,6 +42,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + TargetTransformInfo getTargetTransformInfo(const Function &F) override; }; } Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -12,6 +12,7 @@ #include "RISCVTargetMachine.h" #include "RISCV.h" +#include "RISCVMachineFunctionInfo.h" #include "RISCVTargetObjectFile.h" #include "RISCVTargetTransformInfo.h" #include "TargetInfo/RISCVTargetInfo.h" @@ -105,6 +106,13 @@ return I.get(); } +MachineFunctionInfo *RISCVTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return RISCVMachineFunctionInfo::create(Allocator, + F, STI); +} + TargetTransformInfo RISCVTargetMachine::getTargetTransformInfo(const Function &F) { return TargetTransformInfo(RISCVTTIImpl(this, F)); Index: llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h +++ llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h @@ -34,7 +34,8 @@ SparcMachineFunctionInfo() : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0), IsLeafProc(false) {} - explicit SparcMachineFunctionInfo(MachineFunction &MF) + explicit SparcMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0), IsLeafProc(false) {} Index: llvm/lib/Target/Sparc/SparcTargetMachine.h =================================================================== --- llvm/lib/Target/Sparc/SparcTargetMachine.h +++ llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -39,6 +39,10 @@ TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; /// Sparc 32-bit target machine Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp =================================================================== --- llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -12,6 +12,7 @@ #include "SparcTargetMachine.h" #include "LeonPasses.h" #include "Sparc.h" +#include "SparcMachineFunctionInfo.h" #include "SparcTargetObjectFile.h" #include "TargetInfo/SparcTargetInfo.h" #include "llvm/CodeGen/Passes.h" @@ -140,6 +141,13 @@ return I.get(); } +MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return SparcMachineFunctionInfo::create(Allocator, + F, STI); +} + namespace { /// Sparc Code Generator Pass Configuration Options. class SparcPassConfig : public TargetPassConfig { Index: llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h +++ llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h @@ -38,7 +38,8 @@ unsigned NumLocalDynamics; public: - explicit SystemZMachineFunctionInfo(MachineFunction &MF) + explicit SystemZMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : VarArgsFirstGPR(0), VarArgsFirstFPR(0), VarArgsFrameIndex(0), RegSaveFrameIndex(0), FramePointerSaveIndex(0), ManipulatesSP(false), NumLocalDynamics(0) {} Index: llvm/lib/Target/SystemZ/SystemZTargetMachine.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -50,6 +50,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool targetSchedulesPostRAScheduling() const override { return true; }; }; Index: llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -9,6 +9,7 @@ #include "SystemZTargetMachine.h" #include "MCTargetDesc/SystemZMCTargetDesc.h" #include "SystemZ.h" +#include "SystemZMachineFunctionInfo.h" #include "SystemZMachineScheduler.h" #include "SystemZTargetTransformInfo.h" #include "TargetInfo/SystemZTargetInfo.h" @@ -323,3 +324,10 @@ SystemZTargetMachine::getTargetTransformInfo(const Function &F) { return TargetTransformInfo(SystemZTTIImpl(this, F)); } + +MachineFunctionInfo *SystemZTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return SystemZMachineFunctionInfo::create( + Allocator, F, STI); +} Index: llvm/lib/Target/VE/VEMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/VE/VEMachineFunctionInfo.h +++ llvm/lib/Target/VE/VEMachineFunctionInfo.h @@ -31,7 +31,8 @@ public: VEMachineFunctionInfo() : GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {} - explicit VEMachineFunctionInfo(MachineFunction &MF) + explicit VEMachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) : GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {} Register getGlobalBaseReg() const { return GlobalBaseReg; } Index: llvm/lib/Target/VE/VETargetMachine.h =================================================================== --- llvm/lib/Target/VE/VETargetMachine.h +++ llvm/lib/Target/VE/VETargetMachine.h @@ -47,6 +47,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isMachineVerifierClean() const override { return false; } TargetTransformInfo getTargetTransformInfo(const Function &F) override; Index: llvm/lib/Target/VE/VETargetMachine.cpp =================================================================== --- llvm/lib/Target/VE/VETargetMachine.cpp +++ llvm/lib/Target/VE/VETargetMachine.cpp @@ -12,6 +12,7 @@ #include "VETargetMachine.h" #include "TargetInfo/VETargetInfo.h" #include "VE.h" +#include "VEMachineFunctionInfo.h" #include "VETargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -85,6 +86,13 @@ return TargetTransformInfo(VETTIImpl(this, F)); } +MachineFunctionInfo *VETargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return VEMachineFunctionInfo::create(Allocator, F, + STI); +} + namespace { /// VE Code Generator Pass Configuration Options. class VEPassConfig : public TargetPassConfig { Index: llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h +++ llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h @@ -64,7 +64,8 @@ bool CFGStackified = false; public: - explicit WebAssemblyFunctionInfo(MachineFunction &MF) {} + explicit WebAssemblyFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) {} ~WebAssemblyFunctionInfo() override; void initializeBaseYamlFields(const yaml::WebAssemblyFunctionInfo &YamlMFI); Index: llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h +++ llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h @@ -45,6 +45,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + TargetTransformInfo getTargetTransformInfo(const Function &F) override; bool usesPhysRegsForValues() const override { return false; } Index: llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -330,6 +330,13 @@ }; } // end anonymous namespace +MachineFunctionInfo *WebAssemblyTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return WebAssemblyFunctionInfo::create(Allocator, F, + STI); +} + TargetTransformInfo WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) { return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); Index: llvm/lib/Target/X86/X86MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/X86/X86MachineFunctionInfo.h +++ llvm/lib/Target/X86/X86MachineFunctionInfo.h @@ -120,7 +120,8 @@ public: X86MachineFunctionInfo() = default; - explicit X86MachineFunctionInfo(MachineFunction &MF) {} + explicit X86MachineFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) {} bool getForceFramePointer() const { return ForceFramePointer;} void setForceFramePointer(bool forceFP) { ForceFramePointer = forceFP; } Index: llvm/lib/Target/X86/X86TargetMachine.h =================================================================== --- llvm/lib/Target/X86/X86TargetMachine.h +++ llvm/lib/Target/X86/X86TargetMachine.h @@ -53,6 +53,10 @@ return TLOF.get(); } + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; + bool isJIT() const { return IsJIT; } }; Index: llvm/lib/Target/X86/X86TargetMachine.cpp =================================================================== --- llvm/lib/Target/X86/X86TargetMachine.cpp +++ llvm/lib/Target/X86/X86TargetMachine.cpp @@ -16,6 +16,7 @@ #include "X86.h" #include "X86CallLowering.h" #include "X86LegalizerInfo.h" +#include "X86MachineFunctionInfo.h" #include "X86MacroFusion.h" #include "X86Subtarget.h" #include "X86TargetObjectFile.h" @@ -392,6 +393,13 @@ return new X86PassConfig(*this, PM); } +MachineFunctionInfo *X86TargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return X86MachineFunctionInfo::create(Allocator, F, + STI); +} + void X86PassConfig::addIRPasses() { addPass(createAtomicExpandPass()); Index: llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h +++ llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h @@ -43,7 +43,8 @@ public: XCoreFunctionInfo() = default; - explicit XCoreFunctionInfo(MachineFunction &MF) {} + explicit XCoreFunctionInfo(const Function &F, + const TargetSubtargetInfo *STI) {} ~XCoreFunctionInfo() override = default; Index: llvm/lib/Target/XCore/XCoreTargetMachine.h =================================================================== --- llvm/lib/Target/XCore/XCoreTargetMachine.h +++ llvm/lib/Target/XCore/XCoreTargetMachine.h @@ -47,6 +47,10 @@ TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + MachineFunctionInfo * + createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const override; }; } // end namespace llvm Index: llvm/lib/Target/XCore/XCoreTargetMachine.cpp =================================================================== --- llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -13,6 +13,7 @@ #include "MCTargetDesc/XCoreMCTargetDesc.h" #include "TargetInfo/XCoreTargetInfo.h" #include "XCore.h" +#include "XCoreMachineFunctionInfo.h" #include "XCoreTargetObjectFile.h" #include "XCoreTargetTransformInfo.h" #include "llvm/ADT/Optional.h" @@ -113,3 +114,9 @@ XCoreTargetMachine::getTargetTransformInfo(const Function &F) { return TargetTransformInfo(XCoreTTIImpl(this, F)); } + +MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo( + BumpPtrAllocator &Allocator, const Function &F, + const TargetSubtargetInfo *STI) const { + return XCoreFunctionInfo::create(Allocator, F, STI); +}