diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -1715,8 +1715,8 @@ // Hoist vector bitcasts that don't change the number of lanes out of unary // shuffles, where they are less likely to get in the way of other combines. - // (shuffle (vNxT1 (bitcast (vNxT0 x))), undef, mask) -> - // (vNxT1 (bitcast (vNxt0 (shuffle x, undef, mask)))) + // (shuffle (vNxT1 (bitcast (vNxT0 x))), undef, mask) -> + // (vNxT1 (bitcast (vNxT0 (shuffle x, undef, mask)))) SDValue Bitcast = N->getOperand(0); if (Bitcast.getOpcode() != ISD::BITCAST) return SDValue(); @@ -1725,7 +1725,8 @@ SDValue CastOp = Bitcast.getOperand(0); MVT SrcType = CastOp.getSimpleValueType(); MVT DstType = Bitcast.getSimpleValueType(); - if (SrcType.getVectorNumElements() != DstType.getVectorNumElements()) + if (!SrcType.is128BitVector() || + SrcType.getVectorNumElements() != DstType.getVectorNumElements()) return SDValue(); SDValue NewShuffle = DAG.getVectorShuffle( SrcType, SDLoc(N), CastOp, DAG.getUNDEF(SrcType), Shuffle->getMask()); diff --git a/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll b/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll --- a/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll @@ -17,3 +17,14 @@ %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %b } + +; CHECK-LABEL: not_a_vec: +; CHECK-NEXT: .functype not_a_vec (i64, i64) -> (v128){{$}} +; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $0{{$}} +; CHECK-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $pop[[L1]], $2, 0, 1, 2, 3 +; CHECK-NEXT: return $pop[[R]] +define <4 x i32> @not_a_vec(i128 %x) { + %a = bitcast i128 %x to <4 x i32> + %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer + ret <4 x i32> %b +}