Index: llvm/lib/Target/X86/X86ISelLowering.cpp =================================================================== --- llvm/lib/Target/X86/X86ISelLowering.cpp +++ llvm/lib/Target/X86/X86ISelLowering.cpp @@ -10192,15 +10192,6 @@ if (NumZero == 0) return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); - // Just load a vector integer constant. Loading is better for code size, - // avoids move GPR immediate --> XMM, and reduces register pressure. - if (IsAllConstants && VT.isInteger()) { - // TODO: Remove -1 restriction with demanded elements improvement? - // TODO: Insert 128-bit load into wider undef vector? - if (VT.is128BitVector() && !isAllOnesConstant(Item)) - return SDValue(); - } - if (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 || (EltVT == MVT::i64 && Subtarget.is64Bit())) { assert((VT.is128BitVector() || VT.is256BitVector() || @@ -35790,21 +35781,25 @@ // Load a scalar integer constant directly to XMM instead of transferring an // immediate value from GPR. - // TODO: Would it be better to load a 128-bit vector constant instead? - // vzext_movl (scalar_to_vector C) --> vzext_load &C + // vzext_movl (scalar_to_vector C) --> load [C,0...] if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) { if (auto *C = dyn_cast(N0.getOperand(0))) { - MVT PVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); - SDValue CP = DAG.getConstantPool(C->getConstantIntValue(), PVT); - Align Alignment = cast(CP)->getAlign(); + // Create a vector constant - scalar constant followed by zeros. EVT ScalarVT = N0.getOperand(0).getValueType(); - SDVTList MemTys = DAG.getVTList(VT, MVT::Other); - SDValue MemOps[] = {DAG.getEntryNode(), CP}; + Type *ScalarTy = ScalarVT.getTypeForEVT(*DAG.getContext()); + unsigned NumElts = VT.getVectorNumElements(); + Constant *Zero = ConstantInt::getNullValue(ScalarTy); + SmallVector ConstantVec(NumElts, Zero); + ConstantVec[0] = const_cast(C->getConstantIntValue()); + + // Load the vector constant from constant pool. + MVT PVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); + SDValue CP = DAG.getConstantPool(ConstantVector::get(ConstantVec), PVT); MachinePointerInfo MPI = MachinePointerInfo::getConstantPool(DAG.getMachineFunction()); - return DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, MemTys, MemOps, - ScalarVT, MPI, Alignment, - MachineMemOperand::MOLoad); + Align Alignment = cast(CP)->getAlign(); + return DAG.getLoad(VT, DL, DAG.getEntryNode(), CP, MPI, Alignment, + MachineMemOperand::MOLoad); } } Index: llvm/test/CodeGen/X86/avx-load-store.ll =================================================================== --- llvm/test/CodeGen/X86/avx-load-store.ll +++ llvm/test/CodeGen/X86/avx-load-store.ll @@ -220,7 +220,7 @@ ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jne .LBB9_4 ; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all -; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,0,0,0] ; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax) ; CHECK-NEXT: .LBB9_4: # %cif_mixed_test_any_check ; @@ -237,7 +237,7 @@ ; CHECK_O0-NEXT: jne .LBB9_3 ; CHECK_O0-NEXT: jmp .LBB9_4 ; CHECK_O0-NEXT: .LBB9_3: # %cif_mixed_test_all -; CHECK_O0-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK_O0-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967295,0,0,0] ; CHECK_O0-NEXT: vmovdqa %xmm0, %xmm0 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1 ; CHECK_O0-NEXT: # implicit-def: $rax Index: llvm/test/CodeGen/X86/avx2-arith.ll =================================================================== --- llvm/test/CodeGen/X86/avx2-arith.ll +++ llvm/test/CodeGen/X86/avx2-arith.ll @@ -347,13 +347,13 @@ define <8 x i32> @mul_const9(<8 x i32> %x) { ; X32-LABEL: mul_const9: ; X32: # %bb.0: -; X32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X32-NEXT: vmovdqa {{.*#+}} xmm1 = [2,0,0,0] ; X32-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: mul_const9: ; X64: # %bb.0: -; X64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [2,0,0,0] ; X64-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ; X64-NEXT: retq %y = mul <8 x i32> %x, Index: llvm/test/CodeGen/X86/combine-udiv.ll =================================================================== --- llvm/test/CodeGen/X86/combine-udiv.ll +++ llvm/test/CodeGen/X86/combine-udiv.ll @@ -590,8 +590,7 @@ ; ; XOP-LABEL: combine_vec_udiv_nonuniform2: ; XOP: # %bb.0: -; XOP-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero -; XOP-NEXT: vpshlw %xmm1, %xmm0, %xmm0 +; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: retq @@ -663,30 +662,17 @@ ; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: retq ; -; AVX1-LABEL: combine_vec_udiv_nonuniform4: -; AVX1: # %bb.0: -; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1 -; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1 -; AVX1-NEXT: vpackuswb %xmm1, %xmm1, %xmm1 -; AVX1-NEXT: vpsrlw $7, %xmm1, %xmm1 -; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] -; AVX1-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0 -; AVX1-NEXT: retq -; -; AVX2-LABEL: combine_vec_udiv_nonuniform4: -; AVX2: # %bb.0: -; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX2-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero -; AVX2-NEXT: vpmullw %xmm2, %xmm1, %xmm1 -; AVX2-NEXT: vpsrlw $8, %xmm1, %xmm1 -; AVX2-NEXT: vpackuswb %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vpsrlw $7, %xmm1, %xmm1 -; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1 -; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] -; AVX2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0 -; AVX2-NEXT: retq +; AVX-LABEL: combine_vec_udiv_nonuniform4: +; AVX: # %bb.0: +; AVX-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero +; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1 +; AVX-NEXT: vpsrlw $8, %xmm1, %xmm1 +; AVX-NEXT: vpackuswb %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpsrlw $7, %xmm1, %xmm1 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] +; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq ; ; XOP-LABEL: combine_vec_udiv_nonuniform4: ; XOP: # %bb.0: Index: llvm/test/CodeGen/X86/fcmp-constant.ll =================================================================== --- llvm/test/CodeGen/X86/fcmp-constant.ll +++ llvm/test/CodeGen/X86/fcmp-constant.ll @@ -92,7 +92,7 @@ define <2 x i64> @fcmp_ueq_v2f64_undef_elt() { ; CHECK-LABEL: fcmp_ueq_v2f64_undef_elt: ; CHECK: # %bb.0: -; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,0] ; CHECK-NEXT: retq %1 = fcmp ueq <2 x double> , %2 = sext <2 x i1> %1 to <2 x i64> Index: llvm/test/CodeGen/X86/insert-into-constant-vector.ll =================================================================== --- llvm/test/CodeGen/X86/insert-into-constant-vector.ll +++ llvm/test/CodeGen/X86/insert-into-constant-vector.ll @@ -129,9 +129,8 @@ define <2 x i64> @elt0_v2i64(i64 %x) { ; X32SSE-LABEL: elt0_v2i64: ; X32SSE: # %bb.0: -; X32SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; X32SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; X32SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],mem[0] ; X32SSE-NEXT: retl ; ; X64SSE2-LABEL: elt0_v2i64: @@ -149,9 +148,8 @@ ; ; X32AVX-LABEL: elt0_v2i64: ; X32AVX: # %bb.0: -; X32AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X32AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero -; X32AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; X32AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X32AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],mem[0] ; X32AVX-NEXT: retl ; ; X64AVX-LABEL: elt0_v2i64: @@ -364,7 +362,7 @@ ; X32SSE-LABEL: elt5_v8i64: ; X32SSE: # %bb.0: ; X32SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; X32SSE-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero +; X32SSE-NEXT: movaps {{.*#+}} xmm2 = [4,0,0,0] ; X32SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; X32SSE-NEXT: movaps {{.*#+}} xmm0 = [42,0,1,0] ; X32SSE-NEXT: movaps {{.*#+}} xmm1 = [2,0,3,0] @@ -393,7 +391,7 @@ ; X32AVX1-LABEL: elt5_v8i64: ; X32AVX1: # %bb.0: ; X32AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X32AVX1-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0] ; X32AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] ; X32AVX1-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm0, %ymm1 ; X32AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0] @@ -410,7 +408,7 @@ ; X32AVX2-LABEL: elt5_v8i64: ; X32AVX2: # %bb.0: ; X32AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32AVX2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X32AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0] ; X32AVX2-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] ; X32AVX2-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm0, %ymm1 ; X32AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0] @@ -428,7 +426,7 @@ ; X32AVX512F: # %bb.0: ; X32AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0] ; X32AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero -; X32AVX512F-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero +; X32AVX512F-NEXT: vmovaps {{.*#+}} xmm2 = [4,0,0,0] ; X32AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0] ; X32AVX512F-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm1, %ymm1 ; X32AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 Index: llvm/test/CodeGen/X86/packss.ll =================================================================== --- llvm/test/CodeGen/X86/packss.ll +++ llvm/test/CodeGen/X86/packss.ll @@ -159,13 +159,12 @@ ; X86-SSE-NEXT: psllq $63, %xmm1 ; X86-SSE-NEXT: psllq $63, %xmm0 ; X86-SSE-NEXT: psrlq $63, %xmm0 -; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = <1,0,u,u> +; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [1,0,0,0] ; X86-SSE-NEXT: pxor %xmm2, %xmm0 -; X86-SSE-NEXT: pcmpeqd %xmm3, %xmm3 -; X86-SSE-NEXT: paddq %xmm3, %xmm0 +; X86-SSE-NEXT: psubq %xmm2, %xmm0 ; X86-SSE-NEXT: psrlq $63, %xmm1 ; X86-SSE-NEXT: pxor %xmm2, %xmm1 -; X86-SSE-NEXT: paddq %xmm3, %xmm1 +; X86-SSE-NEXT: psubq %xmm2, %xmm1 ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X86-SSE-NEXT: packssdw %xmm1, %xmm0 Index: llvm/test/CodeGen/X86/pshufb-mask-comments.ll =================================================================== --- llvm/test/CodeGen/X86/pshufb-mask-comments.ll +++ llvm/test/CodeGen/X86/pshufb-mask-comments.ll @@ -54,7 +54,7 @@ define <16 x i8> @test5(<16 x i8> %V) { ; CHECK-LABEL: test5: ; CHECK: # %bb.0: -; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1,0] +; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1,0,0,0] ; CHECK-NEXT: movaps %xmm1, (%rax) ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1,1] ; CHECK-NEXT: movaps %xmm1, (%rax) Index: llvm/test/CodeGen/X86/ret-mmx.ll =================================================================== --- llvm/test/CodeGen/X86/ret-mmx.ll +++ llvm/test/CodeGen/X86/ret-mmx.ll @@ -32,7 +32,7 @@ define <2 x i32> @t3() nounwind { ; CHECK-LABEL: t3: ; CHECK: ## %bb.0: -; CHECK-NEXT: movaps {{.*#+}} xmm0 = <1,0,u,u> +; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1,0,0,0] ; CHECK-NEXT: retq ret <2 x i32> } Index: llvm/test/CodeGen/X86/sad.ll =================================================================== --- llvm/test/CodeGen/X86/sad.ll +++ llvm/test/CodeGen/X86/sad.ll @@ -544,7 +544,7 @@ ; SSE2: # %bb.0: # %entry ; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: movq $-1024, %rax # imm = 0xFC00 -; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,0,0] ; SSE2-NEXT: .p2align 4, 0x90 ; SSE2-NEXT: .LBB3_1: # %vector.body ; SSE2-NEXT: # =>This Inner Loop Header: Depth=1 @@ -994,52 +994,20 @@ ; SSE2-NEXT: movd %xmm1, %eax ; SSE2-NEXT: retq ; -; AVX1-LABEL: sad_unroll_nonzero_initial: -; AVX1: # %bb.0: # %bb -; AVX1-NEXT: vmovdqu (%rdi), %xmm0 -; AVX1-NEXT: vpsadbw (%rsi), %xmm0, %xmm0 -; AVX1-NEXT: vmovdqu (%rdx), %xmm1 -; AVX1-NEXT: vpsadbw (%rcx), %xmm1, %xmm1 -; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 -; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vmovd %xmm0, %eax -; AVX1-NEXT: retq -; -; AVX2-LABEL: sad_unroll_nonzero_initial: -; AVX2: # %bb.0: # %bb -; AVX2-NEXT: vmovdqu (%rdi), %xmm0 -; AVX2-NEXT: vpsadbw (%rsi), %xmm0, %xmm0 -; AVX2-NEXT: vmovdqu (%rdx), %xmm1 -; AVX2-NEXT: vpsadbw (%rcx), %xmm1, %xmm1 -; AVX2-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero -; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1 -; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vmovd %xmm0, %eax -; AVX2-NEXT: retq -; -; AVX512-LABEL: sad_unroll_nonzero_initial: -; AVX512: # %bb.0: # %bb -; AVX512-NEXT: vmovdqu (%rdi), %xmm0 -; AVX512-NEXT: vpsadbw (%rsi), %xmm0, %xmm0 -; AVX512-NEXT: vmovdqu (%rdx), %xmm1 -; AVX512-NEXT: vpsadbw (%rcx), %xmm1, %xmm1 -; AVX512-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero -; AVX512-NEXT: vpaddd %xmm2, %xmm1, %xmm1 -; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: retq +; AVX-LABEL: sad_unroll_nonzero_initial: +; AVX: # %bb.0: # %bb +; AVX-NEXT: vmovdqu (%rdi), %xmm0 +; AVX-NEXT: vpsadbw (%rsi), %xmm0, %xmm0 +; AVX-NEXT: vmovdqu (%rdx), %xmm1 +; AVX-NEXT: vpsadbw (%rcx), %xmm1, %xmm1 +; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] +; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] +; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vmovd %xmm0, %eax +; AVX-NEXT: retq bb: %tmp = load <16 x i8>, <16 x i8>* %arg, align 1 %tmp4 = load <16 x i8>, <16 x i8>* %arg1, align 1 Index: llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll =================================================================== --- llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll +++ llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll @@ -12,12 +12,8 @@ define i1 @dont_hit_assert(i24 signext %d) { ; CHECK-LABEL: dont_hit_assert: ; CHECK: # %bb.0: # %for.cond -; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero -; CHECK-NEXT: pxor %xmm1, %xmm1 -; CHECK-NEXT: packssdw %xmm1, %xmm0 -; CHECK-NEXT: packsswb %xmm0, %xmm0 -; CHECK-NEXT: pmovmskb %xmm0, %eax -; CHECK-NEXT: cmpb $-1, %al +; CHECK-NEXT: movb $-1, %al +; CHECK-NEXT: negb %al ; CHECK-NEXT: sete %al ; CHECK-NEXT: retq for.cond: Index: llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll =================================================================== --- llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll +++ llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll @@ -325,7 +325,7 @@ ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1 -; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u> +; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,0,0,0] ; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2 ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] @@ -452,7 +452,7 @@ ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1 -; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u> +; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,0,0,0] ; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2 ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] @@ -1314,7 +1314,7 @@ ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1 -; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u> +; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,0,0,0] ; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2 ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] Index: llvm/test/CodeGen/X86/vec_set-A.ll =================================================================== --- llvm/test/CodeGen/X86/vec_set-A.ll +++ llvm/test/CodeGen/X86/vec_set-A.ll @@ -10,7 +10,7 @@ ; ; X64-LABEL: test1: ; X64: # %bb.0: -; X64-NEXT: movaps {{.*#+}} xmm0 = [1,0] +; X64-NEXT: movaps {{.*#+}} xmm0 = [1,0,0,0] ; X64-NEXT: retq ret <2 x i64> < i64 1, i64 0 > } Index: llvm/test/CodeGen/X86/vec_shift2.ll =================================================================== --- llvm/test/CodeGen/X86/vec_shift2.ll +++ llvm/test/CodeGen/X86/vec_shift2.ll @@ -5,12 +5,12 @@ define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind { ; X32-LABEL: t1: ; X32: # %bb.0: -; X32-NEXT: psrlw {{\.LCPI.*}}, %xmm0 +; X32-NEXT: psrlw $14, %xmm0 ; X32-NEXT: retl ; ; X64-LABEL: t1: ; X64: # %bb.0: -; X64-NEXT: psrlw {{.*}}(%rip), %xmm0 +; X64-NEXT: psrlw $14, %xmm0 ; X64-NEXT: retq %tmp1 = bitcast <2 x i64> %b1 to <8 x i16> %tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > to <8 x i16>) ) nounwind readnone Index: llvm/test/CodeGen/X86/vector-lzcnt-128.ll =================================================================== --- llvm/test/CodeGen/X86/vector-lzcnt-128.ll +++ llvm/test/CodeGen/X86/vector-lzcnt-128.ll @@ -1666,17 +1666,17 @@ define <2 x i64> @foldv2i64() nounwind { ; SSE-LABEL: foldv2i64: ; SSE: # %bb.0: -; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0] +; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0,0,0] ; SSE-NEXT: retq ; ; NOBW-LABEL: foldv2i64: ; NOBW: # %bb.0: -; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0] +; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0,0,0] ; NOBW-NEXT: retq ; ; AVX512VLBWDQ-LABEL: foldv2i64: ; AVX512VLBWDQ: # %bb.0: -; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0] +; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0,0,0] ; AVX512VLBWDQ-NEXT: retq ; ; X32-SSE-LABEL: foldv2i64: @@ -1690,17 +1690,17 @@ define <2 x i64> @foldv2i64u() nounwind { ; SSE-LABEL: foldv2i64u: ; SSE: # %bb.0: -; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0] +; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0,0,0] ; SSE-NEXT: retq ; ; NOBW-LABEL: foldv2i64u: ; NOBW: # %bb.0: -; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0] +; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0,0,0] ; NOBW-NEXT: retq ; ; AVX512VLBWDQ-LABEL: foldv2i64u: ; AVX512VLBWDQ: # %bb.0: -; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0] +; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0,0,0] ; AVX512VLBWDQ-NEXT: retq ; ; X32-SSE-LABEL: foldv2i64u: Index: llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll +++ llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll @@ -713,7 +713,7 @@ ; ; AVX512VL-LABEL: shuffle_v16i16_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00: ; AVX512VL: # %bb.0: -; AVX512VL-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [15,0,0,0] ; AVX512VL-NEXT: vpermw %ymm0, %ymm1, %ymm0 ; AVX512VL-NEXT: retq ; Index: llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll +++ llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll @@ -1600,21 +1600,21 @@ ; ; AVX2-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00: ; AVX2: # %bb.0: -; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [15,0,0,0] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,0,1] ; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512VLBW-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00: ; AVX512VLBW: # %bb.0: -; AVX512VLBW-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm1 = [15,0,0,0] ; AVX512VLBW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,0,1] ; AVX512VLBW-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; ; AVX512VLVBMI-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00: ; AVX512VLVBMI: # %bb.0: -; AVX512VLVBMI-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; AVX512VLVBMI-NEXT: vmovdqa {{.*#+}} xmm1 = [31,0,0,0] ; AVX512VLVBMI-NEXT: vpermb %ymm0, %ymm1, %ymm0 ; AVX512VLVBMI-NEXT: retq ; @@ -1629,7 +1629,7 @@ ; ; XOPAVX2-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00: ; XOPAVX2: # %bb.0: -; XOPAVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [15,0,0,0] ; XOPAVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,0,1] ; XOPAVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq @@ -2787,7 +2787,7 @@ ; AVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16: ; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0] ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 @@ -2801,7 +2801,7 @@ ; XOPAVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; XOPAVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0] +; XOPAVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0] ; XOPAVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; XOPAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 Index: llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll +++ llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll @@ -187,7 +187,7 @@ ; ; AVX2OR512VL-LABEL: shuffle_v8f32_70000000: ; AVX2OR512VL: # %bb.0: -; AVX2OR512VL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; AVX2OR512VL-NEXT: vmovaps {{.*#+}} xmm1 = [7,0,0,0] ; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; AVX2OR512VL-NEXT: retq %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> @@ -1509,7 +1509,7 @@ ; ; AVX2OR512VL-LABEL: shuffle_v8i32_70000000: ; AVX2OR512VL: # %bb.0: -; AVX2OR512VL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; AVX2OR512VL-NEXT: vmovaps {{.*#+}} xmm1 = [7,0,0,0] ; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; AVX2OR512VL-NEXT: retq %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> Index: llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll +++ llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll @@ -201,13 +201,13 @@ define <32 x i16> @shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<32 x i16> %a) { ; KNL-LABEL: shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; KNL: ## %bb.0: -; KNL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; KNL-NEXT: vmovaps {{.*#+}} xmm1 = [65535,0,0,0] ; KNL-NEXT: vandps %ymm1, %ymm0, %ymm0 ; KNL-NEXT: retq ; ; SKX-LABEL: shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; SKX: ## %bb.0: -; SKX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; SKX-NEXT: vmovaps {{.*#+}} xmm1 = [65535,0,0,0] ; SKX-NEXT: vandps %zmm1, %zmm0, %zmm0 ; SKX-NEXT: retq %shuffle = shufflevector <32 x i16> %a, <32 x i16> zeroinitializer, <32 x i32> Index: llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll +++ llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll @@ -109,7 +109,7 @@ define <64 x i8> @shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<64 x i8> %a) { ; AVX512F-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; AVX512F: # %bb.0: -; AVX512F-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; AVX512F-NEXT: vmovaps {{.*#+}} xmm1 = [255,0,0,0] ; AVX512F-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX512F-NEXT: retq ; @@ -120,7 +120,7 @@ ; ; AVX512DQ-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; AVX512DQ: # %bb.0: -; AVX512DQ-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; AVX512DQ-NEXT: vmovaps {{.*#+}} xmm1 = [255,0,0,0] ; AVX512DQ-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: retq ; Index: llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll +++ llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll @@ -142,7 +142,7 @@ define <8 x double> @shuffle_v8f64_70000000(<8 x double> %a, <8 x double> %b) { ; ALL-LABEL: shuffle_v8f64_70000000: ; ALL: # %bb.0: -; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; ALL-NEXT: vmovaps {{.*#+}} xmm1 = [7,0,0,0] ; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 ; ALL-NEXT: ret{{[l|q]}} %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> @@ -960,7 +960,7 @@ define <8 x i64> @shuffle_v8i64_70000000(<8 x i64> %a, <8 x i64> %b) { ; ALL-LABEL: shuffle_v8i64_70000000: ; ALL: # %bb.0: -; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; ALL-NEXT: vmovaps {{.*#+}} xmm1 = [7,0,0,0] ; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0 ; ALL-NEXT: ret{{[l|q]}} %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> Index: llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll +++ llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll @@ -899,9 +899,8 @@ define <8 x double> @combine_vpermi2var_8f64_as_permpd(<8 x double> %x0, <8 x double> %x1, i64 %a2) { ; X86-LABEL: combine_vpermi2var_8f64_as_permpd: ; X86: # %bb.0: -; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero -; X86-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero -; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm3[0],xmm2[0] +; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero +; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0] ; X86-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-NEXT: vinsertf64x4 $1, {{\.LCPI.*}}, %zmm2, %zmm2 ; X86-NEXT: vpermi2pd %zmm1, %zmm0, %zmm2 Index: llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll +++ llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll @@ -131,25 +131,14 @@ } define <4 x double> @demandedelts_vpermil2pd256_as_shufpd(<4 x double> %a0, <4 x double> %a1, i64 %a2) { -; X86-AVX-LABEL: demandedelts_vpermil2pd256_as_shufpd: -; X86-AVX: # %bb.0: -; X86-AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero -; X86-AVX-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero -; X86-AVX-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0] -; X86-AVX-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2 -; X86-AVX-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0 -; X86-AVX-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3] -; X86-AVX-NEXT: retl -; -; X86-AVX2-LABEL: demandedelts_vpermil2pd256_as_shufpd: -; X86-AVX2: # %bb.0: -; X86-AVX2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero -; X86-AVX2-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero -; X86-AVX2-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm3[0],xmm2[0] -; X86-AVX2-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2 -; X86-AVX2-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0 -; X86-AVX2-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3] -; X86-AVX2-NEXT: retl +; X86-LABEL: demandedelts_vpermil2pd256_as_shufpd: +; X86: # %bb.0: +; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero +; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0] +; X86-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2 +; X86-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0 +; X86-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3] +; X86-NEXT: retl ; ; X64-LABEL: demandedelts_vpermil2pd256_as_shufpd: ; X64: # %bb.0: Index: llvm/test/CodeGen/X86/vector-shuffle-v1.ll =================================================================== --- llvm/test/CodeGen/X86/vector-shuffle-v1.ll +++ llvm/test/CodeGen/X86/vector-shuffle-v1.ll @@ -46,7 +46,7 @@ ; AVX512F-NEXT: vpsllq $63, %xmm0, %xmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512F-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; AVX512F-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,0] ; AVX512F-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7] ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} @@ -60,7 +60,7 @@ ; AVX512VL-NEXT: vptestmq %xmm0, %xmm0, %k1 ; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1} {z} -; AVX512VL-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero +; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [18446744073709551615,0] ; AVX512VL-NEXT: vpalignr {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4,5,6,7] ; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1 ; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z} @@ -71,7 +71,7 @@ ; VL_BW_DQ-NEXT: vpsllq $63, %xmm0, %xmm0 ; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0 ; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0 -; VL_BW_DQ-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; VL_BW_DQ-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,0] ; VL_BW_DQ-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7] ; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0 ; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0 Index: llvm/test/CodeGen/X86/vector-tzcnt-128.ll =================================================================== --- llvm/test/CodeGen/X86/vector-tzcnt-128.ll +++ llvm/test/CodeGen/X86/vector-tzcnt-128.ll @@ -1576,32 +1576,32 @@ define <2 x i64> @foldv2i64() nounwind { ; SSE-LABEL: foldv2i64: ; SSE: # %bb.0: -; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0] +; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,0,0] ; SSE-NEXT: retq ; ; AVX-LABEL: foldv2i64: ; AVX: # %bb.0: -; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; AVX-NEXT: retq ; ; AVX512VPOPCNTDQ-LABEL: foldv2i64: ; AVX512VPOPCNTDQ: # %bb.0: -; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; AVX512VPOPCNTDQ-NEXT: retq ; ; AVX512VPOPCNTDQVL-LABEL: foldv2i64: ; AVX512VPOPCNTDQVL: # %bb.0: -; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; AVX512VPOPCNTDQVL-NEXT: retq ; ; BITALG_NOVLX-LABEL: foldv2i64: ; BITALG_NOVLX: # %bb.0: -; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; BITALG_NOVLX-NEXT: retq ; ; BITALG-LABEL: foldv2i64: ; BITALG: # %bb.0: -; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; BITALG-NEXT: retq ; ; X32-SSE-LABEL: foldv2i64: @@ -1615,32 +1615,32 @@ define <2 x i64> @foldv2i64u() nounwind { ; SSE-LABEL: foldv2i64u: ; SSE: # %bb.0: -; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0] +; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,0,0] ; SSE-NEXT: retq ; ; AVX-LABEL: foldv2i64u: ; AVX: # %bb.0: -; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; AVX-NEXT: retq ; ; AVX512VPOPCNTDQ-LABEL: foldv2i64u: ; AVX512VPOPCNTDQ: # %bb.0: -; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; AVX512VPOPCNTDQ-NEXT: retq ; ; AVX512VPOPCNTDQVL-LABEL: foldv2i64u: ; AVX512VPOPCNTDQVL: # %bb.0: -; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; AVX512VPOPCNTDQVL-NEXT: retq ; ; BITALG_NOVLX-LABEL: foldv2i64u: ; BITALG_NOVLX: # %bb.0: -; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; BITALG_NOVLX-NEXT: retq ; ; BITALG-LABEL: foldv2i64u: ; BITALG: # %bb.0: -; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0] +; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0] ; BITALG-NEXT: retq ; ; X32-SSE-LABEL: foldv2i64u: