diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h --- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h +++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h @@ -53,6 +53,13 @@ const TargetRegisterInfo *TRI) const override; bool canCopyGluedNodeDuringSchedule(SDNode *N) const override; + +protected: + virtual MachineInstr *foldMemoryOperandImpl( + MachineFunction &MF, MachineInstr &MI, ArrayRef Ops, + MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, + LiveIntervals *LIS = nullptr) const override; + private: void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override; }; diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp --- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -152,3 +152,35 @@ return false; } + +MachineInstr *Thumb1InstrInfo::foldMemoryOperandImpl( + MachineFunction &MF, MachineInstr &MI, ArrayRef Ops, + MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, + LiveIntervals *LIS) const { + // Replace: + // ldr Rd, func address + // blx Rd + // with: + // bl func + + if (MI.getOpcode() == ARM::tBLXr && LoadMI.getOpcode() == ARM::tLDRpci && + MI.getParent() == LoadMI.getParent()) { + unsigned CPI = LoadMI.getOperand(1).getIndex(); + const MachineConstantPool *MCP = MF.getConstantPool(); + const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI]; + assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry"); + const Constant *Callee = cast(CPE.Val.ConstVal); + const char *FuncName = MF.createExternalSymbolName(Callee->getName()); + MachineInstrBuilder MIB = BuildMI(*MI.getParent(), InsertPt, MI.getDebugLoc(), get(ARM::tBL)) + .add(predOps(ARMCC::AL)) + .addExternalSymbol(FuncName); + for (auto &MO: MI.implicit_operands()) + if (MO.isReg()) + MIB.addReg(MO.getReg(), RegState::Implicit | RegState::Kill); + else if (MO.isRegMask()) + MIB.add(MO); + return MIB.getInstr(); + } + + return nullptr; +}