diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -14,6 +14,7 @@ #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "Utils/RISCVMatInt.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/Support/Alignment.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" @@ -160,8 +161,9 @@ } // Merge an ADDI into the offset of a load/store instruction where possible. -// (load (add base, off), 0) -> (load base, off) -// (store val, (add base, off)) -> (store val, base, off) +// (load (addi base, off1), off2) -> (load base, off1+off2) +// (store val, (addi base, off1), off2) -> (store val, base, off1+off2) +// This is possible when off1+off2 fits a 12-bit immediate. void RISCVDAGToDAGISel::doPeepholeLoadStoreADDI() { SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode()); ++Position; @@ -202,10 +204,7 @@ break; } - // Currently, the load/store offset must be 0 to be considered for this - // peephole optimisation. - if (!isa(N->getOperand(OffsetOpIdx)) || - N->getConstantOperandVal(OffsetOpIdx) != 0) + if (!isa(N->getOperand(OffsetOpIdx))) continue; SDValue Base = N->getOperand(BaseOpIdx); @@ -215,18 +214,39 @@ continue; SDValue ImmOperand = Base.getOperand(1); + uint64_t Offset2 = N->getConstantOperandVal(OffsetOpIdx); if (auto Const = dyn_cast(ImmOperand)) { - ImmOperand = CurDAG->getTargetConstant( - Const->getSExtValue(), SDLoc(ImmOperand), ImmOperand.getValueType()); + int64_t Offset1 = Const->getSExtValue(); + int64_t CombinedOffset = Offset1 + Offset2; + if (!isInt<12>(CombinedOffset)) + continue; + ImmOperand = CurDAG->getTargetConstant(CombinedOffset, SDLoc(ImmOperand), + ImmOperand.getValueType()); } else if (auto GA = dyn_cast(ImmOperand)) { + // If the off1 in (addi base, off1) is a global variable's address (its + // low part, really), then we can rely on the alignment of that variable + // to provide a margin of safety before off1 can overflow the 12 bits. + // Check if off2 falls within that margin; if so off1+off2 can't overflow. + const DataLayout &DL = CurDAG->getDataLayout(); + Align Alignment = GA->getGlobal()->getPointerAlignment(DL); + if (Offset2 != 0 && Alignment <= Offset2) + continue; + int64_t Offset1 = GA->getOffset(); + int64_t CombinedOffset = Offset1 + Offset2; ImmOperand = CurDAG->getTargetGlobalAddress( GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(), - GA->getOffset(), GA->getTargetFlags()); + CombinedOffset, GA->getTargetFlags()); } else if (auto CP = dyn_cast(ImmOperand)) { + // Ditto. + Align Alignment = CP->getAlign(); + if (Offset2 != 0 && Alignment <= Offset2) + continue; + int64_t Offset1 = CP->getOffset(); + int64_t CombinedOffset = Offset1 + Offset2; ImmOperand = CurDAG->getTargetConstantPool( CP->getConstVal(), ImmOperand.getValueType(), CP->getAlign(), - CP->getOffset(), CP->getTargetFlags()); + CombinedOffset, CP->getTargetFlags()); } else { continue; } diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll --- a/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll @@ -1,15 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32-LP64 +; RUN: | FileCheck %s -check-prefix=ILP32 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32-LP64 +; RUN: | FileCheck %s -check-prefix=LP64 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32F-LP64F +; RUN: | FileCheck %s -check-prefix=ILP32F ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32F-LP64F +; RUN: | FileCheck %s -check-prefix=LP64F ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32D-LP64D +; RUN: | FileCheck %s -check-prefix=ILP32D ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32D-LP64D +; RUN: | FileCheck %s -check-prefix=LP64D @var = global [32 x float] zeroinitializer @@ -20,113 +21,529 @@ ; something appropriate. define void @callee() nounwind { -; ILP32-LP64-LABEL: callee: -; ILP32-LP64: # %bb.0: -; ILP32-LP64-NEXT: lui a0, %hi(var) -; ILP32-LP64-NEXT: flw ft0, %lo(var)(a0) -; ILP32-LP64-NEXT: addi a1, a0, %lo(var) -; ILP32-LP64-NEXT: flw ft1, 4(a1) -; ILP32-LP64-NEXT: flw ft2, 8(a1) -; ILP32-LP64-NEXT: flw ft3, 12(a1) -; ILP32-LP64-NEXT: flw ft4, 16(a1) -; ILP32-LP64-NEXT: flw ft5, 20(a1) -; ILP32-LP64-NEXT: flw ft6, 24(a1) -; ILP32-LP64-NEXT: flw ft7, 28(a1) -; ILP32-LP64-NEXT: flw fa0, 32(a1) -; ILP32-LP64-NEXT: flw fa1, 36(a1) -; ILP32-LP64-NEXT: flw fa2, 40(a1) -; ILP32-LP64-NEXT: flw fa3, 44(a1) -; ILP32-LP64-NEXT: flw fa4, 48(a1) -; ILP32-LP64-NEXT: flw fa5, 52(a1) -; ILP32-LP64-NEXT: flw fa6, 56(a1) -; ILP32-LP64-NEXT: flw fa7, 60(a1) -; ILP32-LP64-NEXT: flw ft8, 64(a1) -; ILP32-LP64-NEXT: flw ft9, 68(a1) -; ILP32-LP64-NEXT: flw ft10, 72(a1) -; ILP32-LP64-NEXT: flw ft11, 76(a1) -; ILP32-LP64-NEXT: flw fs0, 80(a1) -; ILP32-LP64-NEXT: flw fs1, 84(a1) -; ILP32-LP64-NEXT: flw fs2, 88(a1) -; ILP32-LP64-NEXT: flw fs3, 92(a1) -; ILP32-LP64-NEXT: flw fs4, 96(a1) -; ILP32-LP64-NEXT: flw fs5, 100(a1) -; ILP32-LP64-NEXT: flw fs6, 104(a1) -; ILP32-LP64-NEXT: flw fs7, 108(a1) -; ILP32-LP64-NEXT: flw fs8, 124(a1) -; ILP32-LP64-NEXT: flw fs9, 120(a1) -; ILP32-LP64-NEXT: flw fs10, 116(a1) -; ILP32-LP64-NEXT: flw fs11, 112(a1) -; ILP32-LP64-NEXT: fsw fs8, 124(a1) -; ILP32-LP64-NEXT: fsw fs9, 120(a1) -; ILP32-LP64-NEXT: fsw fs10, 116(a1) -; ILP32-LP64-NEXT: fsw fs11, 112(a1) -; ILP32-LP64-NEXT: fsw fs7, 108(a1) -; ILP32-LP64-NEXT: fsw fs6, 104(a1) -; ILP32-LP64-NEXT: fsw fs5, 100(a1) -; ILP32-LP64-NEXT: fsw fs4, 96(a1) -; ILP32-LP64-NEXT: fsw fs3, 92(a1) -; ILP32-LP64-NEXT: fsw fs2, 88(a1) -; ILP32-LP64-NEXT: fsw fs1, 84(a1) -; ILP32-LP64-NEXT: fsw fs0, 80(a1) -; ILP32-LP64-NEXT: fsw ft11, 76(a1) -; ILP32-LP64-NEXT: fsw ft10, 72(a1) -; ILP32-LP64-NEXT: fsw ft9, 68(a1) -; ILP32-LP64-NEXT: fsw ft8, 64(a1) -; ILP32-LP64-NEXT: fsw fa7, 60(a1) -; ILP32-LP64-NEXT: fsw fa6, 56(a1) -; ILP32-LP64-NEXT: fsw fa5, 52(a1) -; ILP32-LP64-NEXT: fsw fa4, 48(a1) -; ILP32-LP64-NEXT: fsw fa3, 44(a1) -; ILP32-LP64-NEXT: fsw fa2, 40(a1) -; ILP32-LP64-NEXT: fsw fa1, 36(a1) -; ILP32-LP64-NEXT: fsw fa0, 32(a1) -; ILP32-LP64-NEXT: fsw ft7, 28(a1) -; ILP32-LP64-NEXT: fsw ft6, 24(a1) -; ILP32-LP64-NEXT: fsw ft5, 20(a1) -; ILP32-LP64-NEXT: fsw ft4, 16(a1) -; ILP32-LP64-NEXT: fsw ft3, 12(a1) -; ILP32-LP64-NEXT: fsw ft2, 8(a1) -; ILP32-LP64-NEXT: fsw ft1, 4(a1) -; ILP32-LP64-NEXT: fsw ft0, %lo(var)(a0) -; ILP32-LP64-NEXT: ret +; ILP32-LABEL: callee: +; ILP32: # %bb.0: +; ILP32-NEXT: lui a0, %hi(var) +; ILP32-NEXT: flw ft0, %lo(var)(a0) +; ILP32-NEXT: flw ft1, %lo(var+4)(a0) +; ILP32-NEXT: flw ft2, %lo(var+8)(a0) +; ILP32-NEXT: flw ft3, %lo(var+12)(a0) +; ILP32-NEXT: addi a1, a0, %lo(var) +; ILP32-NEXT: flw ft4, 16(a1) +; ILP32-NEXT: flw ft5, 20(a1) +; ILP32-NEXT: flw ft6, 24(a1) +; ILP32-NEXT: flw ft7, 28(a1) +; ILP32-NEXT: flw fa0, 32(a1) +; ILP32-NEXT: flw fa1, 36(a1) +; ILP32-NEXT: flw fa2, 40(a1) +; ILP32-NEXT: flw fa3, 44(a1) +; ILP32-NEXT: flw fa4, 48(a1) +; ILP32-NEXT: flw fa5, 52(a1) +; ILP32-NEXT: flw fa6, 56(a1) +; ILP32-NEXT: flw fa7, 60(a1) +; ILP32-NEXT: flw ft8, 64(a1) +; ILP32-NEXT: flw ft9, 68(a1) +; ILP32-NEXT: flw ft10, 72(a1) +; ILP32-NEXT: flw ft11, 76(a1) +; ILP32-NEXT: flw fs0, 80(a1) +; ILP32-NEXT: flw fs1, 84(a1) +; ILP32-NEXT: flw fs2, 88(a1) +; ILP32-NEXT: flw fs3, 92(a1) +; ILP32-NEXT: flw fs4, 96(a1) +; ILP32-NEXT: flw fs5, 100(a1) +; ILP32-NEXT: flw fs6, 104(a1) +; ILP32-NEXT: flw fs7, 108(a1) +; ILP32-NEXT: flw fs8, 124(a1) +; ILP32-NEXT: flw fs9, 120(a1) +; ILP32-NEXT: flw fs10, 116(a1) +; ILP32-NEXT: flw fs11, 112(a1) +; ILP32-NEXT: fsw fs8, 124(a1) +; ILP32-NEXT: fsw fs9, 120(a1) +; ILP32-NEXT: fsw fs10, 116(a1) +; ILP32-NEXT: fsw fs11, 112(a1) +; ILP32-NEXT: fsw fs7, 108(a1) +; ILP32-NEXT: fsw fs6, 104(a1) +; ILP32-NEXT: fsw fs5, 100(a1) +; ILP32-NEXT: fsw fs4, 96(a1) +; ILP32-NEXT: fsw fs3, 92(a1) +; ILP32-NEXT: fsw fs2, 88(a1) +; ILP32-NEXT: fsw fs1, 84(a1) +; ILP32-NEXT: fsw fs0, 80(a1) +; ILP32-NEXT: fsw ft11, 76(a1) +; ILP32-NEXT: fsw ft10, 72(a1) +; ILP32-NEXT: fsw ft9, 68(a1) +; ILP32-NEXT: fsw ft8, 64(a1) +; ILP32-NEXT: fsw fa7, 60(a1) +; ILP32-NEXT: fsw fa6, 56(a1) +; ILP32-NEXT: fsw fa5, 52(a1) +; ILP32-NEXT: fsw fa4, 48(a1) +; ILP32-NEXT: fsw fa3, 44(a1) +; ILP32-NEXT: fsw fa2, 40(a1) +; ILP32-NEXT: fsw fa1, 36(a1) +; ILP32-NEXT: fsw fa0, 32(a1) +; ILP32-NEXT: fsw ft7, 28(a1) +; ILP32-NEXT: fsw ft6, 24(a1) +; ILP32-NEXT: fsw ft5, 20(a1) +; ILP32-NEXT: fsw ft4, 16(a1) +; ILP32-NEXT: fsw ft3, %lo(var+12)(a0) +; ILP32-NEXT: fsw ft2, %lo(var+8)(a0) +; ILP32-NEXT: fsw ft1, %lo(var+4)(a0) +; ILP32-NEXT: fsw ft0, %lo(var)(a0) +; ILP32-NEXT: ret ; -; ILP32F-LP64F-LABEL: callee: -; ILP32F-LP64F: # %bb.0: -; ILP32F-LP64F-NEXT: addi sp, sp, -48 -; ILP32F-LP64F-NEXT: fsw fs0, 44(sp) -; ILP32F-LP64F-NEXT: fsw fs1, 40(sp) -; ILP32F-LP64F-NEXT: fsw fs2, 36(sp) -; ILP32F-LP64F-NEXT: fsw fs3, 32(sp) -; ILP32F-LP64F-NEXT: fsw fs4, 28(sp) -; ILP32F-LP64F-NEXT: fsw fs5, 24(sp) -; ILP32F-LP64F-NEXT: fsw fs6, 20(sp) -; ILP32F-LP64F-NEXT: fsw fs7, 16(sp) -; ILP32F-LP64F-NEXT: fsw fs8, 12(sp) -; ILP32F-LP64F-NEXT: fsw fs9, 8(sp) -; ILP32F-LP64F-NEXT: fsw fs10, 4(sp) -; ILP32F-LP64F-NEXT: fsw fs11, 0(sp) -; ILP32F-LP64F-NEXT: lui a0, %hi(var) -; ILP32F-LP64F-NEXT: flw ft0, %lo(var)(a0) -; ILP32F-LP64F-NEXT: addi a1, a0, %lo(var) +; LP64-LABEL: callee: +; LP64: # %bb.0: +; LP64-NEXT: lui a0, %hi(var) +; LP64-NEXT: flw ft0, %lo(var)(a0) +; LP64-NEXT: flw ft1, %lo(var+4)(a0) +; LP64-NEXT: flw ft2, %lo(var+8)(a0) +; LP64-NEXT: flw ft3, %lo(var+12)(a0) +; LP64-NEXT: addi a1, a0, %lo(var) +; LP64-NEXT: flw ft4, 16(a1) +; LP64-NEXT: flw ft5, 20(a1) +; LP64-NEXT: flw ft6, 24(a1) +; LP64-NEXT: flw ft7, 28(a1) +; LP64-NEXT: flw fa0, 32(a1) +; LP64-NEXT: flw fa1, 36(a1) +; LP64-NEXT: flw fa2, 40(a1) +; LP64-NEXT: flw fa3, 44(a1) +; LP64-NEXT: flw fa4, 48(a1) +; LP64-NEXT: flw fa5, 52(a1) +; LP64-NEXT: flw fa6, 56(a1) +; LP64-NEXT: flw fa7, 60(a1) +; LP64-NEXT: flw ft8, 64(a1) +; LP64-NEXT: flw ft9, 68(a1) +; LP64-NEXT: flw ft10, 72(a1) +; LP64-NEXT: flw ft11, 76(a1) +; LP64-NEXT: flw fs0, 80(a1) +; LP64-NEXT: flw fs1, 84(a1) +; LP64-NEXT: flw fs2, 88(a1) +; LP64-NEXT: flw fs3, 92(a1) +; LP64-NEXT: flw fs4, 96(a1) +; LP64-NEXT: flw fs5, 100(a1) +; LP64-NEXT: flw fs6, 104(a1) +; LP64-NEXT: flw fs7, 108(a1) +; LP64-NEXT: flw fs8, 124(a1) +; LP64-NEXT: flw fs9, 120(a1) +; LP64-NEXT: flw fs10, 116(a1) +; LP64-NEXT: flw fs11, 112(a1) +; LP64-NEXT: fsw fs8, 124(a1) +; LP64-NEXT: fsw fs9, 120(a1) +; LP64-NEXT: fsw fs10, 116(a1) +; LP64-NEXT: fsw fs11, 112(a1) +; LP64-NEXT: fsw fs7, 108(a1) +; LP64-NEXT: fsw fs6, 104(a1) +; LP64-NEXT: fsw fs5, 100(a1) +; LP64-NEXT: fsw fs4, 96(a1) +; LP64-NEXT: fsw fs3, 92(a1) +; LP64-NEXT: fsw fs2, 88(a1) +; LP64-NEXT: fsw fs1, 84(a1) +; LP64-NEXT: fsw fs0, 80(a1) +; LP64-NEXT: fsw ft11, 76(a1) +; LP64-NEXT: fsw ft10, 72(a1) +; LP64-NEXT: fsw ft9, 68(a1) +; LP64-NEXT: fsw ft8, 64(a1) +; LP64-NEXT: fsw fa7, 60(a1) +; LP64-NEXT: fsw fa6, 56(a1) +; LP64-NEXT: fsw fa5, 52(a1) +; LP64-NEXT: fsw fa4, 48(a1) +; LP64-NEXT: fsw fa3, 44(a1) +; LP64-NEXT: fsw fa2, 40(a1) +; LP64-NEXT: fsw fa1, 36(a1) +; LP64-NEXT: fsw fa0, 32(a1) +; LP64-NEXT: fsw ft7, 28(a1) +; LP64-NEXT: fsw ft6, 24(a1) +; LP64-NEXT: fsw ft5, 20(a1) +; LP64-NEXT: fsw ft4, 16(a1) +; LP64-NEXT: fsw ft3, %lo(var+12)(a0) +; LP64-NEXT: fsw ft2, %lo(var+8)(a0) +; LP64-NEXT: fsw ft1, %lo(var+4)(a0) +; LP64-NEXT: fsw ft0, %lo(var)(a0) +; LP64-NEXT: ret ; -; ILP32D-LP64D-LABEL: callee: -; ILP32D-LP64D: # %bb.0: -; ILP32D-LP64D-NEXT: addi sp, sp, -96 -; ILP32D-LP64D-NEXT: fsd fs0, 88(sp) -; ILP32D-LP64D-NEXT: fsd fs1, 80(sp) -; ILP32D-LP64D-NEXT: fsd fs2, 72(sp) -; ILP32D-LP64D-NEXT: fsd fs3, 64(sp) -; ILP32D-LP64D-NEXT: fsd fs4, 56(sp) -; ILP32D-LP64D-NEXT: fsd fs5, 48(sp) -; ILP32D-LP64D-NEXT: fsd fs6, 40(sp) -; ILP32D-LP64D-NEXT: fsd fs7, 32(sp) -; ILP32D-LP64D-NEXT: fsd fs8, 24(sp) -; ILP32D-LP64D-NEXT: fsd fs9, 16(sp) -; ILP32D-LP64D-NEXT: fsd fs10, 8(sp) -; ILP32D-LP64D-NEXT: fsd fs11, 0(sp) -; ILP32D-LP64D-NEXT: lui a0, %hi(var) -; ILP32D-LP64D-NEXT: flw ft0, %lo(var)(a0) -; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var) +; ILP32F-LABEL: callee: +; ILP32F: # %bb.0: +; ILP32F-NEXT: addi sp, sp, -48 +; ILP32F-NEXT: fsw fs0, 44(sp) +; ILP32F-NEXT: fsw fs1, 40(sp) +; ILP32F-NEXT: fsw fs2, 36(sp) +; ILP32F-NEXT: fsw fs3, 32(sp) +; ILP32F-NEXT: fsw fs4, 28(sp) +; ILP32F-NEXT: fsw fs5, 24(sp) +; ILP32F-NEXT: fsw fs6, 20(sp) +; ILP32F-NEXT: fsw fs7, 16(sp) +; ILP32F-NEXT: fsw fs8, 12(sp) +; ILP32F-NEXT: fsw fs9, 8(sp) +; ILP32F-NEXT: fsw fs10, 4(sp) +; ILP32F-NEXT: fsw fs11, 0(sp) +; ILP32F-NEXT: lui a0, %hi(var) +; ILP32F-NEXT: flw ft0, %lo(var)(a0) +; ILP32F-NEXT: flw ft1, %lo(var+4)(a0) +; ILP32F-NEXT: flw ft2, %lo(var+8)(a0) +; ILP32F-NEXT: flw ft3, %lo(var+12)(a0) +; ILP32F-NEXT: addi a1, a0, %lo(var) +; ILP32F-NEXT: flw ft4, 16(a1) +; ILP32F-NEXT: flw ft5, 20(a1) +; ILP32F-NEXT: flw ft6, 24(a1) +; ILP32F-NEXT: flw ft7, 28(a1) +; ILP32F-NEXT: flw fa0, 32(a1) +; ILP32F-NEXT: flw fa1, 36(a1) +; ILP32F-NEXT: flw fa2, 40(a1) +; ILP32F-NEXT: flw fa3, 44(a1) +; ILP32F-NEXT: flw fa4, 48(a1) +; ILP32F-NEXT: flw fa5, 52(a1) +; ILP32F-NEXT: flw fa6, 56(a1) +; ILP32F-NEXT: flw fa7, 60(a1) +; ILP32F-NEXT: flw ft8, 64(a1) +; ILP32F-NEXT: flw ft9, 68(a1) +; ILP32F-NEXT: flw ft10, 72(a1) +; ILP32F-NEXT: flw ft11, 76(a1) +; ILP32F-NEXT: flw fs0, 80(a1) +; ILP32F-NEXT: flw fs1, 84(a1) +; ILP32F-NEXT: flw fs2, 88(a1) +; ILP32F-NEXT: flw fs3, 92(a1) +; ILP32F-NEXT: flw fs4, 96(a1) +; ILP32F-NEXT: flw fs5, 100(a1) +; ILP32F-NEXT: flw fs6, 104(a1) +; ILP32F-NEXT: flw fs7, 108(a1) +; ILP32F-NEXT: flw fs8, 124(a1) +; ILP32F-NEXT: flw fs9, 120(a1) +; ILP32F-NEXT: flw fs10, 116(a1) +; ILP32F-NEXT: flw fs11, 112(a1) +; ILP32F-NEXT: fsw fs8, 124(a1) +; ILP32F-NEXT: fsw fs9, 120(a1) +; ILP32F-NEXT: fsw fs10, 116(a1) +; ILP32F-NEXT: fsw fs11, 112(a1) +; ILP32F-NEXT: fsw fs7, 108(a1) +; ILP32F-NEXT: fsw fs6, 104(a1) +; ILP32F-NEXT: fsw fs5, 100(a1) +; ILP32F-NEXT: fsw fs4, 96(a1) +; ILP32F-NEXT: fsw fs3, 92(a1) +; ILP32F-NEXT: fsw fs2, 88(a1) +; ILP32F-NEXT: fsw fs1, 84(a1) +; ILP32F-NEXT: fsw fs0, 80(a1) +; ILP32F-NEXT: fsw ft11, 76(a1) +; ILP32F-NEXT: fsw ft10, 72(a1) +; ILP32F-NEXT: fsw ft9, 68(a1) +; ILP32F-NEXT: fsw ft8, 64(a1) +; ILP32F-NEXT: fsw fa7, 60(a1) +; ILP32F-NEXT: fsw fa6, 56(a1) +; ILP32F-NEXT: fsw fa5, 52(a1) +; ILP32F-NEXT: fsw fa4, 48(a1) +; ILP32F-NEXT: fsw fa3, 44(a1) +; ILP32F-NEXT: fsw fa2, 40(a1) +; ILP32F-NEXT: fsw fa1, 36(a1) +; ILP32F-NEXT: fsw fa0, 32(a1) +; ILP32F-NEXT: fsw ft7, 28(a1) +; ILP32F-NEXT: fsw ft6, 24(a1) +; ILP32F-NEXT: fsw ft5, 20(a1) +; ILP32F-NEXT: fsw ft4, 16(a1) +; ILP32F-NEXT: fsw ft3, %lo(var+12)(a0) +; ILP32F-NEXT: fsw ft2, %lo(var+8)(a0) +; ILP32F-NEXT: fsw ft1, %lo(var+4)(a0) +; ILP32F-NEXT: fsw ft0, %lo(var)(a0) +; ILP32F-NEXT: flw fs11, 0(sp) +; ILP32F-NEXT: flw fs10, 4(sp) +; ILP32F-NEXT: flw fs9, 8(sp) +; ILP32F-NEXT: flw fs8, 12(sp) +; ILP32F-NEXT: flw fs7, 16(sp) +; ILP32F-NEXT: flw fs6, 20(sp) +; ILP32F-NEXT: flw fs5, 24(sp) +; ILP32F-NEXT: flw fs4, 28(sp) +; ILP32F-NEXT: flw fs3, 32(sp) +; ILP32F-NEXT: flw fs2, 36(sp) +; ILP32F-NEXT: flw fs1, 40(sp) +; ILP32F-NEXT: flw fs0, 44(sp) +; ILP32F-NEXT: addi sp, sp, 48 +; ILP32F-NEXT: ret +; +; LP64F-LABEL: callee: +; LP64F: # %bb.0: +; LP64F-NEXT: addi sp, sp, -48 +; LP64F-NEXT: fsw fs0, 44(sp) +; LP64F-NEXT: fsw fs1, 40(sp) +; LP64F-NEXT: fsw fs2, 36(sp) +; LP64F-NEXT: fsw fs3, 32(sp) +; LP64F-NEXT: fsw fs4, 28(sp) +; LP64F-NEXT: fsw fs5, 24(sp) +; LP64F-NEXT: fsw fs6, 20(sp) +; LP64F-NEXT: fsw fs7, 16(sp) +; LP64F-NEXT: fsw fs8, 12(sp) +; LP64F-NEXT: fsw fs9, 8(sp) +; LP64F-NEXT: fsw fs10, 4(sp) +; LP64F-NEXT: fsw fs11, 0(sp) +; LP64F-NEXT: lui a0, %hi(var) +; LP64F-NEXT: flw ft0, %lo(var)(a0) +; LP64F-NEXT: flw ft1, %lo(var+4)(a0) +; LP64F-NEXT: flw ft2, %lo(var+8)(a0) +; LP64F-NEXT: flw ft3, %lo(var+12)(a0) +; LP64F-NEXT: addi a1, a0, %lo(var) +; LP64F-NEXT: flw ft4, 16(a1) +; LP64F-NEXT: flw ft5, 20(a1) +; LP64F-NEXT: flw ft6, 24(a1) +; LP64F-NEXT: flw ft7, 28(a1) +; LP64F-NEXT: flw fa0, 32(a1) +; LP64F-NEXT: flw fa1, 36(a1) +; LP64F-NEXT: flw fa2, 40(a1) +; LP64F-NEXT: flw fa3, 44(a1) +; LP64F-NEXT: flw fa4, 48(a1) +; LP64F-NEXT: flw fa5, 52(a1) +; LP64F-NEXT: flw fa6, 56(a1) +; LP64F-NEXT: flw fa7, 60(a1) +; LP64F-NEXT: flw ft8, 64(a1) +; LP64F-NEXT: flw ft9, 68(a1) +; LP64F-NEXT: flw ft10, 72(a1) +; LP64F-NEXT: flw ft11, 76(a1) +; LP64F-NEXT: flw fs0, 80(a1) +; LP64F-NEXT: flw fs1, 84(a1) +; LP64F-NEXT: flw fs2, 88(a1) +; LP64F-NEXT: flw fs3, 92(a1) +; LP64F-NEXT: flw fs4, 96(a1) +; LP64F-NEXT: flw fs5, 100(a1) +; LP64F-NEXT: flw fs6, 104(a1) +; LP64F-NEXT: flw fs7, 108(a1) +; LP64F-NEXT: flw fs8, 124(a1) +; LP64F-NEXT: flw fs9, 120(a1) +; LP64F-NEXT: flw fs10, 116(a1) +; LP64F-NEXT: flw fs11, 112(a1) +; LP64F-NEXT: fsw fs8, 124(a1) +; LP64F-NEXT: fsw fs9, 120(a1) +; LP64F-NEXT: fsw fs10, 116(a1) +; LP64F-NEXT: fsw fs11, 112(a1) +; LP64F-NEXT: fsw fs7, 108(a1) +; LP64F-NEXT: fsw fs6, 104(a1) +; LP64F-NEXT: fsw fs5, 100(a1) +; LP64F-NEXT: fsw fs4, 96(a1) +; LP64F-NEXT: fsw fs3, 92(a1) +; LP64F-NEXT: fsw fs2, 88(a1) +; LP64F-NEXT: fsw fs1, 84(a1) +; LP64F-NEXT: fsw fs0, 80(a1) +; LP64F-NEXT: fsw ft11, 76(a1) +; LP64F-NEXT: fsw ft10, 72(a1) +; LP64F-NEXT: fsw ft9, 68(a1) +; LP64F-NEXT: fsw ft8, 64(a1) +; LP64F-NEXT: fsw fa7, 60(a1) +; LP64F-NEXT: fsw fa6, 56(a1) +; LP64F-NEXT: fsw fa5, 52(a1) +; LP64F-NEXT: fsw fa4, 48(a1) +; LP64F-NEXT: fsw fa3, 44(a1) +; LP64F-NEXT: fsw fa2, 40(a1) +; LP64F-NEXT: fsw fa1, 36(a1) +; LP64F-NEXT: fsw fa0, 32(a1) +; LP64F-NEXT: fsw ft7, 28(a1) +; LP64F-NEXT: fsw ft6, 24(a1) +; LP64F-NEXT: fsw ft5, 20(a1) +; LP64F-NEXT: fsw ft4, 16(a1) +; LP64F-NEXT: fsw ft3, %lo(var+12)(a0) +; LP64F-NEXT: fsw ft2, %lo(var+8)(a0) +; LP64F-NEXT: fsw ft1, %lo(var+4)(a0) +; LP64F-NEXT: fsw ft0, %lo(var)(a0) +; LP64F-NEXT: flw fs11, 0(sp) +; LP64F-NEXT: flw fs10, 4(sp) +; LP64F-NEXT: flw fs9, 8(sp) +; LP64F-NEXT: flw fs8, 12(sp) +; LP64F-NEXT: flw fs7, 16(sp) +; LP64F-NEXT: flw fs6, 20(sp) +; LP64F-NEXT: flw fs5, 24(sp) +; LP64F-NEXT: flw fs4, 28(sp) +; LP64F-NEXT: flw fs3, 32(sp) +; LP64F-NEXT: flw fs2, 36(sp) +; LP64F-NEXT: flw fs1, 40(sp) +; LP64F-NEXT: flw fs0, 44(sp) +; LP64F-NEXT: addi sp, sp, 48 +; LP64F-NEXT: ret +; +; ILP32D-LABEL: callee: +; ILP32D: # %bb.0: +; ILP32D-NEXT: addi sp, sp, -96 +; ILP32D-NEXT: fsd fs0, 88(sp) +; ILP32D-NEXT: fsd fs1, 80(sp) +; ILP32D-NEXT: fsd fs2, 72(sp) +; ILP32D-NEXT: fsd fs3, 64(sp) +; ILP32D-NEXT: fsd fs4, 56(sp) +; ILP32D-NEXT: fsd fs5, 48(sp) +; ILP32D-NEXT: fsd fs6, 40(sp) +; ILP32D-NEXT: fsd fs7, 32(sp) +; ILP32D-NEXT: fsd fs8, 24(sp) +; ILP32D-NEXT: fsd fs9, 16(sp) +; ILP32D-NEXT: fsd fs10, 8(sp) +; ILP32D-NEXT: fsd fs11, 0(sp) +; ILP32D-NEXT: lui a0, %hi(var) +; ILP32D-NEXT: flw ft0, %lo(var)(a0) +; ILP32D-NEXT: flw ft1, %lo(var+4)(a0) +; ILP32D-NEXT: flw ft2, %lo(var+8)(a0) +; ILP32D-NEXT: flw ft3, %lo(var+12)(a0) +; ILP32D-NEXT: addi a1, a0, %lo(var) +; ILP32D-NEXT: flw ft4, 16(a1) +; ILP32D-NEXT: flw ft5, 20(a1) +; ILP32D-NEXT: flw ft6, 24(a1) +; ILP32D-NEXT: flw ft7, 28(a1) +; ILP32D-NEXT: flw fa0, 32(a1) +; ILP32D-NEXT: flw fa1, 36(a1) +; ILP32D-NEXT: flw fa2, 40(a1) +; ILP32D-NEXT: flw fa3, 44(a1) +; ILP32D-NEXT: flw fa4, 48(a1) +; ILP32D-NEXT: flw fa5, 52(a1) +; ILP32D-NEXT: flw fa6, 56(a1) +; ILP32D-NEXT: flw fa7, 60(a1) +; ILP32D-NEXT: flw ft8, 64(a1) +; ILP32D-NEXT: flw ft9, 68(a1) +; ILP32D-NEXT: flw ft10, 72(a1) +; ILP32D-NEXT: flw ft11, 76(a1) +; ILP32D-NEXT: flw fs0, 80(a1) +; ILP32D-NEXT: flw fs1, 84(a1) +; ILP32D-NEXT: flw fs2, 88(a1) +; ILP32D-NEXT: flw fs3, 92(a1) +; ILP32D-NEXT: flw fs4, 96(a1) +; ILP32D-NEXT: flw fs5, 100(a1) +; ILP32D-NEXT: flw fs6, 104(a1) +; ILP32D-NEXT: flw fs7, 108(a1) +; ILP32D-NEXT: flw fs8, 124(a1) +; ILP32D-NEXT: flw fs9, 120(a1) +; ILP32D-NEXT: flw fs10, 116(a1) +; ILP32D-NEXT: flw fs11, 112(a1) +; ILP32D-NEXT: fsw fs8, 124(a1) +; ILP32D-NEXT: fsw fs9, 120(a1) +; ILP32D-NEXT: fsw fs10, 116(a1) +; ILP32D-NEXT: fsw fs11, 112(a1) +; ILP32D-NEXT: fsw fs7, 108(a1) +; ILP32D-NEXT: fsw fs6, 104(a1) +; ILP32D-NEXT: fsw fs5, 100(a1) +; ILP32D-NEXT: fsw fs4, 96(a1) +; ILP32D-NEXT: fsw fs3, 92(a1) +; ILP32D-NEXT: fsw fs2, 88(a1) +; ILP32D-NEXT: fsw fs1, 84(a1) +; ILP32D-NEXT: fsw fs0, 80(a1) +; ILP32D-NEXT: fsw ft11, 76(a1) +; ILP32D-NEXT: fsw ft10, 72(a1) +; ILP32D-NEXT: fsw ft9, 68(a1) +; ILP32D-NEXT: fsw ft8, 64(a1) +; ILP32D-NEXT: fsw fa7, 60(a1) +; ILP32D-NEXT: fsw fa6, 56(a1) +; ILP32D-NEXT: fsw fa5, 52(a1) +; ILP32D-NEXT: fsw fa4, 48(a1) +; ILP32D-NEXT: fsw fa3, 44(a1) +; ILP32D-NEXT: fsw fa2, 40(a1) +; ILP32D-NEXT: fsw fa1, 36(a1) +; ILP32D-NEXT: fsw fa0, 32(a1) +; ILP32D-NEXT: fsw ft7, 28(a1) +; ILP32D-NEXT: fsw ft6, 24(a1) +; ILP32D-NEXT: fsw ft5, 20(a1) +; ILP32D-NEXT: fsw ft4, 16(a1) +; ILP32D-NEXT: fsw ft3, %lo(var+12)(a0) +; ILP32D-NEXT: fsw ft2, %lo(var+8)(a0) +; ILP32D-NEXT: fsw ft1, %lo(var+4)(a0) +; ILP32D-NEXT: fsw ft0, %lo(var)(a0) +; ILP32D-NEXT: fld fs11, 0(sp) +; ILP32D-NEXT: fld fs10, 8(sp) +; ILP32D-NEXT: fld fs9, 16(sp) +; ILP32D-NEXT: fld fs8, 24(sp) +; ILP32D-NEXT: fld fs7, 32(sp) +; ILP32D-NEXT: fld fs6, 40(sp) +; ILP32D-NEXT: fld fs5, 48(sp) +; ILP32D-NEXT: fld fs4, 56(sp) +; ILP32D-NEXT: fld fs3, 64(sp) +; ILP32D-NEXT: fld fs2, 72(sp) +; ILP32D-NEXT: fld fs1, 80(sp) +; ILP32D-NEXT: fld fs0, 88(sp) +; ILP32D-NEXT: addi sp, sp, 96 +; ILP32D-NEXT: ret +; +; LP64D-LABEL: callee: +; LP64D: # %bb.0: +; LP64D-NEXT: addi sp, sp, -96 +; LP64D-NEXT: fsd fs0, 88(sp) +; LP64D-NEXT: fsd fs1, 80(sp) +; LP64D-NEXT: fsd fs2, 72(sp) +; LP64D-NEXT: fsd fs3, 64(sp) +; LP64D-NEXT: fsd fs4, 56(sp) +; LP64D-NEXT: fsd fs5, 48(sp) +; LP64D-NEXT: fsd fs6, 40(sp) +; LP64D-NEXT: fsd fs7, 32(sp) +; LP64D-NEXT: fsd fs8, 24(sp) +; LP64D-NEXT: fsd fs9, 16(sp) +; LP64D-NEXT: fsd fs10, 8(sp) +; LP64D-NEXT: fsd fs11, 0(sp) +; LP64D-NEXT: lui a0, %hi(var) +; LP64D-NEXT: flw ft0, %lo(var)(a0) +; LP64D-NEXT: flw ft1, %lo(var+4)(a0) +; LP64D-NEXT: flw ft2, %lo(var+8)(a0) +; LP64D-NEXT: flw ft3, %lo(var+12)(a0) +; LP64D-NEXT: addi a1, a0, %lo(var) +; LP64D-NEXT: flw ft4, 16(a1) +; LP64D-NEXT: flw ft5, 20(a1) +; LP64D-NEXT: flw ft6, 24(a1) +; LP64D-NEXT: flw ft7, 28(a1) +; LP64D-NEXT: flw fa0, 32(a1) +; LP64D-NEXT: flw fa1, 36(a1) +; LP64D-NEXT: flw fa2, 40(a1) +; LP64D-NEXT: flw fa3, 44(a1) +; LP64D-NEXT: flw fa4, 48(a1) +; LP64D-NEXT: flw fa5, 52(a1) +; LP64D-NEXT: flw fa6, 56(a1) +; LP64D-NEXT: flw fa7, 60(a1) +; LP64D-NEXT: flw ft8, 64(a1) +; LP64D-NEXT: flw ft9, 68(a1) +; LP64D-NEXT: flw ft10, 72(a1) +; LP64D-NEXT: flw ft11, 76(a1) +; LP64D-NEXT: flw fs0, 80(a1) +; LP64D-NEXT: flw fs1, 84(a1) +; LP64D-NEXT: flw fs2, 88(a1) +; LP64D-NEXT: flw fs3, 92(a1) +; LP64D-NEXT: flw fs4, 96(a1) +; LP64D-NEXT: flw fs5, 100(a1) +; LP64D-NEXT: flw fs6, 104(a1) +; LP64D-NEXT: flw fs7, 108(a1) +; LP64D-NEXT: flw fs8, 124(a1) +; LP64D-NEXT: flw fs9, 120(a1) +; LP64D-NEXT: flw fs10, 116(a1) +; LP64D-NEXT: flw fs11, 112(a1) +; LP64D-NEXT: fsw fs8, 124(a1) +; LP64D-NEXT: fsw fs9, 120(a1) +; LP64D-NEXT: fsw fs10, 116(a1) +; LP64D-NEXT: fsw fs11, 112(a1) +; LP64D-NEXT: fsw fs7, 108(a1) +; LP64D-NEXT: fsw fs6, 104(a1) +; LP64D-NEXT: fsw fs5, 100(a1) +; LP64D-NEXT: fsw fs4, 96(a1) +; LP64D-NEXT: fsw fs3, 92(a1) +; LP64D-NEXT: fsw fs2, 88(a1) +; LP64D-NEXT: fsw fs1, 84(a1) +; LP64D-NEXT: fsw fs0, 80(a1) +; LP64D-NEXT: fsw ft11, 76(a1) +; LP64D-NEXT: fsw ft10, 72(a1) +; LP64D-NEXT: fsw ft9, 68(a1) +; LP64D-NEXT: fsw ft8, 64(a1) +; LP64D-NEXT: fsw fa7, 60(a1) +; LP64D-NEXT: fsw fa6, 56(a1) +; LP64D-NEXT: fsw fa5, 52(a1) +; LP64D-NEXT: fsw fa4, 48(a1) +; LP64D-NEXT: fsw fa3, 44(a1) +; LP64D-NEXT: fsw fa2, 40(a1) +; LP64D-NEXT: fsw fa1, 36(a1) +; LP64D-NEXT: fsw fa0, 32(a1) +; LP64D-NEXT: fsw ft7, 28(a1) +; LP64D-NEXT: fsw ft6, 24(a1) +; LP64D-NEXT: fsw ft5, 20(a1) +; LP64D-NEXT: fsw ft4, 16(a1) +; LP64D-NEXT: fsw ft3, %lo(var+12)(a0) +; LP64D-NEXT: fsw ft2, %lo(var+8)(a0) +; LP64D-NEXT: fsw ft1, %lo(var+4)(a0) +; LP64D-NEXT: fsw ft0, %lo(var)(a0) +; LP64D-NEXT: fld fs11, 0(sp) +; LP64D-NEXT: fld fs10, 8(sp) +; LP64D-NEXT: fld fs9, 16(sp) +; LP64D-NEXT: fld fs8, 24(sp) +; LP64D-NEXT: fld fs7, 32(sp) +; LP64D-NEXT: fld fs6, 40(sp) +; LP64D-NEXT: fld fs5, 48(sp) +; LP64D-NEXT: fld fs4, 56(sp) +; LP64D-NEXT: fld fs3, 64(sp) +; LP64D-NEXT: fld fs2, 72(sp) +; LP64D-NEXT: fld fs1, 80(sp) +; LP64D-NEXT: fld fs0, 88(sp) +; LP64D-NEXT: addi sp, sp, 96 +; LP64D-NEXT: ret %val = load [32 x float], [32 x float]* @var store volatile [32 x float] %val, [32 x float]* @var ret void @@ -140,71 +557,863 @@ ; fs0-fs11 are preserved across calls. define void @caller() nounwind { -; ILP32-LP64-LABEL: caller: -; ILP32-LP64-NOT: ft{{[1-9][0-9]*}} -; ILP32-LP64-NOT: fs{{[0-9]+}} -; ILP32-LP64-NOT: fa{{[0-9]+}} -; ILP32-LP64: call callee -; ILP32-LP64-NOT: ft{{[1-9][0-9]*}} -; ILP32-LP64-NOT: fs{{[0-9]+}} -; ILP32-LP64-NOT: fa{{[0-9]+}} -; ILP32-LP64: ret +; ILP32-LABEL: caller: +; ILP32: # %bb.0: +; ILP32-NEXT: addi sp, sp, -144 +; ILP32-NEXT: sw ra, 140(sp) +; ILP32-NEXT: sw s0, 136(sp) +; ILP32-NEXT: sw s1, 132(sp) +; ILP32-NEXT: lui s0, %hi(var) +; ILP32-NEXT: flw ft0, %lo(var)(s0) +; ILP32-NEXT: fsw ft0, 128(sp) +; ILP32-NEXT: flw ft0, %lo(var+4)(s0) +; ILP32-NEXT: fsw ft0, 124(sp) +; ILP32-NEXT: flw ft0, %lo(var+8)(s0) +; ILP32-NEXT: fsw ft0, 120(sp) +; ILP32-NEXT: flw ft0, %lo(var+12)(s0) +; ILP32-NEXT: fsw ft0, 116(sp) +; ILP32-NEXT: addi s1, s0, %lo(var) +; ILP32-NEXT: flw ft0, 16(s1) +; ILP32-NEXT: fsw ft0, 112(sp) +; ILP32-NEXT: flw ft0, 20(s1) +; ILP32-NEXT: fsw ft0, 108(sp) +; ILP32-NEXT: flw ft0, 24(s1) +; ILP32-NEXT: fsw ft0, 104(sp) +; ILP32-NEXT: flw ft0, 28(s1) +; ILP32-NEXT: fsw ft0, 100(sp) +; ILP32-NEXT: flw ft0, 32(s1) +; ILP32-NEXT: fsw ft0, 96(sp) +; ILP32-NEXT: flw ft0, 36(s1) +; ILP32-NEXT: fsw ft0, 92(sp) +; ILP32-NEXT: flw ft0, 40(s1) +; ILP32-NEXT: fsw ft0, 88(sp) +; ILP32-NEXT: flw ft0, 44(s1) +; ILP32-NEXT: fsw ft0, 84(sp) +; ILP32-NEXT: flw ft0, 48(s1) +; ILP32-NEXT: fsw ft0, 80(sp) +; ILP32-NEXT: flw ft0, 52(s1) +; ILP32-NEXT: fsw ft0, 76(sp) +; ILP32-NEXT: flw ft0, 56(s1) +; ILP32-NEXT: fsw ft0, 72(sp) +; ILP32-NEXT: flw ft0, 60(s1) +; ILP32-NEXT: fsw ft0, 68(sp) +; ILP32-NEXT: flw ft0, 64(s1) +; ILP32-NEXT: fsw ft0, 64(sp) +; ILP32-NEXT: flw ft0, 68(s1) +; ILP32-NEXT: fsw ft0, 60(sp) +; ILP32-NEXT: flw ft0, 72(s1) +; ILP32-NEXT: fsw ft0, 56(sp) +; ILP32-NEXT: flw ft0, 76(s1) +; ILP32-NEXT: fsw ft0, 52(sp) +; ILP32-NEXT: flw ft0, 80(s1) +; ILP32-NEXT: fsw ft0, 48(sp) +; ILP32-NEXT: flw ft0, 84(s1) +; ILP32-NEXT: fsw ft0, 44(sp) +; ILP32-NEXT: flw ft0, 88(s1) +; ILP32-NEXT: fsw ft0, 40(sp) +; ILP32-NEXT: flw ft0, 92(s1) +; ILP32-NEXT: fsw ft0, 36(sp) +; ILP32-NEXT: flw ft0, 96(s1) +; ILP32-NEXT: fsw ft0, 32(sp) +; ILP32-NEXT: flw ft0, 100(s1) +; ILP32-NEXT: fsw ft0, 28(sp) +; ILP32-NEXT: flw ft0, 104(s1) +; ILP32-NEXT: fsw ft0, 24(sp) +; ILP32-NEXT: flw ft0, 108(s1) +; ILP32-NEXT: fsw ft0, 20(sp) +; ILP32-NEXT: flw ft0, 112(s1) +; ILP32-NEXT: fsw ft0, 16(sp) +; ILP32-NEXT: flw ft0, 116(s1) +; ILP32-NEXT: fsw ft0, 12(sp) +; ILP32-NEXT: flw ft0, 120(s1) +; ILP32-NEXT: fsw ft0, 8(sp) +; ILP32-NEXT: flw ft0, 124(s1) +; ILP32-NEXT: fsw ft0, 4(sp) +; ILP32-NEXT: call callee +; ILP32-NEXT: flw ft0, 4(sp) +; ILP32-NEXT: fsw ft0, 124(s1) +; ILP32-NEXT: flw ft0, 8(sp) +; ILP32-NEXT: fsw ft0, 120(s1) +; ILP32-NEXT: flw ft0, 12(sp) +; ILP32-NEXT: fsw ft0, 116(s1) +; ILP32-NEXT: flw ft0, 16(sp) +; ILP32-NEXT: fsw ft0, 112(s1) +; ILP32-NEXT: flw ft0, 20(sp) +; ILP32-NEXT: fsw ft0, 108(s1) +; ILP32-NEXT: flw ft0, 24(sp) +; ILP32-NEXT: fsw ft0, 104(s1) +; ILP32-NEXT: flw ft0, 28(sp) +; ILP32-NEXT: fsw ft0, 100(s1) +; ILP32-NEXT: flw ft0, 32(sp) +; ILP32-NEXT: fsw ft0, 96(s1) +; ILP32-NEXT: flw ft0, 36(sp) +; ILP32-NEXT: fsw ft0, 92(s1) +; ILP32-NEXT: flw ft0, 40(sp) +; ILP32-NEXT: fsw ft0, 88(s1) +; ILP32-NEXT: flw ft0, 44(sp) +; ILP32-NEXT: fsw ft0, 84(s1) +; ILP32-NEXT: flw ft0, 48(sp) +; ILP32-NEXT: fsw ft0, 80(s1) +; ILP32-NEXT: flw ft0, 52(sp) +; ILP32-NEXT: fsw ft0, 76(s1) +; ILP32-NEXT: flw ft0, 56(sp) +; ILP32-NEXT: fsw ft0, 72(s1) +; ILP32-NEXT: flw ft0, 60(sp) +; ILP32-NEXT: fsw ft0, 68(s1) +; ILP32-NEXT: flw ft0, 64(sp) +; ILP32-NEXT: fsw ft0, 64(s1) +; ILP32-NEXT: flw ft0, 68(sp) +; ILP32-NEXT: fsw ft0, 60(s1) +; ILP32-NEXT: flw ft0, 72(sp) +; ILP32-NEXT: fsw ft0, 56(s1) +; ILP32-NEXT: flw ft0, 76(sp) +; ILP32-NEXT: fsw ft0, 52(s1) +; ILP32-NEXT: flw ft0, 80(sp) +; ILP32-NEXT: fsw ft0, 48(s1) +; ILP32-NEXT: flw ft0, 84(sp) +; ILP32-NEXT: fsw ft0, 44(s1) +; ILP32-NEXT: flw ft0, 88(sp) +; ILP32-NEXT: fsw ft0, 40(s1) +; ILP32-NEXT: flw ft0, 92(sp) +; ILP32-NEXT: fsw ft0, 36(s1) +; ILP32-NEXT: flw ft0, 96(sp) +; ILP32-NEXT: fsw ft0, 32(s1) +; ILP32-NEXT: flw ft0, 100(sp) +; ILP32-NEXT: fsw ft0, 28(s1) +; ILP32-NEXT: flw ft0, 104(sp) +; ILP32-NEXT: fsw ft0, 24(s1) +; ILP32-NEXT: flw ft0, 108(sp) +; ILP32-NEXT: fsw ft0, 20(s1) +; ILP32-NEXT: flw ft0, 112(sp) +; ILP32-NEXT: fsw ft0, 16(s1) +; ILP32-NEXT: flw ft0, 116(sp) +; ILP32-NEXT: fsw ft0, %lo(var+12)(s0) +; ILP32-NEXT: flw ft0, 120(sp) +; ILP32-NEXT: fsw ft0, %lo(var+8)(s0) +; ILP32-NEXT: flw ft0, 124(sp) +; ILP32-NEXT: fsw ft0, %lo(var+4)(s0) +; ILP32-NEXT: flw ft0, 128(sp) +; ILP32-NEXT: fsw ft0, %lo(var)(s0) +; ILP32-NEXT: lw s1, 132(sp) +; ILP32-NEXT: lw s0, 136(sp) +; ILP32-NEXT: lw ra, 140(sp) +; ILP32-NEXT: addi sp, sp, 144 +; ILP32-NEXT: ret +; +; LP64-LABEL: caller: +; LP64: # %bb.0: +; LP64-NEXT: addi sp, sp, -160 +; LP64-NEXT: sd ra, 152(sp) +; LP64-NEXT: sd s0, 144(sp) +; LP64-NEXT: sd s1, 136(sp) +; LP64-NEXT: lui s0, %hi(var) +; LP64-NEXT: flw ft0, %lo(var)(s0) +; LP64-NEXT: fsw ft0, 132(sp) +; LP64-NEXT: flw ft0, %lo(var+4)(s0) +; LP64-NEXT: fsw ft0, 128(sp) +; LP64-NEXT: flw ft0, %lo(var+8)(s0) +; LP64-NEXT: fsw ft0, 124(sp) +; LP64-NEXT: flw ft0, %lo(var+12)(s0) +; LP64-NEXT: fsw ft0, 120(sp) +; LP64-NEXT: addi s1, s0, %lo(var) +; LP64-NEXT: flw ft0, 16(s1) +; LP64-NEXT: fsw ft0, 116(sp) +; LP64-NEXT: flw ft0, 20(s1) +; LP64-NEXT: fsw ft0, 112(sp) +; LP64-NEXT: flw ft0, 24(s1) +; LP64-NEXT: fsw ft0, 108(sp) +; LP64-NEXT: flw ft0, 28(s1) +; LP64-NEXT: fsw ft0, 104(sp) +; LP64-NEXT: flw ft0, 32(s1) +; LP64-NEXT: fsw ft0, 100(sp) +; LP64-NEXT: flw ft0, 36(s1) +; LP64-NEXT: fsw ft0, 96(sp) +; LP64-NEXT: flw ft0, 40(s1) +; LP64-NEXT: fsw ft0, 92(sp) +; LP64-NEXT: flw ft0, 44(s1) +; LP64-NEXT: fsw ft0, 88(sp) +; LP64-NEXT: flw ft0, 48(s1) +; LP64-NEXT: fsw ft0, 84(sp) +; LP64-NEXT: flw ft0, 52(s1) +; LP64-NEXT: fsw ft0, 80(sp) +; LP64-NEXT: flw ft0, 56(s1) +; LP64-NEXT: fsw ft0, 76(sp) +; LP64-NEXT: flw ft0, 60(s1) +; LP64-NEXT: fsw ft0, 72(sp) +; LP64-NEXT: flw ft0, 64(s1) +; LP64-NEXT: fsw ft0, 68(sp) +; LP64-NEXT: flw ft0, 68(s1) +; LP64-NEXT: fsw ft0, 64(sp) +; LP64-NEXT: flw ft0, 72(s1) +; LP64-NEXT: fsw ft0, 60(sp) +; LP64-NEXT: flw ft0, 76(s1) +; LP64-NEXT: fsw ft0, 56(sp) +; LP64-NEXT: flw ft0, 80(s1) +; LP64-NEXT: fsw ft0, 52(sp) +; LP64-NEXT: flw ft0, 84(s1) +; LP64-NEXT: fsw ft0, 48(sp) +; LP64-NEXT: flw ft0, 88(s1) +; LP64-NEXT: fsw ft0, 44(sp) +; LP64-NEXT: flw ft0, 92(s1) +; LP64-NEXT: fsw ft0, 40(sp) +; LP64-NEXT: flw ft0, 96(s1) +; LP64-NEXT: fsw ft0, 36(sp) +; LP64-NEXT: flw ft0, 100(s1) +; LP64-NEXT: fsw ft0, 32(sp) +; LP64-NEXT: flw ft0, 104(s1) +; LP64-NEXT: fsw ft0, 28(sp) +; LP64-NEXT: flw ft0, 108(s1) +; LP64-NEXT: fsw ft0, 24(sp) +; LP64-NEXT: flw ft0, 112(s1) +; LP64-NEXT: fsw ft0, 20(sp) +; LP64-NEXT: flw ft0, 116(s1) +; LP64-NEXT: fsw ft0, 16(sp) +; LP64-NEXT: flw ft0, 120(s1) +; LP64-NEXT: fsw ft0, 12(sp) +; LP64-NEXT: flw ft0, 124(s1) +; LP64-NEXT: fsw ft0, 8(sp) +; LP64-NEXT: call callee +; LP64-NEXT: flw ft0, 8(sp) +; LP64-NEXT: fsw ft0, 124(s1) +; LP64-NEXT: flw ft0, 12(sp) +; LP64-NEXT: fsw ft0, 120(s1) +; LP64-NEXT: flw ft0, 16(sp) +; LP64-NEXT: fsw ft0, 116(s1) +; LP64-NEXT: flw ft0, 20(sp) +; LP64-NEXT: fsw ft0, 112(s1) +; LP64-NEXT: flw ft0, 24(sp) +; LP64-NEXT: fsw ft0, 108(s1) +; LP64-NEXT: flw ft0, 28(sp) +; LP64-NEXT: fsw ft0, 104(s1) +; LP64-NEXT: flw ft0, 32(sp) +; LP64-NEXT: fsw ft0, 100(s1) +; LP64-NEXT: flw ft0, 36(sp) +; LP64-NEXT: fsw ft0, 96(s1) +; LP64-NEXT: flw ft0, 40(sp) +; LP64-NEXT: fsw ft0, 92(s1) +; LP64-NEXT: flw ft0, 44(sp) +; LP64-NEXT: fsw ft0, 88(s1) +; LP64-NEXT: flw ft0, 48(sp) +; LP64-NEXT: fsw ft0, 84(s1) +; LP64-NEXT: flw ft0, 52(sp) +; LP64-NEXT: fsw ft0, 80(s1) +; LP64-NEXT: flw ft0, 56(sp) +; LP64-NEXT: fsw ft0, 76(s1) +; LP64-NEXT: flw ft0, 60(sp) +; LP64-NEXT: fsw ft0, 72(s1) +; LP64-NEXT: flw ft0, 64(sp) +; LP64-NEXT: fsw ft0, 68(s1) +; LP64-NEXT: flw ft0, 68(sp) +; LP64-NEXT: fsw ft0, 64(s1) +; LP64-NEXT: flw ft0, 72(sp) +; LP64-NEXT: fsw ft0, 60(s1) +; LP64-NEXT: flw ft0, 76(sp) +; LP64-NEXT: fsw ft0, 56(s1) +; LP64-NEXT: flw ft0, 80(sp) +; LP64-NEXT: fsw ft0, 52(s1) +; LP64-NEXT: flw ft0, 84(sp) +; LP64-NEXT: fsw ft0, 48(s1) +; LP64-NEXT: flw ft0, 88(sp) +; LP64-NEXT: fsw ft0, 44(s1) +; LP64-NEXT: flw ft0, 92(sp) +; LP64-NEXT: fsw ft0, 40(s1) +; LP64-NEXT: flw ft0, 96(sp) +; LP64-NEXT: fsw ft0, 36(s1) +; LP64-NEXT: flw ft0, 100(sp) +; LP64-NEXT: fsw ft0, 32(s1) +; LP64-NEXT: flw ft0, 104(sp) +; LP64-NEXT: fsw ft0, 28(s1) +; LP64-NEXT: flw ft0, 108(sp) +; LP64-NEXT: fsw ft0, 24(s1) +; LP64-NEXT: flw ft0, 112(sp) +; LP64-NEXT: fsw ft0, 20(s1) +; LP64-NEXT: flw ft0, 116(sp) +; LP64-NEXT: fsw ft0, 16(s1) +; LP64-NEXT: flw ft0, 120(sp) +; LP64-NEXT: fsw ft0, %lo(var+12)(s0) +; LP64-NEXT: flw ft0, 124(sp) +; LP64-NEXT: fsw ft0, %lo(var+8)(s0) +; LP64-NEXT: flw ft0, 128(sp) +; LP64-NEXT: fsw ft0, %lo(var+4)(s0) +; LP64-NEXT: flw ft0, 132(sp) +; LP64-NEXT: fsw ft0, %lo(var)(s0) +; LP64-NEXT: ld s1, 136(sp) +; LP64-NEXT: ld s0, 144(sp) +; LP64-NEXT: ld ra, 152(sp) +; LP64-NEXT: addi sp, sp, 160 +; LP64-NEXT: ret +; +; ILP32F-LABEL: caller: +; ILP32F: # %bb.0: +; ILP32F-NEXT: addi sp, sp, -144 +; ILP32F-NEXT: sw ra, 140(sp) +; ILP32F-NEXT: sw s0, 136(sp) +; ILP32F-NEXT: sw s1, 132(sp) +; ILP32F-NEXT: fsw fs0, 128(sp) +; ILP32F-NEXT: fsw fs1, 124(sp) +; ILP32F-NEXT: fsw fs2, 120(sp) +; ILP32F-NEXT: fsw fs3, 116(sp) +; ILP32F-NEXT: fsw fs4, 112(sp) +; ILP32F-NEXT: fsw fs5, 108(sp) +; ILP32F-NEXT: fsw fs6, 104(sp) +; ILP32F-NEXT: fsw fs7, 100(sp) +; ILP32F-NEXT: fsw fs8, 96(sp) +; ILP32F-NEXT: fsw fs9, 92(sp) +; ILP32F-NEXT: fsw fs10, 88(sp) +; ILP32F-NEXT: fsw fs11, 84(sp) +; ILP32F-NEXT: lui s0, %hi(var) +; ILP32F-NEXT: flw ft0, %lo(var)(s0) +; ILP32F-NEXT: fsw ft0, 80(sp) +; ILP32F-NEXT: flw ft0, %lo(var+4)(s0) +; ILP32F-NEXT: fsw ft0, 76(sp) +; ILP32F-NEXT: flw ft0, %lo(var+8)(s0) +; ILP32F-NEXT: fsw ft0, 72(sp) +; ILP32F-NEXT: flw ft0, %lo(var+12)(s0) +; ILP32F-NEXT: fsw ft0, 68(sp) +; ILP32F-NEXT: addi s1, s0, %lo(var) +; ILP32F-NEXT: flw ft0, 16(s1) +; ILP32F-NEXT: fsw ft0, 64(sp) +; ILP32F-NEXT: flw ft0, 20(s1) +; ILP32F-NEXT: fsw ft0, 60(sp) +; ILP32F-NEXT: flw ft0, 24(s1) +; ILP32F-NEXT: fsw ft0, 56(sp) +; ILP32F-NEXT: flw ft0, 28(s1) +; ILP32F-NEXT: fsw ft0, 52(sp) +; ILP32F-NEXT: flw ft0, 32(s1) +; ILP32F-NEXT: fsw ft0, 48(sp) +; ILP32F-NEXT: flw ft0, 36(s1) +; ILP32F-NEXT: fsw ft0, 44(sp) +; ILP32F-NEXT: flw ft0, 40(s1) +; ILP32F-NEXT: fsw ft0, 40(sp) +; ILP32F-NEXT: flw ft0, 44(s1) +; ILP32F-NEXT: fsw ft0, 36(sp) +; ILP32F-NEXT: flw ft0, 48(s1) +; ILP32F-NEXT: fsw ft0, 32(sp) +; ILP32F-NEXT: flw ft0, 52(s1) +; ILP32F-NEXT: fsw ft0, 28(sp) +; ILP32F-NEXT: flw ft0, 56(s1) +; ILP32F-NEXT: fsw ft0, 24(sp) +; ILP32F-NEXT: flw ft0, 60(s1) +; ILP32F-NEXT: fsw ft0, 20(sp) +; ILP32F-NEXT: flw ft0, 64(s1) +; ILP32F-NEXT: fsw ft0, 16(sp) +; ILP32F-NEXT: flw ft0, 68(s1) +; ILP32F-NEXT: fsw ft0, 12(sp) +; ILP32F-NEXT: flw ft0, 72(s1) +; ILP32F-NEXT: fsw ft0, 8(sp) +; ILP32F-NEXT: flw ft0, 76(s1) +; ILP32F-NEXT: fsw ft0, 4(sp) +; ILP32F-NEXT: flw fs8, 80(s1) +; ILP32F-NEXT: flw fs9, 84(s1) +; ILP32F-NEXT: flw fs10, 88(s1) +; ILP32F-NEXT: flw fs11, 92(s1) +; ILP32F-NEXT: flw fs0, 96(s1) +; ILP32F-NEXT: flw fs1, 100(s1) +; ILP32F-NEXT: flw fs2, 104(s1) +; ILP32F-NEXT: flw fs3, 108(s1) +; ILP32F-NEXT: flw fs4, 112(s1) +; ILP32F-NEXT: flw fs5, 116(s1) +; ILP32F-NEXT: flw fs6, 120(s1) +; ILP32F-NEXT: flw fs7, 124(s1) +; ILP32F-NEXT: call callee +; ILP32F-NEXT: fsw fs7, 124(s1) +; ILP32F-NEXT: fsw fs6, 120(s1) +; ILP32F-NEXT: fsw fs5, 116(s1) +; ILP32F-NEXT: fsw fs4, 112(s1) +; ILP32F-NEXT: fsw fs3, 108(s1) +; ILP32F-NEXT: fsw fs2, 104(s1) +; ILP32F-NEXT: fsw fs1, 100(s1) +; ILP32F-NEXT: fsw fs0, 96(s1) +; ILP32F-NEXT: fsw fs11, 92(s1) +; ILP32F-NEXT: fsw fs10, 88(s1) +; ILP32F-NEXT: fsw fs9, 84(s1) +; ILP32F-NEXT: fsw fs8, 80(s1) +; ILP32F-NEXT: flw ft0, 4(sp) +; ILP32F-NEXT: fsw ft0, 76(s1) +; ILP32F-NEXT: flw ft0, 8(sp) +; ILP32F-NEXT: fsw ft0, 72(s1) +; ILP32F-NEXT: flw ft0, 12(sp) +; ILP32F-NEXT: fsw ft0, 68(s1) +; ILP32F-NEXT: flw ft0, 16(sp) +; ILP32F-NEXT: fsw ft0, 64(s1) +; ILP32F-NEXT: flw ft0, 20(sp) +; ILP32F-NEXT: fsw ft0, 60(s1) +; ILP32F-NEXT: flw ft0, 24(sp) +; ILP32F-NEXT: fsw ft0, 56(s1) +; ILP32F-NEXT: flw ft0, 28(sp) +; ILP32F-NEXT: fsw ft0, 52(s1) +; ILP32F-NEXT: flw ft0, 32(sp) +; ILP32F-NEXT: fsw ft0, 48(s1) +; ILP32F-NEXT: flw ft0, 36(sp) +; ILP32F-NEXT: fsw ft0, 44(s1) +; ILP32F-NEXT: flw ft0, 40(sp) +; ILP32F-NEXT: fsw ft0, 40(s1) +; ILP32F-NEXT: flw ft0, 44(sp) +; ILP32F-NEXT: fsw ft0, 36(s1) +; ILP32F-NEXT: flw ft0, 48(sp) +; ILP32F-NEXT: fsw ft0, 32(s1) +; ILP32F-NEXT: flw ft0, 52(sp) +; ILP32F-NEXT: fsw ft0, 28(s1) +; ILP32F-NEXT: flw ft0, 56(sp) +; ILP32F-NEXT: fsw ft0, 24(s1) +; ILP32F-NEXT: flw ft0, 60(sp) +; ILP32F-NEXT: fsw ft0, 20(s1) +; ILP32F-NEXT: flw ft0, 64(sp) +; ILP32F-NEXT: fsw ft0, 16(s1) +; ILP32F-NEXT: flw ft0, 68(sp) +; ILP32F-NEXT: fsw ft0, %lo(var+12)(s0) +; ILP32F-NEXT: flw ft0, 72(sp) +; ILP32F-NEXT: fsw ft0, %lo(var+8)(s0) +; ILP32F-NEXT: flw ft0, 76(sp) +; ILP32F-NEXT: fsw ft0, %lo(var+4)(s0) +; ILP32F-NEXT: flw ft0, 80(sp) +; ILP32F-NEXT: fsw ft0, %lo(var)(s0) +; ILP32F-NEXT: flw fs11, 84(sp) +; ILP32F-NEXT: flw fs10, 88(sp) +; ILP32F-NEXT: flw fs9, 92(sp) +; ILP32F-NEXT: flw fs8, 96(sp) +; ILP32F-NEXT: flw fs7, 100(sp) +; ILP32F-NEXT: flw fs6, 104(sp) +; ILP32F-NEXT: flw fs5, 108(sp) +; ILP32F-NEXT: flw fs4, 112(sp) +; ILP32F-NEXT: flw fs3, 116(sp) +; ILP32F-NEXT: flw fs2, 120(sp) +; ILP32F-NEXT: flw fs1, 124(sp) +; ILP32F-NEXT: flw fs0, 128(sp) +; ILP32F-NEXT: lw s1, 132(sp) +; ILP32F-NEXT: lw s0, 136(sp) +; ILP32F-NEXT: lw ra, 140(sp) +; ILP32F-NEXT: addi sp, sp, 144 +; ILP32F-NEXT: ret +; +; LP64F-LABEL: caller: +; LP64F: # %bb.0: +; LP64F-NEXT: addi sp, sp, -160 +; LP64F-NEXT: sd ra, 152(sp) +; LP64F-NEXT: sd s0, 144(sp) +; LP64F-NEXT: sd s1, 136(sp) +; LP64F-NEXT: fsw fs0, 132(sp) +; LP64F-NEXT: fsw fs1, 128(sp) +; LP64F-NEXT: fsw fs2, 124(sp) +; LP64F-NEXT: fsw fs3, 120(sp) +; LP64F-NEXT: fsw fs4, 116(sp) +; LP64F-NEXT: fsw fs5, 112(sp) +; LP64F-NEXT: fsw fs6, 108(sp) +; LP64F-NEXT: fsw fs7, 104(sp) +; LP64F-NEXT: fsw fs8, 100(sp) +; LP64F-NEXT: fsw fs9, 96(sp) +; LP64F-NEXT: fsw fs10, 92(sp) +; LP64F-NEXT: fsw fs11, 88(sp) +; LP64F-NEXT: lui s0, %hi(var) +; LP64F-NEXT: flw ft0, %lo(var)(s0) +; LP64F-NEXT: fsw ft0, 84(sp) +; LP64F-NEXT: flw ft0, %lo(var+4)(s0) +; LP64F-NEXT: fsw ft0, 80(sp) +; LP64F-NEXT: flw ft0, %lo(var+8)(s0) +; LP64F-NEXT: fsw ft0, 76(sp) +; LP64F-NEXT: flw ft0, %lo(var+12)(s0) +; LP64F-NEXT: fsw ft0, 72(sp) +; LP64F-NEXT: addi s1, s0, %lo(var) +; LP64F-NEXT: flw ft0, 16(s1) +; LP64F-NEXT: fsw ft0, 68(sp) +; LP64F-NEXT: flw ft0, 20(s1) +; LP64F-NEXT: fsw ft0, 64(sp) +; LP64F-NEXT: flw ft0, 24(s1) +; LP64F-NEXT: fsw ft0, 60(sp) +; LP64F-NEXT: flw ft0, 28(s1) +; LP64F-NEXT: fsw ft0, 56(sp) +; LP64F-NEXT: flw ft0, 32(s1) +; LP64F-NEXT: fsw ft0, 52(sp) +; LP64F-NEXT: flw ft0, 36(s1) +; LP64F-NEXT: fsw ft0, 48(sp) +; LP64F-NEXT: flw ft0, 40(s1) +; LP64F-NEXT: fsw ft0, 44(sp) +; LP64F-NEXT: flw ft0, 44(s1) +; LP64F-NEXT: fsw ft0, 40(sp) +; LP64F-NEXT: flw ft0, 48(s1) +; LP64F-NEXT: fsw ft0, 36(sp) +; LP64F-NEXT: flw ft0, 52(s1) +; LP64F-NEXT: fsw ft0, 32(sp) +; LP64F-NEXT: flw ft0, 56(s1) +; LP64F-NEXT: fsw ft0, 28(sp) +; LP64F-NEXT: flw ft0, 60(s1) +; LP64F-NEXT: fsw ft0, 24(sp) +; LP64F-NEXT: flw ft0, 64(s1) +; LP64F-NEXT: fsw ft0, 20(sp) +; LP64F-NEXT: flw ft0, 68(s1) +; LP64F-NEXT: fsw ft0, 16(sp) +; LP64F-NEXT: flw ft0, 72(s1) +; LP64F-NEXT: fsw ft0, 12(sp) +; LP64F-NEXT: flw ft0, 76(s1) +; LP64F-NEXT: fsw ft0, 8(sp) +; LP64F-NEXT: flw fs8, 80(s1) +; LP64F-NEXT: flw fs9, 84(s1) +; LP64F-NEXT: flw fs10, 88(s1) +; LP64F-NEXT: flw fs11, 92(s1) +; LP64F-NEXT: flw fs0, 96(s1) +; LP64F-NEXT: flw fs1, 100(s1) +; LP64F-NEXT: flw fs2, 104(s1) +; LP64F-NEXT: flw fs3, 108(s1) +; LP64F-NEXT: flw fs4, 112(s1) +; LP64F-NEXT: flw fs5, 116(s1) +; LP64F-NEXT: flw fs6, 120(s1) +; LP64F-NEXT: flw fs7, 124(s1) +; LP64F-NEXT: call callee +; LP64F-NEXT: fsw fs7, 124(s1) +; LP64F-NEXT: fsw fs6, 120(s1) +; LP64F-NEXT: fsw fs5, 116(s1) +; LP64F-NEXT: fsw fs4, 112(s1) +; LP64F-NEXT: fsw fs3, 108(s1) +; LP64F-NEXT: fsw fs2, 104(s1) +; LP64F-NEXT: fsw fs1, 100(s1) +; LP64F-NEXT: fsw fs0, 96(s1) +; LP64F-NEXT: fsw fs11, 92(s1) +; LP64F-NEXT: fsw fs10, 88(s1) +; LP64F-NEXT: fsw fs9, 84(s1) +; LP64F-NEXT: fsw fs8, 80(s1) +; LP64F-NEXT: flw ft0, 8(sp) +; LP64F-NEXT: fsw ft0, 76(s1) +; LP64F-NEXT: flw ft0, 12(sp) +; LP64F-NEXT: fsw ft0, 72(s1) +; LP64F-NEXT: flw ft0, 16(sp) +; LP64F-NEXT: fsw ft0, 68(s1) +; LP64F-NEXT: flw ft0, 20(sp) +; LP64F-NEXT: fsw ft0, 64(s1) +; LP64F-NEXT: flw ft0, 24(sp) +; LP64F-NEXT: fsw ft0, 60(s1) +; LP64F-NEXT: flw ft0, 28(sp) +; LP64F-NEXT: fsw ft0, 56(s1) +; LP64F-NEXT: flw ft0, 32(sp) +; LP64F-NEXT: fsw ft0, 52(s1) +; LP64F-NEXT: flw ft0, 36(sp) +; LP64F-NEXT: fsw ft0, 48(s1) +; LP64F-NEXT: flw ft0, 40(sp) +; LP64F-NEXT: fsw ft0, 44(s1) +; LP64F-NEXT: flw ft0, 44(sp) +; LP64F-NEXT: fsw ft0, 40(s1) +; LP64F-NEXT: flw ft0, 48(sp) +; LP64F-NEXT: fsw ft0, 36(s1) +; LP64F-NEXT: flw ft0, 52(sp) +; LP64F-NEXT: fsw ft0, 32(s1) +; LP64F-NEXT: flw ft0, 56(sp) +; LP64F-NEXT: fsw ft0, 28(s1) +; LP64F-NEXT: flw ft0, 60(sp) +; LP64F-NEXT: fsw ft0, 24(s1) +; LP64F-NEXT: flw ft0, 64(sp) +; LP64F-NEXT: fsw ft0, 20(s1) +; LP64F-NEXT: flw ft0, 68(sp) +; LP64F-NEXT: fsw ft0, 16(s1) +; LP64F-NEXT: flw ft0, 72(sp) +; LP64F-NEXT: fsw ft0, %lo(var+12)(s0) +; LP64F-NEXT: flw ft0, 76(sp) +; LP64F-NEXT: fsw ft0, %lo(var+8)(s0) +; LP64F-NEXT: flw ft0, 80(sp) +; LP64F-NEXT: fsw ft0, %lo(var+4)(s0) +; LP64F-NEXT: flw ft0, 84(sp) +; LP64F-NEXT: fsw ft0, %lo(var)(s0) +; LP64F-NEXT: flw fs11, 88(sp) +; LP64F-NEXT: flw fs10, 92(sp) +; LP64F-NEXT: flw fs9, 96(sp) +; LP64F-NEXT: flw fs8, 100(sp) +; LP64F-NEXT: flw fs7, 104(sp) +; LP64F-NEXT: flw fs6, 108(sp) +; LP64F-NEXT: flw fs5, 112(sp) +; LP64F-NEXT: flw fs4, 116(sp) +; LP64F-NEXT: flw fs3, 120(sp) +; LP64F-NEXT: flw fs2, 124(sp) +; LP64F-NEXT: flw fs1, 128(sp) +; LP64F-NEXT: flw fs0, 132(sp) +; LP64F-NEXT: ld s1, 136(sp) +; LP64F-NEXT: ld s0, 144(sp) +; LP64F-NEXT: ld ra, 152(sp) +; LP64F-NEXT: addi sp, sp, 160 +; LP64F-NEXT: ret ; -; ILP32F-LP64F-LABEL: caller: -; ILP32F-LP64F: flw fs8, 80(s1) -; ILP32F-LP64F-NEXT: flw fs9, 84(s1) -; ILP32F-LP64F-NEXT: flw fs10, 88(s1) -; ILP32F-LP64F-NEXT: flw fs11, 92(s1) -; ILP32F-LP64F-NEXT: flw fs0, 96(s1) -; ILP32F-LP64F-NEXT: flw fs1, 100(s1) -; ILP32F-LP64F-NEXT: flw fs2, 104(s1) -; ILP32F-LP64F-NEXT: flw fs3, 108(s1) -; ILP32F-LP64F-NEXT: flw fs4, 112(s1) -; ILP32F-LP64F-NEXT: flw fs5, 116(s1) -; ILP32F-LP64F-NEXT: flw fs6, 120(s1) -; ILP32F-LP64F-NEXT: flw fs7, 124(s1) -; ILP32F-LP64F-NEXT: call callee -; ILP32F-LP64F-NEXT: fsw fs7, 124(s1) -; ILP32F-LP64F-NEXT: fsw fs6, 120(s1) -; ILP32F-LP64F-NEXT: fsw fs5, 116(s1) -; ILP32F-LP64F-NEXT: fsw fs4, 112(s1) -; ILP32F-LP64F-NEXT: fsw fs3, 108(s1) -; ILP32F-LP64F-NEXT: fsw fs2, 104(s1) -; ILP32F-LP64F-NEXT: fsw fs1, 100(s1) -; ILP32F-LP64F-NEXT: fsw fs0, 96(s1) -; ILP32F-LP64F-NEXT: fsw fs11, 92(s1) -; ILP32F-LP64F-NEXT: fsw fs10, 88(s1) -; ILP32F-LP64F-NEXT: fsw fs9, 84(s1) -; ILP32F-LP64F-NEXT: fsw fs8, 80(s1) -; ILP32F-LP64F-NEXT: lw ft0, {{[0-9]+}}(sp) +; ILP32D-LABEL: caller: +; ILP32D: # %bb.0: +; ILP32D-NEXT: addi sp, sp, -192 +; ILP32D-NEXT: sw ra, 188(sp) +; ILP32D-NEXT: sw s0, 184(sp) +; ILP32D-NEXT: sw s1, 180(sp) +; ILP32D-NEXT: fsd fs0, 168(sp) +; ILP32D-NEXT: fsd fs1, 160(sp) +; ILP32D-NEXT: fsd fs2, 152(sp) +; ILP32D-NEXT: fsd fs3, 144(sp) +; ILP32D-NEXT: fsd fs4, 136(sp) +; ILP32D-NEXT: fsd fs5, 128(sp) +; ILP32D-NEXT: fsd fs6, 120(sp) +; ILP32D-NEXT: fsd fs7, 112(sp) +; ILP32D-NEXT: fsd fs8, 104(sp) +; ILP32D-NEXT: fsd fs9, 96(sp) +; ILP32D-NEXT: fsd fs10, 88(sp) +; ILP32D-NEXT: fsd fs11, 80(sp) +; ILP32D-NEXT: lui s0, %hi(var) +; ILP32D-NEXT: flw ft0, %lo(var)(s0) +; ILP32D-NEXT: fsw ft0, 76(sp) +; ILP32D-NEXT: flw ft0, %lo(var+4)(s0) +; ILP32D-NEXT: fsw ft0, 72(sp) +; ILP32D-NEXT: flw ft0, %lo(var+8)(s0) +; ILP32D-NEXT: fsw ft0, 68(sp) +; ILP32D-NEXT: flw ft0, %lo(var+12)(s0) +; ILP32D-NEXT: fsw ft0, 64(sp) +; ILP32D-NEXT: addi s1, s0, %lo(var) +; ILP32D-NEXT: flw ft0, 16(s1) +; ILP32D-NEXT: fsw ft0, 60(sp) +; ILP32D-NEXT: flw ft0, 20(s1) +; ILP32D-NEXT: fsw ft0, 56(sp) +; ILP32D-NEXT: flw ft0, 24(s1) +; ILP32D-NEXT: fsw ft0, 52(sp) +; ILP32D-NEXT: flw ft0, 28(s1) +; ILP32D-NEXT: fsw ft0, 48(sp) +; ILP32D-NEXT: flw ft0, 32(s1) +; ILP32D-NEXT: fsw ft0, 44(sp) +; ILP32D-NEXT: flw ft0, 36(s1) +; ILP32D-NEXT: fsw ft0, 40(sp) +; ILP32D-NEXT: flw ft0, 40(s1) +; ILP32D-NEXT: fsw ft0, 36(sp) +; ILP32D-NEXT: flw ft0, 44(s1) +; ILP32D-NEXT: fsw ft0, 32(sp) +; ILP32D-NEXT: flw ft0, 48(s1) +; ILP32D-NEXT: fsw ft0, 28(sp) +; ILP32D-NEXT: flw ft0, 52(s1) +; ILP32D-NEXT: fsw ft0, 24(sp) +; ILP32D-NEXT: flw ft0, 56(s1) +; ILP32D-NEXT: fsw ft0, 20(sp) +; ILP32D-NEXT: flw ft0, 60(s1) +; ILP32D-NEXT: fsw ft0, 16(sp) +; ILP32D-NEXT: flw ft0, 64(s1) +; ILP32D-NEXT: fsw ft0, 12(sp) +; ILP32D-NEXT: flw ft0, 68(s1) +; ILP32D-NEXT: fsw ft0, 8(sp) +; ILP32D-NEXT: flw ft0, 72(s1) +; ILP32D-NEXT: fsw ft0, 4(sp) +; ILP32D-NEXT: flw ft0, 76(s1) +; ILP32D-NEXT: fsw ft0, 0(sp) +; ILP32D-NEXT: flw fs8, 80(s1) +; ILP32D-NEXT: flw fs9, 84(s1) +; ILP32D-NEXT: flw fs10, 88(s1) +; ILP32D-NEXT: flw fs11, 92(s1) +; ILP32D-NEXT: flw fs0, 96(s1) +; ILP32D-NEXT: flw fs1, 100(s1) +; ILP32D-NEXT: flw fs2, 104(s1) +; ILP32D-NEXT: flw fs3, 108(s1) +; ILP32D-NEXT: flw fs4, 112(s1) +; ILP32D-NEXT: flw fs5, 116(s1) +; ILP32D-NEXT: flw fs6, 120(s1) +; ILP32D-NEXT: flw fs7, 124(s1) +; ILP32D-NEXT: call callee +; ILP32D-NEXT: fsw fs7, 124(s1) +; ILP32D-NEXT: fsw fs6, 120(s1) +; ILP32D-NEXT: fsw fs5, 116(s1) +; ILP32D-NEXT: fsw fs4, 112(s1) +; ILP32D-NEXT: fsw fs3, 108(s1) +; ILP32D-NEXT: fsw fs2, 104(s1) +; ILP32D-NEXT: fsw fs1, 100(s1) +; ILP32D-NEXT: fsw fs0, 96(s1) +; ILP32D-NEXT: fsw fs11, 92(s1) +; ILP32D-NEXT: fsw fs10, 88(s1) +; ILP32D-NEXT: fsw fs9, 84(s1) +; ILP32D-NEXT: fsw fs8, 80(s1) +; ILP32D-NEXT: flw ft0, 0(sp) +; ILP32D-NEXT: fsw ft0, 76(s1) +; ILP32D-NEXT: flw ft0, 4(sp) +; ILP32D-NEXT: fsw ft0, 72(s1) +; ILP32D-NEXT: flw ft0, 8(sp) +; ILP32D-NEXT: fsw ft0, 68(s1) +; ILP32D-NEXT: flw ft0, 12(sp) +; ILP32D-NEXT: fsw ft0, 64(s1) +; ILP32D-NEXT: flw ft0, 16(sp) +; ILP32D-NEXT: fsw ft0, 60(s1) +; ILP32D-NEXT: flw ft0, 20(sp) +; ILP32D-NEXT: fsw ft0, 56(s1) +; ILP32D-NEXT: flw ft0, 24(sp) +; ILP32D-NEXT: fsw ft0, 52(s1) +; ILP32D-NEXT: flw ft0, 28(sp) +; ILP32D-NEXT: fsw ft0, 48(s1) +; ILP32D-NEXT: flw ft0, 32(sp) +; ILP32D-NEXT: fsw ft0, 44(s1) +; ILP32D-NEXT: flw ft0, 36(sp) +; ILP32D-NEXT: fsw ft0, 40(s1) +; ILP32D-NEXT: flw ft0, 40(sp) +; ILP32D-NEXT: fsw ft0, 36(s1) +; ILP32D-NEXT: flw ft0, 44(sp) +; ILP32D-NEXT: fsw ft0, 32(s1) +; ILP32D-NEXT: flw ft0, 48(sp) +; ILP32D-NEXT: fsw ft0, 28(s1) +; ILP32D-NEXT: flw ft0, 52(sp) +; ILP32D-NEXT: fsw ft0, 24(s1) +; ILP32D-NEXT: flw ft0, 56(sp) +; ILP32D-NEXT: fsw ft0, 20(s1) +; ILP32D-NEXT: flw ft0, 60(sp) +; ILP32D-NEXT: fsw ft0, 16(s1) +; ILP32D-NEXT: flw ft0, 64(sp) +; ILP32D-NEXT: fsw ft0, %lo(var+12)(s0) +; ILP32D-NEXT: flw ft0, 68(sp) +; ILP32D-NEXT: fsw ft0, %lo(var+8)(s0) +; ILP32D-NEXT: flw ft0, 72(sp) +; ILP32D-NEXT: fsw ft0, %lo(var+4)(s0) +; ILP32D-NEXT: flw ft0, 76(sp) +; ILP32D-NEXT: fsw ft0, %lo(var)(s0) +; ILP32D-NEXT: fld fs11, 80(sp) +; ILP32D-NEXT: fld fs10, 88(sp) +; ILP32D-NEXT: fld fs9, 96(sp) +; ILP32D-NEXT: fld fs8, 104(sp) +; ILP32D-NEXT: fld fs7, 112(sp) +; ILP32D-NEXT: fld fs6, 120(sp) +; ILP32D-NEXT: fld fs5, 128(sp) +; ILP32D-NEXT: fld fs4, 136(sp) +; ILP32D-NEXT: fld fs3, 144(sp) +; ILP32D-NEXT: fld fs2, 152(sp) +; ILP32D-NEXT: fld fs1, 160(sp) +; ILP32D-NEXT: fld fs0, 168(sp) +; ILP32D-NEXT: lw s1, 180(sp) +; ILP32D-NEXT: lw s0, 184(sp) +; ILP32D-NEXT: lw ra, 188(sp) +; ILP32D-NEXT: addi sp, sp, 192 +; ILP32D-NEXT: ret ; -; ILP32D-LP64D-LABEL: caller: -; ILP32D-LP64D: flw fs8, 80(s1) -; ILP32D-LP64D-NEXT: flw fs9, 84(s1) -; ILP32D-LP64D-NEXT: flw fs10, 88(s1) -; ILP32D-LP64D-NEXT: flw fs11, 92(s1) -; ILP32D-LP64D-NEXT: flw fs0, 96(s1) -; ILP32D-LP64D-NEXT: flw fs1, 100(s1) -; ILP32D-LP64D-NEXT: flw fs2, 104(s1) -; ILP32D-LP64D-NEXT: flw fs3, 108(s1) -; ILP32D-LP64D-NEXT: flw fs4, 112(s1) -; ILP32D-LP64D-NEXT: flw fs5, 116(s1) -; ILP32D-LP64D-NEXT: flw fs6, 120(s1) -; ILP32D-LP64D-NEXT: flw fs7, 124(s1) -; ILP32D-LP64D-NEXT: call callee -; ILP32D-LP64D-NEXT: fsw fs7, 124(s1) -; ILP32D-LP64D-NEXT: fsw fs6, 120(s1) -; ILP32D-LP64D-NEXT: fsw fs5, 116(s1) -; ILP32D-LP64D-NEXT: fsw fs4, 112(s1) -; ILP32D-LP64D-NEXT: fsw fs3, 108(s1) -; ILP32D-LP64D-NEXT: fsw fs2, 104(s1) -; ILP32D-LP64D-NEXT: fsw fs1, 100(s1) -; ILP32D-LP64D-NEXT: fsw fs0, 96(s1) -; ILP32D-LP64D-NEXT: fsw fs11, 92(s1) -; ILP32D-LP64D-NEXT: fsw fs10, 88(s1) -; ILP32D-LP64D-NEXT: fsw fs9, 84(s1) -; ILP32D-LP64D-NEXT: fsw fs8, 80(s1) -; ILP32D-LP64D-NEXT: flw ft0, {{[0-9]+}}(sp) +; LP64D-LABEL: caller: +; LP64D: # %bb.0: +; LP64D-NEXT: addi sp, sp, -208 +; LP64D-NEXT: sd ra, 200(sp) +; LP64D-NEXT: sd s0, 192(sp) +; LP64D-NEXT: sd s1, 184(sp) +; LP64D-NEXT: fsd fs0, 176(sp) +; LP64D-NEXT: fsd fs1, 168(sp) +; LP64D-NEXT: fsd fs2, 160(sp) +; LP64D-NEXT: fsd fs3, 152(sp) +; LP64D-NEXT: fsd fs4, 144(sp) +; LP64D-NEXT: fsd fs5, 136(sp) +; LP64D-NEXT: fsd fs6, 128(sp) +; LP64D-NEXT: fsd fs7, 120(sp) +; LP64D-NEXT: fsd fs8, 112(sp) +; LP64D-NEXT: fsd fs9, 104(sp) +; LP64D-NEXT: fsd fs10, 96(sp) +; LP64D-NEXT: fsd fs11, 88(sp) +; LP64D-NEXT: lui s0, %hi(var) +; LP64D-NEXT: flw ft0, %lo(var)(s0) +; LP64D-NEXT: fsw ft0, 84(sp) +; LP64D-NEXT: flw ft0, %lo(var+4)(s0) +; LP64D-NEXT: fsw ft0, 80(sp) +; LP64D-NEXT: flw ft0, %lo(var+8)(s0) +; LP64D-NEXT: fsw ft0, 76(sp) +; LP64D-NEXT: flw ft0, %lo(var+12)(s0) +; LP64D-NEXT: fsw ft0, 72(sp) +; LP64D-NEXT: addi s1, s0, %lo(var) +; LP64D-NEXT: flw ft0, 16(s1) +; LP64D-NEXT: fsw ft0, 68(sp) +; LP64D-NEXT: flw ft0, 20(s1) +; LP64D-NEXT: fsw ft0, 64(sp) +; LP64D-NEXT: flw ft0, 24(s1) +; LP64D-NEXT: fsw ft0, 60(sp) +; LP64D-NEXT: flw ft0, 28(s1) +; LP64D-NEXT: fsw ft0, 56(sp) +; LP64D-NEXT: flw ft0, 32(s1) +; LP64D-NEXT: fsw ft0, 52(sp) +; LP64D-NEXT: flw ft0, 36(s1) +; LP64D-NEXT: fsw ft0, 48(sp) +; LP64D-NEXT: flw ft0, 40(s1) +; LP64D-NEXT: fsw ft0, 44(sp) +; LP64D-NEXT: flw ft0, 44(s1) +; LP64D-NEXT: fsw ft0, 40(sp) +; LP64D-NEXT: flw ft0, 48(s1) +; LP64D-NEXT: fsw ft0, 36(sp) +; LP64D-NEXT: flw ft0, 52(s1) +; LP64D-NEXT: fsw ft0, 32(sp) +; LP64D-NEXT: flw ft0, 56(s1) +; LP64D-NEXT: fsw ft0, 28(sp) +; LP64D-NEXT: flw ft0, 60(s1) +; LP64D-NEXT: fsw ft0, 24(sp) +; LP64D-NEXT: flw ft0, 64(s1) +; LP64D-NEXT: fsw ft0, 20(sp) +; LP64D-NEXT: flw ft0, 68(s1) +; LP64D-NEXT: fsw ft0, 16(sp) +; LP64D-NEXT: flw ft0, 72(s1) +; LP64D-NEXT: fsw ft0, 12(sp) +; LP64D-NEXT: flw ft0, 76(s1) +; LP64D-NEXT: fsw ft0, 8(sp) +; LP64D-NEXT: flw fs8, 80(s1) +; LP64D-NEXT: flw fs9, 84(s1) +; LP64D-NEXT: flw fs10, 88(s1) +; LP64D-NEXT: flw fs11, 92(s1) +; LP64D-NEXT: flw fs0, 96(s1) +; LP64D-NEXT: flw fs1, 100(s1) +; LP64D-NEXT: flw fs2, 104(s1) +; LP64D-NEXT: flw fs3, 108(s1) +; LP64D-NEXT: flw fs4, 112(s1) +; LP64D-NEXT: flw fs5, 116(s1) +; LP64D-NEXT: flw fs6, 120(s1) +; LP64D-NEXT: flw fs7, 124(s1) +; LP64D-NEXT: call callee +; LP64D-NEXT: fsw fs7, 124(s1) +; LP64D-NEXT: fsw fs6, 120(s1) +; LP64D-NEXT: fsw fs5, 116(s1) +; LP64D-NEXT: fsw fs4, 112(s1) +; LP64D-NEXT: fsw fs3, 108(s1) +; LP64D-NEXT: fsw fs2, 104(s1) +; LP64D-NEXT: fsw fs1, 100(s1) +; LP64D-NEXT: fsw fs0, 96(s1) +; LP64D-NEXT: fsw fs11, 92(s1) +; LP64D-NEXT: fsw fs10, 88(s1) +; LP64D-NEXT: fsw fs9, 84(s1) +; LP64D-NEXT: fsw fs8, 80(s1) +; LP64D-NEXT: flw ft0, 8(sp) +; LP64D-NEXT: fsw ft0, 76(s1) +; LP64D-NEXT: flw ft0, 12(sp) +; LP64D-NEXT: fsw ft0, 72(s1) +; LP64D-NEXT: flw ft0, 16(sp) +; LP64D-NEXT: fsw ft0, 68(s1) +; LP64D-NEXT: flw ft0, 20(sp) +; LP64D-NEXT: fsw ft0, 64(s1) +; LP64D-NEXT: flw ft0, 24(sp) +; LP64D-NEXT: fsw ft0, 60(s1) +; LP64D-NEXT: flw ft0, 28(sp) +; LP64D-NEXT: fsw ft0, 56(s1) +; LP64D-NEXT: flw ft0, 32(sp) +; LP64D-NEXT: fsw ft0, 52(s1) +; LP64D-NEXT: flw ft0, 36(sp) +; LP64D-NEXT: fsw ft0, 48(s1) +; LP64D-NEXT: flw ft0, 40(sp) +; LP64D-NEXT: fsw ft0, 44(s1) +; LP64D-NEXT: flw ft0, 44(sp) +; LP64D-NEXT: fsw ft0, 40(s1) +; LP64D-NEXT: flw ft0, 48(sp) +; LP64D-NEXT: fsw ft0, 36(s1) +; LP64D-NEXT: flw ft0, 52(sp) +; LP64D-NEXT: fsw ft0, 32(s1) +; LP64D-NEXT: flw ft0, 56(sp) +; LP64D-NEXT: fsw ft0, 28(s1) +; LP64D-NEXT: flw ft0, 60(sp) +; LP64D-NEXT: fsw ft0, 24(s1) +; LP64D-NEXT: flw ft0, 64(sp) +; LP64D-NEXT: fsw ft0, 20(s1) +; LP64D-NEXT: flw ft0, 68(sp) +; LP64D-NEXT: fsw ft0, 16(s1) +; LP64D-NEXT: flw ft0, 72(sp) +; LP64D-NEXT: fsw ft0, %lo(var+12)(s0) +; LP64D-NEXT: flw ft0, 76(sp) +; LP64D-NEXT: fsw ft0, %lo(var+8)(s0) +; LP64D-NEXT: flw ft0, 80(sp) +; LP64D-NEXT: fsw ft0, %lo(var+4)(s0) +; LP64D-NEXT: flw ft0, 84(sp) +; LP64D-NEXT: fsw ft0, %lo(var)(s0) +; LP64D-NEXT: fld fs11, 88(sp) +; LP64D-NEXT: fld fs10, 96(sp) +; LP64D-NEXT: fld fs9, 104(sp) +; LP64D-NEXT: fld fs8, 112(sp) +; LP64D-NEXT: fld fs7, 120(sp) +; LP64D-NEXT: fld fs6, 128(sp) +; LP64D-NEXT: fld fs5, 136(sp) +; LP64D-NEXT: fld fs4, 144(sp) +; LP64D-NEXT: fld fs3, 152(sp) +; LP64D-NEXT: fld fs2, 160(sp) +; LP64D-NEXT: fld fs1, 168(sp) +; LP64D-NEXT: fld fs0, 176(sp) +; LP64D-NEXT: ld s1, 184(sp) +; LP64D-NEXT: ld s0, 192(sp) +; LP64D-NEXT: ld ra, 200(sp) +; LP64D-NEXT: addi sp, sp, 208 +; LP64D-NEXT: ret %val = load [32 x float], [32 x float]* @var call void @callee() store volatile [32 x float] %val, [32 x float]* @var diff --git a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll --- a/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll @@ -1,11 +1,12 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32-LP64 +; RUN: | FileCheck %s -check-prefix=ILP32 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32-LP64 +; RUN: | FileCheck %s -check-prefix=LP64 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32D-LP64D +; RUN: | FileCheck %s -check-prefix=ILP32D ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s -check-prefix=ILP32D-LP64D +; RUN: | FileCheck %s -check-prefix=LP64D @var = global [32 x double] zeroinitializer @@ -16,94 +17,337 @@ ; something appropriate. define void @callee() nounwind { -; ILP32-LP64-LABEL: callee: -; ILP32-LP64: # %bb.0: -; ILP32-LP64-NEXT: lui a0, %hi(var) -; ILP32-LP64-NEXT: fld ft0, %lo(var)(a0) -; ILP32-LP64-NEXT: addi a1, a0, %lo(var) -; ILP32-LP64-NEXT: fld ft1, 8(a1) -; ILP32-LP64-NEXT: fld ft2, 16(a1) -; ILP32-LP64-NEXT: fld ft3, 24(a1) -; ILP32-LP64-NEXT: fld ft4, 32(a1) -; ILP32-LP64-NEXT: fld ft5, 40(a1) -; ILP32-LP64-NEXT: fld ft6, 48(a1) -; ILP32-LP64-NEXT: fld ft7, 56(a1) -; ILP32-LP64-NEXT: fld fa0, 64(a1) -; ILP32-LP64-NEXT: fld fa1, 72(a1) -; ILP32-LP64-NEXT: fld fa2, 80(a1) -; ILP32-LP64-NEXT: fld fa3, 88(a1) -; ILP32-LP64-NEXT: fld fa4, 96(a1) -; ILP32-LP64-NEXT: fld fa5, 104(a1) -; ILP32-LP64-NEXT: fld fa6, 112(a1) -; ILP32-LP64-NEXT: fld fa7, 120(a1) -; ILP32-LP64-NEXT: fld ft8, 128(a1) -; ILP32-LP64-NEXT: fld ft9, 136(a1) -; ILP32-LP64-NEXT: fld ft10, 144(a1) -; ILP32-LP64-NEXT: fld ft11, 152(a1) -; ILP32-LP64-NEXT: fld fs0, 160(a1) -; ILP32-LP64-NEXT: fld fs1, 168(a1) -; ILP32-LP64-NEXT: fld fs2, 176(a1) -; ILP32-LP64-NEXT: fld fs3, 184(a1) -; ILP32-LP64-NEXT: fld fs4, 192(a1) -; ILP32-LP64-NEXT: fld fs5, 200(a1) -; ILP32-LP64-NEXT: fld fs6, 208(a1) -; ILP32-LP64-NEXT: fld fs7, 216(a1) -; ILP32-LP64-NEXT: fld fs8, 248(a1) -; ILP32-LP64-NEXT: fld fs9, 240(a1) -; ILP32-LP64-NEXT: fld fs10, 232(a1) -; ILP32-LP64-NEXT: fld fs11, 224(a1) -; ILP32-LP64-NEXT: fsd fs8, 248(a1) -; ILP32-LP64-NEXT: fsd fs9, 240(a1) -; ILP32-LP64-NEXT: fsd fs10, 232(a1) -; ILP32-LP64-NEXT: fsd fs11, 224(a1) -; ILP32-LP64-NEXT: fsd fs7, 216(a1) -; ILP32-LP64-NEXT: fsd fs6, 208(a1) -; ILP32-LP64-NEXT: fsd fs5, 200(a1) -; ILP32-LP64-NEXT: fsd fs4, 192(a1) -; ILP32-LP64-NEXT: fsd fs3, 184(a1) -; ILP32-LP64-NEXT: fsd fs2, 176(a1) -; ILP32-LP64-NEXT: fsd fs1, 168(a1) -; ILP32-LP64-NEXT: fsd fs0, 160(a1) -; ILP32-LP64-NEXT: fsd ft11, 152(a1) -; ILP32-LP64-NEXT: fsd ft10, 144(a1) -; ILP32-LP64-NEXT: fsd ft9, 136(a1) -; ILP32-LP64-NEXT: fsd ft8, 128(a1) -; ILP32-LP64-NEXT: fsd fa7, 120(a1) -; ILP32-LP64-NEXT: fsd fa6, 112(a1) -; ILP32-LP64-NEXT: fsd fa5, 104(a1) -; ILP32-LP64-NEXT: fsd fa4, 96(a1) -; ILP32-LP64-NEXT: fsd fa3, 88(a1) -; ILP32-LP64-NEXT: fsd fa2, 80(a1) -; ILP32-LP64-NEXT: fsd fa1, 72(a1) -; ILP32-LP64-NEXT: fsd fa0, 64(a1) -; ILP32-LP64-NEXT: fsd ft7, 56(a1) -; ILP32-LP64-NEXT: fsd ft6, 48(a1) -; ILP32-LP64-NEXT: fsd ft5, 40(a1) -; ILP32-LP64-NEXT: fsd ft4, 32(a1) -; ILP32-LP64-NEXT: fsd ft3, 24(a1) -; ILP32-LP64-NEXT: fsd ft2, 16(a1) -; ILP32-LP64-NEXT: fsd ft1, 8(a1) -; ILP32-LP64-NEXT: fsd ft0, %lo(var)(a0) -; ILP32-LP64-NEXT: ret +; ILP32-LABEL: callee: +; ILP32: # %bb.0: +; ILP32-NEXT: lui a0, %hi(var) +; ILP32-NEXT: fld ft0, %lo(var)(a0) +; ILP32-NEXT: fld ft1, %lo(var+8)(a0) +; ILP32-NEXT: addi a1, a0, %lo(var) +; ILP32-NEXT: fld ft2, 16(a1) +; ILP32-NEXT: fld ft3, 24(a1) +; ILP32-NEXT: fld ft4, 32(a1) +; ILP32-NEXT: fld ft5, 40(a1) +; ILP32-NEXT: fld ft6, 48(a1) +; ILP32-NEXT: fld ft7, 56(a1) +; ILP32-NEXT: fld fa0, 64(a1) +; ILP32-NEXT: fld fa1, 72(a1) +; ILP32-NEXT: fld fa2, 80(a1) +; ILP32-NEXT: fld fa3, 88(a1) +; ILP32-NEXT: fld fa4, 96(a1) +; ILP32-NEXT: fld fa5, 104(a1) +; ILP32-NEXT: fld fa6, 112(a1) +; ILP32-NEXT: fld fa7, 120(a1) +; ILP32-NEXT: fld ft8, 128(a1) +; ILP32-NEXT: fld ft9, 136(a1) +; ILP32-NEXT: fld ft10, 144(a1) +; ILP32-NEXT: fld ft11, 152(a1) +; ILP32-NEXT: fld fs0, 160(a1) +; ILP32-NEXT: fld fs1, 168(a1) +; ILP32-NEXT: fld fs2, 176(a1) +; ILP32-NEXT: fld fs3, 184(a1) +; ILP32-NEXT: fld fs4, 192(a1) +; ILP32-NEXT: fld fs5, 200(a1) +; ILP32-NEXT: fld fs6, 208(a1) +; ILP32-NEXT: fld fs7, 216(a1) +; ILP32-NEXT: fld fs8, 248(a1) +; ILP32-NEXT: fld fs9, 240(a1) +; ILP32-NEXT: fld fs10, 232(a1) +; ILP32-NEXT: fld fs11, 224(a1) +; ILP32-NEXT: fsd fs8, 248(a1) +; ILP32-NEXT: fsd fs9, 240(a1) +; ILP32-NEXT: fsd fs10, 232(a1) +; ILP32-NEXT: fsd fs11, 224(a1) +; ILP32-NEXT: fsd fs7, 216(a1) +; ILP32-NEXT: fsd fs6, 208(a1) +; ILP32-NEXT: fsd fs5, 200(a1) +; ILP32-NEXT: fsd fs4, 192(a1) +; ILP32-NEXT: fsd fs3, 184(a1) +; ILP32-NEXT: fsd fs2, 176(a1) +; ILP32-NEXT: fsd fs1, 168(a1) +; ILP32-NEXT: fsd fs0, 160(a1) +; ILP32-NEXT: fsd ft11, 152(a1) +; ILP32-NEXT: fsd ft10, 144(a1) +; ILP32-NEXT: fsd ft9, 136(a1) +; ILP32-NEXT: fsd ft8, 128(a1) +; ILP32-NEXT: fsd fa7, 120(a1) +; ILP32-NEXT: fsd fa6, 112(a1) +; ILP32-NEXT: fsd fa5, 104(a1) +; ILP32-NEXT: fsd fa4, 96(a1) +; ILP32-NEXT: fsd fa3, 88(a1) +; ILP32-NEXT: fsd fa2, 80(a1) +; ILP32-NEXT: fsd fa1, 72(a1) +; ILP32-NEXT: fsd fa0, 64(a1) +; ILP32-NEXT: fsd ft7, 56(a1) +; ILP32-NEXT: fsd ft6, 48(a1) +; ILP32-NEXT: fsd ft5, 40(a1) +; ILP32-NEXT: fsd ft4, 32(a1) +; ILP32-NEXT: fsd ft3, 24(a1) +; ILP32-NEXT: fsd ft2, 16(a1) +; ILP32-NEXT: fsd ft1, %lo(var+8)(a0) +; ILP32-NEXT: fsd ft0, %lo(var)(a0) +; ILP32-NEXT: ret ; -; ILP32D-LP64D-LABEL: callee: -; ILP32D-LP64D: # %bb.0: -; ILP32D-LP64D-NEXT: addi sp, sp, -96 -; ILP32D-LP64D-NEXT: fsd fs0, 88(sp) -; ILP32D-LP64D-NEXT: fsd fs1, 80(sp) -; ILP32D-LP64D-NEXT: fsd fs2, 72(sp) -; ILP32D-LP64D-NEXT: fsd fs3, 64(sp) -; ILP32D-LP64D-NEXT: fsd fs4, 56(sp) -; ILP32D-LP64D-NEXT: fsd fs5, 48(sp) -; ILP32D-LP64D-NEXT: fsd fs6, 40(sp) -; ILP32D-LP64D-NEXT: fsd fs7, 32(sp) -; ILP32D-LP64D-NEXT: fsd fs8, 24(sp) -; ILP32D-LP64D-NEXT: fsd fs9, 16(sp) -; ILP32D-LP64D-NEXT: fsd fs10, 8(sp) -; ILP32D-LP64D-NEXT: fsd fs11, 0(sp) -; ILP32D-LP64D-NEXT: lui a0, %hi(var) -; ILP32D-LP64D-NEXT: fld ft0, %lo(var)(a0) -; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var) +; LP64-LABEL: callee: +; LP64: # %bb.0: +; LP64-NEXT: lui a0, %hi(var) +; LP64-NEXT: fld ft0, %lo(var)(a0) +; LP64-NEXT: fld ft1, %lo(var+8)(a0) +; LP64-NEXT: addi a1, a0, %lo(var) +; LP64-NEXT: fld ft2, 16(a1) +; LP64-NEXT: fld ft3, 24(a1) +; LP64-NEXT: fld ft4, 32(a1) +; LP64-NEXT: fld ft5, 40(a1) +; LP64-NEXT: fld ft6, 48(a1) +; LP64-NEXT: fld ft7, 56(a1) +; LP64-NEXT: fld fa0, 64(a1) +; LP64-NEXT: fld fa1, 72(a1) +; LP64-NEXT: fld fa2, 80(a1) +; LP64-NEXT: fld fa3, 88(a1) +; LP64-NEXT: fld fa4, 96(a1) +; LP64-NEXT: fld fa5, 104(a1) +; LP64-NEXT: fld fa6, 112(a1) +; LP64-NEXT: fld fa7, 120(a1) +; LP64-NEXT: fld ft8, 128(a1) +; LP64-NEXT: fld ft9, 136(a1) +; LP64-NEXT: fld ft10, 144(a1) +; LP64-NEXT: fld ft11, 152(a1) +; LP64-NEXT: fld fs0, 160(a1) +; LP64-NEXT: fld fs1, 168(a1) +; LP64-NEXT: fld fs2, 176(a1) +; LP64-NEXT: fld fs3, 184(a1) +; LP64-NEXT: fld fs4, 192(a1) +; LP64-NEXT: fld fs5, 200(a1) +; LP64-NEXT: fld fs6, 208(a1) +; LP64-NEXT: fld fs7, 216(a1) +; LP64-NEXT: fld fs8, 248(a1) +; LP64-NEXT: fld fs9, 240(a1) +; LP64-NEXT: fld fs10, 232(a1) +; LP64-NEXT: fld fs11, 224(a1) +; LP64-NEXT: fsd fs8, 248(a1) +; LP64-NEXT: fsd fs9, 240(a1) +; LP64-NEXT: fsd fs10, 232(a1) +; LP64-NEXT: fsd fs11, 224(a1) +; LP64-NEXT: fsd fs7, 216(a1) +; LP64-NEXT: fsd fs6, 208(a1) +; LP64-NEXT: fsd fs5, 200(a1) +; LP64-NEXT: fsd fs4, 192(a1) +; LP64-NEXT: fsd fs3, 184(a1) +; LP64-NEXT: fsd fs2, 176(a1) +; LP64-NEXT: fsd fs1, 168(a1) +; LP64-NEXT: fsd fs0, 160(a1) +; LP64-NEXT: fsd ft11, 152(a1) +; LP64-NEXT: fsd ft10, 144(a1) +; LP64-NEXT: fsd ft9, 136(a1) +; LP64-NEXT: fsd ft8, 128(a1) +; LP64-NEXT: fsd fa7, 120(a1) +; LP64-NEXT: fsd fa6, 112(a1) +; LP64-NEXT: fsd fa5, 104(a1) +; LP64-NEXT: fsd fa4, 96(a1) +; LP64-NEXT: fsd fa3, 88(a1) +; LP64-NEXT: fsd fa2, 80(a1) +; LP64-NEXT: fsd fa1, 72(a1) +; LP64-NEXT: fsd fa0, 64(a1) +; LP64-NEXT: fsd ft7, 56(a1) +; LP64-NEXT: fsd ft6, 48(a1) +; LP64-NEXT: fsd ft5, 40(a1) +; LP64-NEXT: fsd ft4, 32(a1) +; LP64-NEXT: fsd ft3, 24(a1) +; LP64-NEXT: fsd ft2, 16(a1) +; LP64-NEXT: fsd ft1, %lo(var+8)(a0) +; LP64-NEXT: fsd ft0, %lo(var)(a0) +; LP64-NEXT: ret +; +; ILP32D-LABEL: callee: +; ILP32D: # %bb.0: +; ILP32D-NEXT: addi sp, sp, -96 +; ILP32D-NEXT: fsd fs0, 88(sp) +; ILP32D-NEXT: fsd fs1, 80(sp) +; ILP32D-NEXT: fsd fs2, 72(sp) +; ILP32D-NEXT: fsd fs3, 64(sp) +; ILP32D-NEXT: fsd fs4, 56(sp) +; ILP32D-NEXT: fsd fs5, 48(sp) +; ILP32D-NEXT: fsd fs6, 40(sp) +; ILP32D-NEXT: fsd fs7, 32(sp) +; ILP32D-NEXT: fsd fs8, 24(sp) +; ILP32D-NEXT: fsd fs9, 16(sp) +; ILP32D-NEXT: fsd fs10, 8(sp) +; ILP32D-NEXT: fsd fs11, 0(sp) +; ILP32D-NEXT: lui a0, %hi(var) +; ILP32D-NEXT: fld ft0, %lo(var)(a0) +; ILP32D-NEXT: fld ft1, %lo(var+8)(a0) +; ILP32D-NEXT: addi a1, a0, %lo(var) +; ILP32D-NEXT: fld ft2, 16(a1) +; ILP32D-NEXT: fld ft3, 24(a1) +; ILP32D-NEXT: fld ft4, 32(a1) +; ILP32D-NEXT: fld ft5, 40(a1) +; ILP32D-NEXT: fld ft6, 48(a1) +; ILP32D-NEXT: fld ft7, 56(a1) +; ILP32D-NEXT: fld fa0, 64(a1) +; ILP32D-NEXT: fld fa1, 72(a1) +; ILP32D-NEXT: fld fa2, 80(a1) +; ILP32D-NEXT: fld fa3, 88(a1) +; ILP32D-NEXT: fld fa4, 96(a1) +; ILP32D-NEXT: fld fa5, 104(a1) +; ILP32D-NEXT: fld fa6, 112(a1) +; ILP32D-NEXT: fld fa7, 120(a1) +; ILP32D-NEXT: fld ft8, 128(a1) +; ILP32D-NEXT: fld ft9, 136(a1) +; ILP32D-NEXT: fld ft10, 144(a1) +; ILP32D-NEXT: fld ft11, 152(a1) +; ILP32D-NEXT: fld fs0, 160(a1) +; ILP32D-NEXT: fld fs1, 168(a1) +; ILP32D-NEXT: fld fs2, 176(a1) +; ILP32D-NEXT: fld fs3, 184(a1) +; ILP32D-NEXT: fld fs4, 192(a1) +; ILP32D-NEXT: fld fs5, 200(a1) +; ILP32D-NEXT: fld fs6, 208(a1) +; ILP32D-NEXT: fld fs7, 216(a1) +; ILP32D-NEXT: fld fs8, 248(a1) +; ILP32D-NEXT: fld fs9, 240(a1) +; ILP32D-NEXT: fld fs10, 232(a1) +; ILP32D-NEXT: fld fs11, 224(a1) +; ILP32D-NEXT: fsd fs8, 248(a1) +; ILP32D-NEXT: fsd fs9, 240(a1) +; ILP32D-NEXT: fsd fs10, 232(a1) +; ILP32D-NEXT: fsd fs11, 224(a1) +; ILP32D-NEXT: fsd fs7, 216(a1) +; ILP32D-NEXT: fsd fs6, 208(a1) +; ILP32D-NEXT: fsd fs5, 200(a1) +; ILP32D-NEXT: fsd fs4, 192(a1) +; ILP32D-NEXT: fsd fs3, 184(a1) +; ILP32D-NEXT: fsd fs2, 176(a1) +; ILP32D-NEXT: fsd fs1, 168(a1) +; ILP32D-NEXT: fsd fs0, 160(a1) +; ILP32D-NEXT: fsd ft11, 152(a1) +; ILP32D-NEXT: fsd ft10, 144(a1) +; ILP32D-NEXT: fsd ft9, 136(a1) +; ILP32D-NEXT: fsd ft8, 128(a1) +; ILP32D-NEXT: fsd fa7, 120(a1) +; ILP32D-NEXT: fsd fa6, 112(a1) +; ILP32D-NEXT: fsd fa5, 104(a1) +; ILP32D-NEXT: fsd fa4, 96(a1) +; ILP32D-NEXT: fsd fa3, 88(a1) +; ILP32D-NEXT: fsd fa2, 80(a1) +; ILP32D-NEXT: fsd fa1, 72(a1) +; ILP32D-NEXT: fsd fa0, 64(a1) +; ILP32D-NEXT: fsd ft7, 56(a1) +; ILP32D-NEXT: fsd ft6, 48(a1) +; ILP32D-NEXT: fsd ft5, 40(a1) +; ILP32D-NEXT: fsd ft4, 32(a1) +; ILP32D-NEXT: fsd ft3, 24(a1) +; ILP32D-NEXT: fsd ft2, 16(a1) +; ILP32D-NEXT: fsd ft1, %lo(var+8)(a0) +; ILP32D-NEXT: fsd ft0, %lo(var)(a0) +; ILP32D-NEXT: fld fs11, 0(sp) +; ILP32D-NEXT: fld fs10, 8(sp) +; ILP32D-NEXT: fld fs9, 16(sp) +; ILP32D-NEXT: fld fs8, 24(sp) +; ILP32D-NEXT: fld fs7, 32(sp) +; ILP32D-NEXT: fld fs6, 40(sp) +; ILP32D-NEXT: fld fs5, 48(sp) +; ILP32D-NEXT: fld fs4, 56(sp) +; ILP32D-NEXT: fld fs3, 64(sp) +; ILP32D-NEXT: fld fs2, 72(sp) +; ILP32D-NEXT: fld fs1, 80(sp) +; ILP32D-NEXT: fld fs0, 88(sp) +; ILP32D-NEXT: addi sp, sp, 96 +; ILP32D-NEXT: ret +; +; LP64D-LABEL: callee: +; LP64D: # %bb.0: +; LP64D-NEXT: addi sp, sp, -96 +; LP64D-NEXT: fsd fs0, 88(sp) +; LP64D-NEXT: fsd fs1, 80(sp) +; LP64D-NEXT: fsd fs2, 72(sp) +; LP64D-NEXT: fsd fs3, 64(sp) +; LP64D-NEXT: fsd fs4, 56(sp) +; LP64D-NEXT: fsd fs5, 48(sp) +; LP64D-NEXT: fsd fs6, 40(sp) +; LP64D-NEXT: fsd fs7, 32(sp) +; LP64D-NEXT: fsd fs8, 24(sp) +; LP64D-NEXT: fsd fs9, 16(sp) +; LP64D-NEXT: fsd fs10, 8(sp) +; LP64D-NEXT: fsd fs11, 0(sp) +; LP64D-NEXT: lui a0, %hi(var) +; LP64D-NEXT: fld ft0, %lo(var)(a0) +; LP64D-NEXT: fld ft1, %lo(var+8)(a0) +; LP64D-NEXT: addi a1, a0, %lo(var) +; LP64D-NEXT: fld ft2, 16(a1) +; LP64D-NEXT: fld ft3, 24(a1) +; LP64D-NEXT: fld ft4, 32(a1) +; LP64D-NEXT: fld ft5, 40(a1) +; LP64D-NEXT: fld ft6, 48(a1) +; LP64D-NEXT: fld ft7, 56(a1) +; LP64D-NEXT: fld fa0, 64(a1) +; LP64D-NEXT: fld fa1, 72(a1) +; LP64D-NEXT: fld fa2, 80(a1) +; LP64D-NEXT: fld fa3, 88(a1) +; LP64D-NEXT: fld fa4, 96(a1) +; LP64D-NEXT: fld fa5, 104(a1) +; LP64D-NEXT: fld fa6, 112(a1) +; LP64D-NEXT: fld fa7, 120(a1) +; LP64D-NEXT: fld ft8, 128(a1) +; LP64D-NEXT: fld ft9, 136(a1) +; LP64D-NEXT: fld ft10, 144(a1) +; LP64D-NEXT: fld ft11, 152(a1) +; LP64D-NEXT: fld fs0, 160(a1) +; LP64D-NEXT: fld fs1, 168(a1) +; LP64D-NEXT: fld fs2, 176(a1) +; LP64D-NEXT: fld fs3, 184(a1) +; LP64D-NEXT: fld fs4, 192(a1) +; LP64D-NEXT: fld fs5, 200(a1) +; LP64D-NEXT: fld fs6, 208(a1) +; LP64D-NEXT: fld fs7, 216(a1) +; LP64D-NEXT: fld fs8, 248(a1) +; LP64D-NEXT: fld fs9, 240(a1) +; LP64D-NEXT: fld fs10, 232(a1) +; LP64D-NEXT: fld fs11, 224(a1) +; LP64D-NEXT: fsd fs8, 248(a1) +; LP64D-NEXT: fsd fs9, 240(a1) +; LP64D-NEXT: fsd fs10, 232(a1) +; LP64D-NEXT: fsd fs11, 224(a1) +; LP64D-NEXT: fsd fs7, 216(a1) +; LP64D-NEXT: fsd fs6, 208(a1) +; LP64D-NEXT: fsd fs5, 200(a1) +; LP64D-NEXT: fsd fs4, 192(a1) +; LP64D-NEXT: fsd fs3, 184(a1) +; LP64D-NEXT: fsd fs2, 176(a1) +; LP64D-NEXT: fsd fs1, 168(a1) +; LP64D-NEXT: fsd fs0, 160(a1) +; LP64D-NEXT: fsd ft11, 152(a1) +; LP64D-NEXT: fsd ft10, 144(a1) +; LP64D-NEXT: fsd ft9, 136(a1) +; LP64D-NEXT: fsd ft8, 128(a1) +; LP64D-NEXT: fsd fa7, 120(a1) +; LP64D-NEXT: fsd fa6, 112(a1) +; LP64D-NEXT: fsd fa5, 104(a1) +; LP64D-NEXT: fsd fa4, 96(a1) +; LP64D-NEXT: fsd fa3, 88(a1) +; LP64D-NEXT: fsd fa2, 80(a1) +; LP64D-NEXT: fsd fa1, 72(a1) +; LP64D-NEXT: fsd fa0, 64(a1) +; LP64D-NEXT: fsd ft7, 56(a1) +; LP64D-NEXT: fsd ft6, 48(a1) +; LP64D-NEXT: fsd ft5, 40(a1) +; LP64D-NEXT: fsd ft4, 32(a1) +; LP64D-NEXT: fsd ft3, 24(a1) +; LP64D-NEXT: fsd ft2, 16(a1) +; LP64D-NEXT: fsd ft1, %lo(var+8)(a0) +; LP64D-NEXT: fsd ft0, %lo(var)(a0) +; LP64D-NEXT: fld fs11, 0(sp) +; LP64D-NEXT: fld fs10, 8(sp) +; LP64D-NEXT: fld fs9, 16(sp) +; LP64D-NEXT: fld fs8, 24(sp) +; LP64D-NEXT: fld fs7, 32(sp) +; LP64D-NEXT: fld fs6, 40(sp) +; LP64D-NEXT: fld fs5, 48(sp) +; LP64D-NEXT: fld fs4, 56(sp) +; LP64D-NEXT: fld fs3, 64(sp) +; LP64D-NEXT: fld fs2, 72(sp) +; LP64D-NEXT: fld fs1, 80(sp) +; LP64D-NEXT: fld fs0, 88(sp) +; LP64D-NEXT: addi sp, sp, 96 +; LP64D-NEXT: ret %val = load [32 x double], [32 x double]* @var store volatile [32 x double] %val, [32 x double]* @var ret void @@ -117,43 +361,577 @@ ; fs0-fs11 are preserved across calls. define void @caller() nounwind { -; ILP32-LP64-LABEL: caller: -; ILP32-LP64-NOT: ft{{[1-9][0-9]*}} -; ILP32-LP64-NOT: fs{{[0-9]+}} -; ILP32-LP64-NOT: fa{{[0-9]+}} -; ILP32-LP64: call callee -; ILP32-LP64-NOT: ft{{[1-9][0-9]*}} -; ILP32-LP64-NOT: fs{{[0-9]+}} -; ILP32-LP64-NOT: fa{{[0-9]+}} -; ILP32-LP64: ret +; ILP32-LABEL: caller: +; ILP32: # %bb.0: +; ILP32-NEXT: addi sp, sp, -272 +; ILP32-NEXT: sw ra, 268(sp) +; ILP32-NEXT: sw s0, 264(sp) +; ILP32-NEXT: sw s1, 260(sp) +; ILP32-NEXT: lui s0, %hi(var) +; ILP32-NEXT: fld ft0, %lo(var)(s0) +; ILP32-NEXT: fsd ft0, 248(sp) +; ILP32-NEXT: fld ft0, %lo(var+8)(s0) +; ILP32-NEXT: fsd ft0, 240(sp) +; ILP32-NEXT: addi s1, s0, %lo(var) +; ILP32-NEXT: fld ft0, 16(s1) +; ILP32-NEXT: fsd ft0, 232(sp) +; ILP32-NEXT: fld ft0, 24(s1) +; ILP32-NEXT: fsd ft0, 224(sp) +; ILP32-NEXT: fld ft0, 32(s1) +; ILP32-NEXT: fsd ft0, 216(sp) +; ILP32-NEXT: fld ft0, 40(s1) +; ILP32-NEXT: fsd ft0, 208(sp) +; ILP32-NEXT: fld ft0, 48(s1) +; ILP32-NEXT: fsd ft0, 200(sp) +; ILP32-NEXT: fld ft0, 56(s1) +; ILP32-NEXT: fsd ft0, 192(sp) +; ILP32-NEXT: fld ft0, 64(s1) +; ILP32-NEXT: fsd ft0, 184(sp) +; ILP32-NEXT: fld ft0, 72(s1) +; ILP32-NEXT: fsd ft0, 176(sp) +; ILP32-NEXT: fld ft0, 80(s1) +; ILP32-NEXT: fsd ft0, 168(sp) +; ILP32-NEXT: fld ft0, 88(s1) +; ILP32-NEXT: fsd ft0, 160(sp) +; ILP32-NEXT: fld ft0, 96(s1) +; ILP32-NEXT: fsd ft0, 152(sp) +; ILP32-NEXT: fld ft0, 104(s1) +; ILP32-NEXT: fsd ft0, 144(sp) +; ILP32-NEXT: fld ft0, 112(s1) +; ILP32-NEXT: fsd ft0, 136(sp) +; ILP32-NEXT: fld ft0, 120(s1) +; ILP32-NEXT: fsd ft0, 128(sp) +; ILP32-NEXT: fld ft0, 128(s1) +; ILP32-NEXT: fsd ft0, 120(sp) +; ILP32-NEXT: fld ft0, 136(s1) +; ILP32-NEXT: fsd ft0, 112(sp) +; ILP32-NEXT: fld ft0, 144(s1) +; ILP32-NEXT: fsd ft0, 104(sp) +; ILP32-NEXT: fld ft0, 152(s1) +; ILP32-NEXT: fsd ft0, 96(sp) +; ILP32-NEXT: fld ft0, 160(s1) +; ILP32-NEXT: fsd ft0, 88(sp) +; ILP32-NEXT: fld ft0, 168(s1) +; ILP32-NEXT: fsd ft0, 80(sp) +; ILP32-NEXT: fld ft0, 176(s1) +; ILP32-NEXT: fsd ft0, 72(sp) +; ILP32-NEXT: fld ft0, 184(s1) +; ILP32-NEXT: fsd ft0, 64(sp) +; ILP32-NEXT: fld ft0, 192(s1) +; ILP32-NEXT: fsd ft0, 56(sp) +; ILP32-NEXT: fld ft0, 200(s1) +; ILP32-NEXT: fsd ft0, 48(sp) +; ILP32-NEXT: fld ft0, 208(s1) +; ILP32-NEXT: fsd ft0, 40(sp) +; ILP32-NEXT: fld ft0, 216(s1) +; ILP32-NEXT: fsd ft0, 32(sp) +; ILP32-NEXT: fld ft0, 224(s1) +; ILP32-NEXT: fsd ft0, 24(sp) +; ILP32-NEXT: fld ft0, 232(s1) +; ILP32-NEXT: fsd ft0, 16(sp) +; ILP32-NEXT: fld ft0, 240(s1) +; ILP32-NEXT: fsd ft0, 8(sp) +; ILP32-NEXT: fld ft0, 248(s1) +; ILP32-NEXT: fsd ft0, 0(sp) +; ILP32-NEXT: call callee +; ILP32-NEXT: fld ft0, 0(sp) +; ILP32-NEXT: fsd ft0, 248(s1) +; ILP32-NEXT: fld ft0, 8(sp) +; ILP32-NEXT: fsd ft0, 240(s1) +; ILP32-NEXT: fld ft0, 16(sp) +; ILP32-NEXT: fsd ft0, 232(s1) +; ILP32-NEXT: fld ft0, 24(sp) +; ILP32-NEXT: fsd ft0, 224(s1) +; ILP32-NEXT: fld ft0, 32(sp) +; ILP32-NEXT: fsd ft0, 216(s1) +; ILP32-NEXT: fld ft0, 40(sp) +; ILP32-NEXT: fsd ft0, 208(s1) +; ILP32-NEXT: fld ft0, 48(sp) +; ILP32-NEXT: fsd ft0, 200(s1) +; ILP32-NEXT: fld ft0, 56(sp) +; ILP32-NEXT: fsd ft0, 192(s1) +; ILP32-NEXT: fld ft0, 64(sp) +; ILP32-NEXT: fsd ft0, 184(s1) +; ILP32-NEXT: fld ft0, 72(sp) +; ILP32-NEXT: fsd ft0, 176(s1) +; ILP32-NEXT: fld ft0, 80(sp) +; ILP32-NEXT: fsd ft0, 168(s1) +; ILP32-NEXT: fld ft0, 88(sp) +; ILP32-NEXT: fsd ft0, 160(s1) +; ILP32-NEXT: fld ft0, 96(sp) +; ILP32-NEXT: fsd ft0, 152(s1) +; ILP32-NEXT: fld ft0, 104(sp) +; ILP32-NEXT: fsd ft0, 144(s1) +; ILP32-NEXT: fld ft0, 112(sp) +; ILP32-NEXT: fsd ft0, 136(s1) +; ILP32-NEXT: fld ft0, 120(sp) +; ILP32-NEXT: fsd ft0, 128(s1) +; ILP32-NEXT: fld ft0, 128(sp) +; ILP32-NEXT: fsd ft0, 120(s1) +; ILP32-NEXT: fld ft0, 136(sp) +; ILP32-NEXT: fsd ft0, 112(s1) +; ILP32-NEXT: fld ft0, 144(sp) +; ILP32-NEXT: fsd ft0, 104(s1) +; ILP32-NEXT: fld ft0, 152(sp) +; ILP32-NEXT: fsd ft0, 96(s1) +; ILP32-NEXT: fld ft0, 160(sp) +; ILP32-NEXT: fsd ft0, 88(s1) +; ILP32-NEXT: fld ft0, 168(sp) +; ILP32-NEXT: fsd ft0, 80(s1) +; ILP32-NEXT: fld ft0, 176(sp) +; ILP32-NEXT: fsd ft0, 72(s1) +; ILP32-NEXT: fld ft0, 184(sp) +; ILP32-NEXT: fsd ft0, 64(s1) +; ILP32-NEXT: fld ft0, 192(sp) +; ILP32-NEXT: fsd ft0, 56(s1) +; ILP32-NEXT: fld ft0, 200(sp) +; ILP32-NEXT: fsd ft0, 48(s1) +; ILP32-NEXT: fld ft0, 208(sp) +; ILP32-NEXT: fsd ft0, 40(s1) +; ILP32-NEXT: fld ft0, 216(sp) +; ILP32-NEXT: fsd ft0, 32(s1) +; ILP32-NEXT: fld ft0, 224(sp) +; ILP32-NEXT: fsd ft0, 24(s1) +; ILP32-NEXT: fld ft0, 232(sp) +; ILP32-NEXT: fsd ft0, 16(s1) +; ILP32-NEXT: fld ft0, 240(sp) +; ILP32-NEXT: fsd ft0, %lo(var+8)(s0) +; ILP32-NEXT: fld ft0, 248(sp) +; ILP32-NEXT: fsd ft0, %lo(var)(s0) +; ILP32-NEXT: lw s1, 260(sp) +; ILP32-NEXT: lw s0, 264(sp) +; ILP32-NEXT: lw ra, 268(sp) +; ILP32-NEXT: addi sp, sp, 272 +; ILP32-NEXT: ret +; +; LP64-LABEL: caller: +; LP64: # %bb.0: +; LP64-NEXT: addi sp, sp, -288 +; LP64-NEXT: sd ra, 280(sp) +; LP64-NEXT: sd s0, 272(sp) +; LP64-NEXT: sd s1, 264(sp) +; LP64-NEXT: lui s0, %hi(var) +; LP64-NEXT: fld ft0, %lo(var)(s0) +; LP64-NEXT: fsd ft0, 256(sp) +; LP64-NEXT: fld ft0, %lo(var+8)(s0) +; LP64-NEXT: fsd ft0, 248(sp) +; LP64-NEXT: addi s1, s0, %lo(var) +; LP64-NEXT: fld ft0, 16(s1) +; LP64-NEXT: fsd ft0, 240(sp) +; LP64-NEXT: fld ft0, 24(s1) +; LP64-NEXT: fsd ft0, 232(sp) +; LP64-NEXT: fld ft0, 32(s1) +; LP64-NEXT: fsd ft0, 224(sp) +; LP64-NEXT: fld ft0, 40(s1) +; LP64-NEXT: fsd ft0, 216(sp) +; LP64-NEXT: fld ft0, 48(s1) +; LP64-NEXT: fsd ft0, 208(sp) +; LP64-NEXT: fld ft0, 56(s1) +; LP64-NEXT: fsd ft0, 200(sp) +; LP64-NEXT: fld ft0, 64(s1) +; LP64-NEXT: fsd ft0, 192(sp) +; LP64-NEXT: fld ft0, 72(s1) +; LP64-NEXT: fsd ft0, 184(sp) +; LP64-NEXT: fld ft0, 80(s1) +; LP64-NEXT: fsd ft0, 176(sp) +; LP64-NEXT: fld ft0, 88(s1) +; LP64-NEXT: fsd ft0, 168(sp) +; LP64-NEXT: fld ft0, 96(s1) +; LP64-NEXT: fsd ft0, 160(sp) +; LP64-NEXT: fld ft0, 104(s1) +; LP64-NEXT: fsd ft0, 152(sp) +; LP64-NEXT: fld ft0, 112(s1) +; LP64-NEXT: fsd ft0, 144(sp) +; LP64-NEXT: fld ft0, 120(s1) +; LP64-NEXT: fsd ft0, 136(sp) +; LP64-NEXT: fld ft0, 128(s1) +; LP64-NEXT: fsd ft0, 128(sp) +; LP64-NEXT: fld ft0, 136(s1) +; LP64-NEXT: fsd ft0, 120(sp) +; LP64-NEXT: fld ft0, 144(s1) +; LP64-NEXT: fsd ft0, 112(sp) +; LP64-NEXT: fld ft0, 152(s1) +; LP64-NEXT: fsd ft0, 104(sp) +; LP64-NEXT: fld ft0, 160(s1) +; LP64-NEXT: fsd ft0, 96(sp) +; LP64-NEXT: fld ft0, 168(s1) +; LP64-NEXT: fsd ft0, 88(sp) +; LP64-NEXT: fld ft0, 176(s1) +; LP64-NEXT: fsd ft0, 80(sp) +; LP64-NEXT: fld ft0, 184(s1) +; LP64-NEXT: fsd ft0, 72(sp) +; LP64-NEXT: fld ft0, 192(s1) +; LP64-NEXT: fsd ft0, 64(sp) +; LP64-NEXT: fld ft0, 200(s1) +; LP64-NEXT: fsd ft0, 56(sp) +; LP64-NEXT: fld ft0, 208(s1) +; LP64-NEXT: fsd ft0, 48(sp) +; LP64-NEXT: fld ft0, 216(s1) +; LP64-NEXT: fsd ft0, 40(sp) +; LP64-NEXT: fld ft0, 224(s1) +; LP64-NEXT: fsd ft0, 32(sp) +; LP64-NEXT: fld ft0, 232(s1) +; LP64-NEXT: fsd ft0, 24(sp) +; LP64-NEXT: fld ft0, 240(s1) +; LP64-NEXT: fsd ft0, 16(sp) +; LP64-NEXT: fld ft0, 248(s1) +; LP64-NEXT: fsd ft0, 8(sp) +; LP64-NEXT: call callee +; LP64-NEXT: fld ft0, 8(sp) +; LP64-NEXT: fsd ft0, 248(s1) +; LP64-NEXT: fld ft0, 16(sp) +; LP64-NEXT: fsd ft0, 240(s1) +; LP64-NEXT: fld ft0, 24(sp) +; LP64-NEXT: fsd ft0, 232(s1) +; LP64-NEXT: fld ft0, 32(sp) +; LP64-NEXT: fsd ft0, 224(s1) +; LP64-NEXT: fld ft0, 40(sp) +; LP64-NEXT: fsd ft0, 216(s1) +; LP64-NEXT: fld ft0, 48(sp) +; LP64-NEXT: fsd ft0, 208(s1) +; LP64-NEXT: fld ft0, 56(sp) +; LP64-NEXT: fsd ft0, 200(s1) +; LP64-NEXT: fld ft0, 64(sp) +; LP64-NEXT: fsd ft0, 192(s1) +; LP64-NEXT: fld ft0, 72(sp) +; LP64-NEXT: fsd ft0, 184(s1) +; LP64-NEXT: fld ft0, 80(sp) +; LP64-NEXT: fsd ft0, 176(s1) +; LP64-NEXT: fld ft0, 88(sp) +; LP64-NEXT: fsd ft0, 168(s1) +; LP64-NEXT: fld ft0, 96(sp) +; LP64-NEXT: fsd ft0, 160(s1) +; LP64-NEXT: fld ft0, 104(sp) +; LP64-NEXT: fsd ft0, 152(s1) +; LP64-NEXT: fld ft0, 112(sp) +; LP64-NEXT: fsd ft0, 144(s1) +; LP64-NEXT: fld ft0, 120(sp) +; LP64-NEXT: fsd ft0, 136(s1) +; LP64-NEXT: fld ft0, 128(sp) +; LP64-NEXT: fsd ft0, 128(s1) +; LP64-NEXT: fld ft0, 136(sp) +; LP64-NEXT: fsd ft0, 120(s1) +; LP64-NEXT: fld ft0, 144(sp) +; LP64-NEXT: fsd ft0, 112(s1) +; LP64-NEXT: fld ft0, 152(sp) +; LP64-NEXT: fsd ft0, 104(s1) +; LP64-NEXT: fld ft0, 160(sp) +; LP64-NEXT: fsd ft0, 96(s1) +; LP64-NEXT: fld ft0, 168(sp) +; LP64-NEXT: fsd ft0, 88(s1) +; LP64-NEXT: fld ft0, 176(sp) +; LP64-NEXT: fsd ft0, 80(s1) +; LP64-NEXT: fld ft0, 184(sp) +; LP64-NEXT: fsd ft0, 72(s1) +; LP64-NEXT: fld ft0, 192(sp) +; LP64-NEXT: fsd ft0, 64(s1) +; LP64-NEXT: fld ft0, 200(sp) +; LP64-NEXT: fsd ft0, 56(s1) +; LP64-NEXT: fld ft0, 208(sp) +; LP64-NEXT: fsd ft0, 48(s1) +; LP64-NEXT: fld ft0, 216(sp) +; LP64-NEXT: fsd ft0, 40(s1) +; LP64-NEXT: fld ft0, 224(sp) +; LP64-NEXT: fsd ft0, 32(s1) +; LP64-NEXT: fld ft0, 232(sp) +; LP64-NEXT: fsd ft0, 24(s1) +; LP64-NEXT: fld ft0, 240(sp) +; LP64-NEXT: fsd ft0, 16(s1) +; LP64-NEXT: fld ft0, 248(sp) +; LP64-NEXT: fsd ft0, %lo(var+8)(s0) +; LP64-NEXT: fld ft0, 256(sp) +; LP64-NEXT: fsd ft0, %lo(var)(s0) +; LP64-NEXT: ld s1, 264(sp) +; LP64-NEXT: ld s0, 272(sp) +; LP64-NEXT: ld ra, 280(sp) +; LP64-NEXT: addi sp, sp, 288 +; LP64-NEXT: ret +; +; ILP32D-LABEL: caller: +; ILP32D: # %bb.0: +; ILP32D-NEXT: addi sp, sp, -272 +; ILP32D-NEXT: sw ra, 268(sp) +; ILP32D-NEXT: sw s0, 264(sp) +; ILP32D-NEXT: sw s1, 260(sp) +; ILP32D-NEXT: fsd fs0, 248(sp) +; ILP32D-NEXT: fsd fs1, 240(sp) +; ILP32D-NEXT: fsd fs2, 232(sp) +; ILP32D-NEXT: fsd fs3, 224(sp) +; ILP32D-NEXT: fsd fs4, 216(sp) +; ILP32D-NEXT: fsd fs5, 208(sp) +; ILP32D-NEXT: fsd fs6, 200(sp) +; ILP32D-NEXT: fsd fs7, 192(sp) +; ILP32D-NEXT: fsd fs8, 184(sp) +; ILP32D-NEXT: fsd fs9, 176(sp) +; ILP32D-NEXT: fsd fs10, 168(sp) +; ILP32D-NEXT: fsd fs11, 160(sp) +; ILP32D-NEXT: lui s0, %hi(var) +; ILP32D-NEXT: fld ft0, %lo(var)(s0) +; ILP32D-NEXT: fsd ft0, 152(sp) +; ILP32D-NEXT: fld ft0, %lo(var+8)(s0) +; ILP32D-NEXT: fsd ft0, 144(sp) +; ILP32D-NEXT: addi s1, s0, %lo(var) +; ILP32D-NEXT: fld ft0, 16(s1) +; ILP32D-NEXT: fsd ft0, 136(sp) +; ILP32D-NEXT: fld ft0, 24(s1) +; ILP32D-NEXT: fsd ft0, 128(sp) +; ILP32D-NEXT: fld ft0, 32(s1) +; ILP32D-NEXT: fsd ft0, 120(sp) +; ILP32D-NEXT: fld ft0, 40(s1) +; ILP32D-NEXT: fsd ft0, 112(sp) +; ILP32D-NEXT: fld ft0, 48(s1) +; ILP32D-NEXT: fsd ft0, 104(sp) +; ILP32D-NEXT: fld ft0, 56(s1) +; ILP32D-NEXT: fsd ft0, 96(sp) +; ILP32D-NEXT: fld ft0, 64(s1) +; ILP32D-NEXT: fsd ft0, 88(sp) +; ILP32D-NEXT: fld ft0, 72(s1) +; ILP32D-NEXT: fsd ft0, 80(sp) +; ILP32D-NEXT: fld ft0, 80(s1) +; ILP32D-NEXT: fsd ft0, 72(sp) +; ILP32D-NEXT: fld ft0, 88(s1) +; ILP32D-NEXT: fsd ft0, 64(sp) +; ILP32D-NEXT: fld ft0, 96(s1) +; ILP32D-NEXT: fsd ft0, 56(sp) +; ILP32D-NEXT: fld ft0, 104(s1) +; ILP32D-NEXT: fsd ft0, 48(sp) +; ILP32D-NEXT: fld ft0, 112(s1) +; ILP32D-NEXT: fsd ft0, 40(sp) +; ILP32D-NEXT: fld ft0, 120(s1) +; ILP32D-NEXT: fsd ft0, 32(sp) +; ILP32D-NEXT: fld ft0, 128(s1) +; ILP32D-NEXT: fsd ft0, 24(sp) +; ILP32D-NEXT: fld ft0, 136(s1) +; ILP32D-NEXT: fsd ft0, 16(sp) +; ILP32D-NEXT: fld ft0, 144(s1) +; ILP32D-NEXT: fsd ft0, 8(sp) +; ILP32D-NEXT: fld ft0, 152(s1) +; ILP32D-NEXT: fsd ft0, 0(sp) +; ILP32D-NEXT: fld fs8, 160(s1) +; ILP32D-NEXT: fld fs9, 168(s1) +; ILP32D-NEXT: fld fs10, 176(s1) +; ILP32D-NEXT: fld fs11, 184(s1) +; ILP32D-NEXT: fld fs0, 192(s1) +; ILP32D-NEXT: fld fs1, 200(s1) +; ILP32D-NEXT: fld fs2, 208(s1) +; ILP32D-NEXT: fld fs3, 216(s1) +; ILP32D-NEXT: fld fs4, 224(s1) +; ILP32D-NEXT: fld fs5, 232(s1) +; ILP32D-NEXT: fld fs6, 240(s1) +; ILP32D-NEXT: fld fs7, 248(s1) +; ILP32D-NEXT: call callee +; ILP32D-NEXT: fsd fs7, 248(s1) +; ILP32D-NEXT: fsd fs6, 240(s1) +; ILP32D-NEXT: fsd fs5, 232(s1) +; ILP32D-NEXT: fsd fs4, 224(s1) +; ILP32D-NEXT: fsd fs3, 216(s1) +; ILP32D-NEXT: fsd fs2, 208(s1) +; ILP32D-NEXT: fsd fs1, 200(s1) +; ILP32D-NEXT: fsd fs0, 192(s1) +; ILP32D-NEXT: fsd fs11, 184(s1) +; ILP32D-NEXT: fsd fs10, 176(s1) +; ILP32D-NEXT: fsd fs9, 168(s1) +; ILP32D-NEXT: fsd fs8, 160(s1) +; ILP32D-NEXT: fld ft0, 0(sp) +; ILP32D-NEXT: fsd ft0, 152(s1) +; ILP32D-NEXT: fld ft0, 8(sp) +; ILP32D-NEXT: fsd ft0, 144(s1) +; ILP32D-NEXT: fld ft0, 16(sp) +; ILP32D-NEXT: fsd ft0, 136(s1) +; ILP32D-NEXT: fld ft0, 24(sp) +; ILP32D-NEXT: fsd ft0, 128(s1) +; ILP32D-NEXT: fld ft0, 32(sp) +; ILP32D-NEXT: fsd ft0, 120(s1) +; ILP32D-NEXT: fld ft0, 40(sp) +; ILP32D-NEXT: fsd ft0, 112(s1) +; ILP32D-NEXT: fld ft0, 48(sp) +; ILP32D-NEXT: fsd ft0, 104(s1) +; ILP32D-NEXT: fld ft0, 56(sp) +; ILP32D-NEXT: fsd ft0, 96(s1) +; ILP32D-NEXT: fld ft0, 64(sp) +; ILP32D-NEXT: fsd ft0, 88(s1) +; ILP32D-NEXT: fld ft0, 72(sp) +; ILP32D-NEXT: fsd ft0, 80(s1) +; ILP32D-NEXT: fld ft0, 80(sp) +; ILP32D-NEXT: fsd ft0, 72(s1) +; ILP32D-NEXT: fld ft0, 88(sp) +; ILP32D-NEXT: fsd ft0, 64(s1) +; ILP32D-NEXT: fld ft0, 96(sp) +; ILP32D-NEXT: fsd ft0, 56(s1) +; ILP32D-NEXT: fld ft0, 104(sp) +; ILP32D-NEXT: fsd ft0, 48(s1) +; ILP32D-NEXT: fld ft0, 112(sp) +; ILP32D-NEXT: fsd ft0, 40(s1) +; ILP32D-NEXT: fld ft0, 120(sp) +; ILP32D-NEXT: fsd ft0, 32(s1) +; ILP32D-NEXT: fld ft0, 128(sp) +; ILP32D-NEXT: fsd ft0, 24(s1) +; ILP32D-NEXT: fld ft0, 136(sp) +; ILP32D-NEXT: fsd ft0, 16(s1) +; ILP32D-NEXT: fld ft0, 144(sp) +; ILP32D-NEXT: fsd ft0, %lo(var+8)(s0) +; ILP32D-NEXT: fld ft0, 152(sp) +; ILP32D-NEXT: fsd ft0, %lo(var)(s0) +; ILP32D-NEXT: fld fs11, 160(sp) +; ILP32D-NEXT: fld fs10, 168(sp) +; ILP32D-NEXT: fld fs9, 176(sp) +; ILP32D-NEXT: fld fs8, 184(sp) +; ILP32D-NEXT: fld fs7, 192(sp) +; ILP32D-NEXT: fld fs6, 200(sp) +; ILP32D-NEXT: fld fs5, 208(sp) +; ILP32D-NEXT: fld fs4, 216(sp) +; ILP32D-NEXT: fld fs3, 224(sp) +; ILP32D-NEXT: fld fs2, 232(sp) +; ILP32D-NEXT: fld fs1, 240(sp) +; ILP32D-NEXT: fld fs0, 248(sp) +; ILP32D-NEXT: lw s1, 260(sp) +; ILP32D-NEXT: lw s0, 264(sp) +; ILP32D-NEXT: lw ra, 268(sp) +; ILP32D-NEXT: addi sp, sp, 272 +; ILP32D-NEXT: ret ; -; ILP32F-LP64D-LABEL: caller: -; ILP32D-LP64D: fld fs8, 160(s1) -; ILP32D-LP64D-NEXT: fld fs9, 168(s1) -; ILP32D-LP64D-NEXT: fld fs10, 176(s1) -; ILP32D-LP64D-NEXT: fld fs11, 184(s1) -; ILP32D-LP64D-NEXT: fld fs0, 192(s1) -; ILP32D-LP64D-NEXT: fld fs1, 200(s1) -; ILP32D-LP64D-NEXT: fld fs2, 208(s1) -; ILP32D-LP64D-NEXT: fld fs3, 216(s1) -; ILP32D-LP64D-NEXT: fld fs4, 224(s1) -; ILP32D-LP64D-NEXT: fld fs5, 232(s1) -; ILP32D-LP64D-NEXT: fld fs6, 240(s1) -; ILP32D-LP64D-NEXT: fld fs7, 248(s1) -; ILP32D-LP64D-NEXT: call callee -; ILP32D-LP64D-NEXT: fsd fs7, 248(s1) -; ILP32D-LP64D-NEXT: fsd fs6, 240(s1) -; ILP32D-LP64D-NEXT: fsd fs5, 232(s1) -; ILP32D-LP64D-NEXT: fsd fs4, 224(s1) -; ILP32D-LP64D-NEXT: fsd fs3, 216(s1) -; ILP32D-LP64D-NEXT: fsd fs2, 208(s1) -; ILP32D-LP64D-NEXT: fsd fs1, 200(s1) -; ILP32D-LP64D-NEXT: fsd fs0, 192(s1) -; ILP32D-LP64D-NEXT: fsd fs11, 184(s1) -; ILP32D-LP64D-NEXT: fsd fs10, 176(s1) -; ILP32D-LP64D-NEXT: fsd fs9, 168(s1) -; ILP32D-LP64D-NEXT: fsd fs8, 160(s1) -; ILP32D-LP64D-NEXT: fld ft0, {{[0-9]+}}(sp) +; LP64D-LABEL: caller: +; LP64D: # %bb.0: +; LP64D-NEXT: addi sp, sp, -288 +; LP64D-NEXT: sd ra, 280(sp) +; LP64D-NEXT: sd s0, 272(sp) +; LP64D-NEXT: sd s1, 264(sp) +; LP64D-NEXT: fsd fs0, 256(sp) +; LP64D-NEXT: fsd fs1, 248(sp) +; LP64D-NEXT: fsd fs2, 240(sp) +; LP64D-NEXT: fsd fs3, 232(sp) +; LP64D-NEXT: fsd fs4, 224(sp) +; LP64D-NEXT: fsd fs5, 216(sp) +; LP64D-NEXT: fsd fs6, 208(sp) +; LP64D-NEXT: fsd fs7, 200(sp) +; LP64D-NEXT: fsd fs8, 192(sp) +; LP64D-NEXT: fsd fs9, 184(sp) +; LP64D-NEXT: fsd fs10, 176(sp) +; LP64D-NEXT: fsd fs11, 168(sp) +; LP64D-NEXT: lui s0, %hi(var) +; LP64D-NEXT: fld ft0, %lo(var)(s0) +; LP64D-NEXT: fsd ft0, 160(sp) +; LP64D-NEXT: fld ft0, %lo(var+8)(s0) +; LP64D-NEXT: fsd ft0, 152(sp) +; LP64D-NEXT: addi s1, s0, %lo(var) +; LP64D-NEXT: fld ft0, 16(s1) +; LP64D-NEXT: fsd ft0, 144(sp) +; LP64D-NEXT: fld ft0, 24(s1) +; LP64D-NEXT: fsd ft0, 136(sp) +; LP64D-NEXT: fld ft0, 32(s1) +; LP64D-NEXT: fsd ft0, 128(sp) +; LP64D-NEXT: fld ft0, 40(s1) +; LP64D-NEXT: fsd ft0, 120(sp) +; LP64D-NEXT: fld ft0, 48(s1) +; LP64D-NEXT: fsd ft0, 112(sp) +; LP64D-NEXT: fld ft0, 56(s1) +; LP64D-NEXT: fsd ft0, 104(sp) +; LP64D-NEXT: fld ft0, 64(s1) +; LP64D-NEXT: fsd ft0, 96(sp) +; LP64D-NEXT: fld ft0, 72(s1) +; LP64D-NEXT: fsd ft0, 88(sp) +; LP64D-NEXT: fld ft0, 80(s1) +; LP64D-NEXT: fsd ft0, 80(sp) +; LP64D-NEXT: fld ft0, 88(s1) +; LP64D-NEXT: fsd ft0, 72(sp) +; LP64D-NEXT: fld ft0, 96(s1) +; LP64D-NEXT: fsd ft0, 64(sp) +; LP64D-NEXT: fld ft0, 104(s1) +; LP64D-NEXT: fsd ft0, 56(sp) +; LP64D-NEXT: fld ft0, 112(s1) +; LP64D-NEXT: fsd ft0, 48(sp) +; LP64D-NEXT: fld ft0, 120(s1) +; LP64D-NEXT: fsd ft0, 40(sp) +; LP64D-NEXT: fld ft0, 128(s1) +; LP64D-NEXT: fsd ft0, 32(sp) +; LP64D-NEXT: fld ft0, 136(s1) +; LP64D-NEXT: fsd ft0, 24(sp) +; LP64D-NEXT: fld ft0, 144(s1) +; LP64D-NEXT: fsd ft0, 16(sp) +; LP64D-NEXT: fld ft0, 152(s1) +; LP64D-NEXT: fsd ft0, 8(sp) +; LP64D-NEXT: fld fs8, 160(s1) +; LP64D-NEXT: fld fs9, 168(s1) +; LP64D-NEXT: fld fs10, 176(s1) +; LP64D-NEXT: fld fs11, 184(s1) +; LP64D-NEXT: fld fs0, 192(s1) +; LP64D-NEXT: fld fs1, 200(s1) +; LP64D-NEXT: fld fs2, 208(s1) +; LP64D-NEXT: fld fs3, 216(s1) +; LP64D-NEXT: fld fs4, 224(s1) +; LP64D-NEXT: fld fs5, 232(s1) +; LP64D-NEXT: fld fs6, 240(s1) +; LP64D-NEXT: fld fs7, 248(s1) +; LP64D-NEXT: call callee +; LP64D-NEXT: fsd fs7, 248(s1) +; LP64D-NEXT: fsd fs6, 240(s1) +; LP64D-NEXT: fsd fs5, 232(s1) +; LP64D-NEXT: fsd fs4, 224(s1) +; LP64D-NEXT: fsd fs3, 216(s1) +; LP64D-NEXT: fsd fs2, 208(s1) +; LP64D-NEXT: fsd fs1, 200(s1) +; LP64D-NEXT: fsd fs0, 192(s1) +; LP64D-NEXT: fsd fs11, 184(s1) +; LP64D-NEXT: fsd fs10, 176(s1) +; LP64D-NEXT: fsd fs9, 168(s1) +; LP64D-NEXT: fsd fs8, 160(s1) +; LP64D-NEXT: fld ft0, 8(sp) +; LP64D-NEXT: fsd ft0, 152(s1) +; LP64D-NEXT: fld ft0, 16(sp) +; LP64D-NEXT: fsd ft0, 144(s1) +; LP64D-NEXT: fld ft0, 24(sp) +; LP64D-NEXT: fsd ft0, 136(s1) +; LP64D-NEXT: fld ft0, 32(sp) +; LP64D-NEXT: fsd ft0, 128(s1) +; LP64D-NEXT: fld ft0, 40(sp) +; LP64D-NEXT: fsd ft0, 120(s1) +; LP64D-NEXT: fld ft0, 48(sp) +; LP64D-NEXT: fsd ft0, 112(s1) +; LP64D-NEXT: fld ft0, 56(sp) +; LP64D-NEXT: fsd ft0, 104(s1) +; LP64D-NEXT: fld ft0, 64(sp) +; LP64D-NEXT: fsd ft0, 96(s1) +; LP64D-NEXT: fld ft0, 72(sp) +; LP64D-NEXT: fsd ft0, 88(s1) +; LP64D-NEXT: fld ft0, 80(sp) +; LP64D-NEXT: fsd ft0, 80(s1) +; LP64D-NEXT: fld ft0, 88(sp) +; LP64D-NEXT: fsd ft0, 72(s1) +; LP64D-NEXT: fld ft0, 96(sp) +; LP64D-NEXT: fsd ft0, 64(s1) +; LP64D-NEXT: fld ft0, 104(sp) +; LP64D-NEXT: fsd ft0, 56(s1) +; LP64D-NEXT: fld ft0, 112(sp) +; LP64D-NEXT: fsd ft0, 48(s1) +; LP64D-NEXT: fld ft0, 120(sp) +; LP64D-NEXT: fsd ft0, 40(s1) +; LP64D-NEXT: fld ft0, 128(sp) +; LP64D-NEXT: fsd ft0, 32(s1) +; LP64D-NEXT: fld ft0, 136(sp) +; LP64D-NEXT: fsd ft0, 24(s1) +; LP64D-NEXT: fld ft0, 144(sp) +; LP64D-NEXT: fsd ft0, 16(s1) +; LP64D-NEXT: fld ft0, 152(sp) +; LP64D-NEXT: fsd ft0, %lo(var+8)(s0) +; LP64D-NEXT: fld ft0, 160(sp) +; LP64D-NEXT: fsd ft0, %lo(var)(s0) +; LP64D-NEXT: fld fs11, 168(sp) +; LP64D-NEXT: fld fs10, 176(sp) +; LP64D-NEXT: fld fs9, 184(sp) +; LP64D-NEXT: fld fs8, 192(sp) +; LP64D-NEXT: fld fs7, 200(sp) +; LP64D-NEXT: fld fs6, 208(sp) +; LP64D-NEXT: fld fs5, 216(sp) +; LP64D-NEXT: fld fs4, 224(sp) +; LP64D-NEXT: fld fs3, 232(sp) +; LP64D-NEXT: fld fs2, 240(sp) +; LP64D-NEXT: fld fs1, 248(sp) +; LP64D-NEXT: fld fs0, 256(sp) +; LP64D-NEXT: ld s1, 264(sp) +; LP64D-NEXT: ld s0, 272(sp) +; LP64D-NEXT: ld ra, 280(sp) +; LP64D-NEXT: addi sp, sp, 288 +; LP64D-NEXT: ret %val = load [32 x double], [32 x double]* @var call void @callee() store volatile [32 x double] %val, [32 x double]* @var diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll --- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ @@ -41,10 +42,99 @@ ; RV32I-NEXT: sw s9, 36(sp) ; RV32I-NEXT: sw s10, 32(sp) ; RV32I-NEXT: sw s11, 28(sp) -; RV32I-NEXT: lui a0, %hi(var) -; RV32I-NEXT: lw a1, %lo(var)(a0) -; RV32I-NEXT: sw a1, 24(sp) -; RV32I-NEXT: addi a2, a0, %lo(var) +; RV32I-NEXT: lui a7, %hi(var) +; RV32I-NEXT: lw a0, %lo(var)(a7) +; RV32I-NEXT: sw a0, 24(sp) +; RV32I-NEXT: lw a0, %lo(var+4)(a7) +; RV32I-NEXT: sw a0, 20(sp) +; RV32I-NEXT: lw a0, %lo(var+8)(a7) +; RV32I-NEXT: sw a0, 16(sp) +; RV32I-NEXT: lw a0, %lo(var+12)(a7) +; RV32I-NEXT: sw a0, 12(sp) +; RV32I-NEXT: addi a5, a7, %lo(var) +; RV32I-NEXT: lw a0, 16(a5) +; RV32I-NEXT: sw a0, 8(sp) +; RV32I-NEXT: lw a0, 20(a5) +; RV32I-NEXT: sw a0, 4(sp) +; RV32I-NEXT: lw t4, 24(a5) +; RV32I-NEXT: lw t5, 28(a5) +; RV32I-NEXT: lw t6, 32(a5) +; RV32I-NEXT: lw s2, 36(a5) +; RV32I-NEXT: lw s3, 40(a5) +; RV32I-NEXT: lw s4, 44(a5) +; RV32I-NEXT: lw s5, 48(a5) +; RV32I-NEXT: lw s6, 52(a5) +; RV32I-NEXT: lw s7, 56(a5) +; RV32I-NEXT: lw s8, 60(a5) +; RV32I-NEXT: lw s9, 64(a5) +; RV32I-NEXT: lw s10, 68(a5) +; RV32I-NEXT: lw s11, 72(a5) +; RV32I-NEXT: lw ra, 76(a5) +; RV32I-NEXT: lw s1, 80(a5) +; RV32I-NEXT: lw t3, 84(a5) +; RV32I-NEXT: lw t2, 88(a5) +; RV32I-NEXT: lw t1, 92(a5) +; RV32I-NEXT: lw t0, 96(a5) +; RV32I-NEXT: lw s0, 100(a5) +; RV32I-NEXT: lw a6, 104(a5) +; RV32I-NEXT: lw a4, 108(a5) +; RV32I-NEXT: lw a0, 124(a5) +; RV32I-NEXT: lw a1, 120(a5) +; RV32I-NEXT: lw a2, 116(a5) +; RV32I-NEXT: lw a3, 112(a5) +; RV32I-NEXT: sw a0, 124(a5) +; RV32I-NEXT: sw a1, 120(a5) +; RV32I-NEXT: sw a2, 116(a5) +; RV32I-NEXT: sw a3, 112(a5) +; RV32I-NEXT: sw a4, 108(a5) +; RV32I-NEXT: sw a6, 104(a5) +; RV32I-NEXT: sw s0, 100(a5) +; RV32I-NEXT: sw t0, 96(a5) +; RV32I-NEXT: sw t1, 92(a5) +; RV32I-NEXT: sw t2, 88(a5) +; RV32I-NEXT: sw t3, 84(a5) +; RV32I-NEXT: sw s1, 80(a5) +; RV32I-NEXT: sw ra, 76(a5) +; RV32I-NEXT: sw s11, 72(a5) +; RV32I-NEXT: sw s10, 68(a5) +; RV32I-NEXT: sw s9, 64(a5) +; RV32I-NEXT: sw s8, 60(a5) +; RV32I-NEXT: sw s7, 56(a5) +; RV32I-NEXT: sw s6, 52(a5) +; RV32I-NEXT: sw s5, 48(a5) +; RV32I-NEXT: sw s4, 44(a5) +; RV32I-NEXT: sw s3, 40(a5) +; RV32I-NEXT: sw s2, 36(a5) +; RV32I-NEXT: sw t6, 32(a5) +; RV32I-NEXT: sw t5, 28(a5) +; RV32I-NEXT: sw t4, 24(a5) +; RV32I-NEXT: lw a0, 4(sp) +; RV32I-NEXT: sw a0, 20(a5) +; RV32I-NEXT: lw a0, 8(sp) +; RV32I-NEXT: sw a0, 16(a5) +; RV32I-NEXT: lw a0, 12(sp) +; RV32I-NEXT: sw a0, %lo(var+12)(a7) +; RV32I-NEXT: lw a0, 16(sp) +; RV32I-NEXT: sw a0, %lo(var+8)(a7) +; RV32I-NEXT: lw a0, 20(sp) +; RV32I-NEXT: sw a0, %lo(var+4)(a7) +; RV32I-NEXT: lw a0, 24(sp) +; RV32I-NEXT: sw a0, %lo(var)(a7) +; RV32I-NEXT: lw s11, 28(sp) +; RV32I-NEXT: lw s10, 32(sp) +; RV32I-NEXT: lw s9, 36(sp) +; RV32I-NEXT: lw s8, 40(sp) +; RV32I-NEXT: lw s7, 44(sp) +; RV32I-NEXT: lw s6, 48(sp) +; RV32I-NEXT: lw s5, 52(sp) +; RV32I-NEXT: lw s4, 56(sp) +; RV32I-NEXT: lw s3, 60(sp) +; RV32I-NEXT: lw s2, 64(sp) +; RV32I-NEXT: lw s1, 68(sp) +; RV32I-NEXT: lw s0, 72(sp) +; RV32I-NEXT: lw ra, 76(sp) +; RV32I-NEXT: addi sp, sp, 80 +; RV32I-NEXT: ret ; ; RV32I-WITH-FP-LABEL: callee: ; RV32I-WITH-FP: # %bb.0: @@ -63,31 +153,211 @@ ; RV32I-WITH-FP-NEXT: sw s10, 32(sp) ; RV32I-WITH-FP-NEXT: sw s11, 28(sp) ; RV32I-WITH-FP-NEXT: addi s0, sp, 80 -; RV32I-WITH-FP-NEXT: lui a0, %hi(var) -; RV32I-WITH-FP-NEXT: lw a1, %lo(var)(a0) -; RV32I-WITH-FP-NEXT: sw a1, -56(s0) -; RV32I-WITH-FP-NEXT: addi a2, a0, %lo(var) +; RV32I-WITH-FP-NEXT: lui a7, %hi(var) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(a7) +; RV32I-WITH-FP-NEXT: sw a0, -56(s0) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(a7) +; RV32I-WITH-FP-NEXT: sw a0, -60(s0) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(a7) +; RV32I-WITH-FP-NEXT: sw a0, -64(s0) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(a7) +; RV32I-WITH-FP-NEXT: sw a0, -68(s0) +; RV32I-WITH-FP-NEXT: addi a5, a7, %lo(var) +; RV32I-WITH-FP-NEXT: lw a0, 16(a5) +; RV32I-WITH-FP-NEXT: sw a0, -72(s0) +; RV32I-WITH-FP-NEXT: lw a0, 20(a5) +; RV32I-WITH-FP-NEXT: sw a0, -76(s0) +; RV32I-WITH-FP-NEXT: lw a0, 24(a5) +; RV32I-WITH-FP-NEXT: sw a0, -80(s0) +; RV32I-WITH-FP-NEXT: lw t5, 28(a5) +; RV32I-WITH-FP-NEXT: lw t6, 32(a5) +; RV32I-WITH-FP-NEXT: lw s2, 36(a5) +; RV32I-WITH-FP-NEXT: lw s3, 40(a5) +; RV32I-WITH-FP-NEXT: lw s4, 44(a5) +; RV32I-WITH-FP-NEXT: lw s5, 48(a5) +; RV32I-WITH-FP-NEXT: lw s6, 52(a5) +; RV32I-WITH-FP-NEXT: lw s7, 56(a5) +; RV32I-WITH-FP-NEXT: lw s8, 60(a5) +; RV32I-WITH-FP-NEXT: lw s9, 64(a5) +; RV32I-WITH-FP-NEXT: lw s10, 68(a5) +; RV32I-WITH-FP-NEXT: lw s11, 72(a5) +; RV32I-WITH-FP-NEXT: lw ra, 76(a5) +; RV32I-WITH-FP-NEXT: lw t4, 80(a5) +; RV32I-WITH-FP-NEXT: lw t3, 84(a5) +; RV32I-WITH-FP-NEXT: lw t2, 88(a5) +; RV32I-WITH-FP-NEXT: lw s1, 92(a5) +; RV32I-WITH-FP-NEXT: lw t1, 96(a5) +; RV32I-WITH-FP-NEXT: lw t0, 100(a5) +; RV32I-WITH-FP-NEXT: lw a6, 104(a5) +; RV32I-WITH-FP-NEXT: lw a4, 108(a5) +; RV32I-WITH-FP-NEXT: lw a0, 124(a5) +; RV32I-WITH-FP-NEXT: lw a1, 120(a5) +; RV32I-WITH-FP-NEXT: lw a2, 116(a5) +; RV32I-WITH-FP-NEXT: lw a3, 112(a5) +; RV32I-WITH-FP-NEXT: sw a0, 124(a5) +; RV32I-WITH-FP-NEXT: sw a1, 120(a5) +; RV32I-WITH-FP-NEXT: sw a2, 116(a5) +; RV32I-WITH-FP-NEXT: sw a3, 112(a5) +; RV32I-WITH-FP-NEXT: sw a4, 108(a5) +; RV32I-WITH-FP-NEXT: sw a6, 104(a5) +; RV32I-WITH-FP-NEXT: sw t0, 100(a5) +; RV32I-WITH-FP-NEXT: sw t1, 96(a5) +; RV32I-WITH-FP-NEXT: sw s1, 92(a5) +; RV32I-WITH-FP-NEXT: sw t2, 88(a5) +; RV32I-WITH-FP-NEXT: sw t3, 84(a5) +; RV32I-WITH-FP-NEXT: sw t4, 80(a5) +; RV32I-WITH-FP-NEXT: sw ra, 76(a5) +; RV32I-WITH-FP-NEXT: sw s11, 72(a5) +; RV32I-WITH-FP-NEXT: sw s10, 68(a5) +; RV32I-WITH-FP-NEXT: sw s9, 64(a5) +; RV32I-WITH-FP-NEXT: sw s8, 60(a5) +; RV32I-WITH-FP-NEXT: sw s7, 56(a5) +; RV32I-WITH-FP-NEXT: sw s6, 52(a5) +; RV32I-WITH-FP-NEXT: sw s5, 48(a5) +; RV32I-WITH-FP-NEXT: sw s4, 44(a5) +; RV32I-WITH-FP-NEXT: sw s3, 40(a5) +; RV32I-WITH-FP-NEXT: sw s2, 36(a5) +; RV32I-WITH-FP-NEXT: sw t6, 32(a5) +; RV32I-WITH-FP-NEXT: sw t5, 28(a5) +; RV32I-WITH-FP-NEXT: lw a0, -80(s0) +; RV32I-WITH-FP-NEXT: sw a0, 24(a5) +; RV32I-WITH-FP-NEXT: lw a0, -76(s0) +; RV32I-WITH-FP-NEXT: sw a0, 20(a5) +; RV32I-WITH-FP-NEXT: lw a0, -72(s0) +; RV32I-WITH-FP-NEXT: sw a0, 16(a5) +; RV32I-WITH-FP-NEXT: lw a0, -68(s0) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) +; RV32I-WITH-FP-NEXT: lw a0, -64(s0) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(a7) +; RV32I-WITH-FP-NEXT: lw a0, -60(s0) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(a7) +; RV32I-WITH-FP-NEXT: lw a0, -56(s0) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(a7) +; RV32I-WITH-FP-NEXT: lw s11, 28(sp) +; RV32I-WITH-FP-NEXT: lw s10, 32(sp) +; RV32I-WITH-FP-NEXT: lw s9, 36(sp) +; RV32I-WITH-FP-NEXT: lw s8, 40(sp) +; RV32I-WITH-FP-NEXT: lw s7, 44(sp) +; RV32I-WITH-FP-NEXT: lw s6, 48(sp) +; RV32I-WITH-FP-NEXT: lw s5, 52(sp) +; RV32I-WITH-FP-NEXT: lw s4, 56(sp) +; RV32I-WITH-FP-NEXT: lw s3, 60(sp) +; RV32I-WITH-FP-NEXT: lw s2, 64(sp) +; RV32I-WITH-FP-NEXT: lw s1, 68(sp) +; RV32I-WITH-FP-NEXT: lw s0, 72(sp) +; RV32I-WITH-FP-NEXT: lw ra, 76(sp) +; RV32I-WITH-FP-NEXT: addi sp, sp, 80 +; RV32I-WITH-FP-NEXT: ret ; ; RV64I-LABEL: callee: ; RV64I: # %bb.0: -; RV64I-NEXT: addi sp, sp, -144 -; RV64I-NEXT: sd ra, 136(sp) -; RV64I-NEXT: sd s0, 128(sp) -; RV64I-NEXT: sd s1, 120(sp) -; RV64I-NEXT: sd s2, 112(sp) -; RV64I-NEXT: sd s3, 104(sp) -; RV64I-NEXT: sd s4, 96(sp) -; RV64I-NEXT: sd s5, 88(sp) -; RV64I-NEXT: sd s6, 80(sp) -; RV64I-NEXT: sd s7, 72(sp) -; RV64I-NEXT: sd s8, 64(sp) -; RV64I-NEXT: sd s9, 56(sp) -; RV64I-NEXT: sd s10, 48(sp) -; RV64I-NEXT: sd s11, 40(sp) -; RV64I-NEXT: lui a0, %hi(var) -; RV64I-NEXT: lw a1, %lo(var)(a0) -; RV64I-NEXT: sd a1, 32(sp) -; RV64I-NEXT: addi a2, a0, %lo(var) +; RV64I-NEXT: addi sp, sp, -160 +; RV64I-NEXT: sd ra, 152(sp) +; RV64I-NEXT: sd s0, 144(sp) +; RV64I-NEXT: sd s1, 136(sp) +; RV64I-NEXT: sd s2, 128(sp) +; RV64I-NEXT: sd s3, 120(sp) +; RV64I-NEXT: sd s4, 112(sp) +; RV64I-NEXT: sd s5, 104(sp) +; RV64I-NEXT: sd s6, 96(sp) +; RV64I-NEXT: sd s7, 88(sp) +; RV64I-NEXT: sd s8, 80(sp) +; RV64I-NEXT: sd s9, 72(sp) +; RV64I-NEXT: sd s10, 64(sp) +; RV64I-NEXT: sd s11, 56(sp) +; RV64I-NEXT: lui a7, %hi(var) +; RV64I-NEXT: lw a0, %lo(var)(a7) +; RV64I-NEXT: sd a0, 48(sp) +; RV64I-NEXT: lw a0, %lo(var+4)(a7) +; RV64I-NEXT: sd a0, 40(sp) +; RV64I-NEXT: lw a0, %lo(var+8)(a7) +; RV64I-NEXT: sd a0, 32(sp) +; RV64I-NEXT: lw a0, %lo(var+12)(a7) +; RV64I-NEXT: sd a0, 24(sp) +; RV64I-NEXT: addi a5, a7, %lo(var) +; RV64I-NEXT: lw a0, 16(a5) +; RV64I-NEXT: sd a0, 16(sp) +; RV64I-NEXT: lw a0, 20(a5) +; RV64I-NEXT: sd a0, 8(sp) +; RV64I-NEXT: lw t4, 24(a5) +; RV64I-NEXT: lw t5, 28(a5) +; RV64I-NEXT: lw t6, 32(a5) +; RV64I-NEXT: lw s2, 36(a5) +; RV64I-NEXT: lw s3, 40(a5) +; RV64I-NEXT: lw s4, 44(a5) +; RV64I-NEXT: lw s5, 48(a5) +; RV64I-NEXT: lw s6, 52(a5) +; RV64I-NEXT: lw s7, 56(a5) +; RV64I-NEXT: lw s8, 60(a5) +; RV64I-NEXT: lw s9, 64(a5) +; RV64I-NEXT: lw s10, 68(a5) +; RV64I-NEXT: lw s11, 72(a5) +; RV64I-NEXT: lw ra, 76(a5) +; RV64I-NEXT: lw s1, 80(a5) +; RV64I-NEXT: lw t3, 84(a5) +; RV64I-NEXT: lw t2, 88(a5) +; RV64I-NEXT: lw t1, 92(a5) +; RV64I-NEXT: lw t0, 96(a5) +; RV64I-NEXT: lw s0, 100(a5) +; RV64I-NEXT: lw a6, 104(a5) +; RV64I-NEXT: lw a4, 108(a5) +; RV64I-NEXT: lw a0, 124(a5) +; RV64I-NEXT: lw a1, 120(a5) +; RV64I-NEXT: lw a2, 116(a5) +; RV64I-NEXT: lw a3, 112(a5) +; RV64I-NEXT: sw a0, 124(a5) +; RV64I-NEXT: sw a1, 120(a5) +; RV64I-NEXT: sw a2, 116(a5) +; RV64I-NEXT: sw a3, 112(a5) +; RV64I-NEXT: sw a4, 108(a5) +; RV64I-NEXT: sw a6, 104(a5) +; RV64I-NEXT: sw s0, 100(a5) +; RV64I-NEXT: sw t0, 96(a5) +; RV64I-NEXT: sw t1, 92(a5) +; RV64I-NEXT: sw t2, 88(a5) +; RV64I-NEXT: sw t3, 84(a5) +; RV64I-NEXT: sw s1, 80(a5) +; RV64I-NEXT: sw ra, 76(a5) +; RV64I-NEXT: sw s11, 72(a5) +; RV64I-NEXT: sw s10, 68(a5) +; RV64I-NEXT: sw s9, 64(a5) +; RV64I-NEXT: sw s8, 60(a5) +; RV64I-NEXT: sw s7, 56(a5) +; RV64I-NEXT: sw s6, 52(a5) +; RV64I-NEXT: sw s5, 48(a5) +; RV64I-NEXT: sw s4, 44(a5) +; RV64I-NEXT: sw s3, 40(a5) +; RV64I-NEXT: sw s2, 36(a5) +; RV64I-NEXT: sw t6, 32(a5) +; RV64I-NEXT: sw t5, 28(a5) +; RV64I-NEXT: sw t4, 24(a5) +; RV64I-NEXT: ld a0, 8(sp) +; RV64I-NEXT: sw a0, 20(a5) +; RV64I-NEXT: ld a0, 16(sp) +; RV64I-NEXT: sw a0, 16(a5) +; RV64I-NEXT: ld a0, 24(sp) +; RV64I-NEXT: sw a0, %lo(var+12)(a7) +; RV64I-NEXT: ld a0, 32(sp) +; RV64I-NEXT: sw a0, %lo(var+8)(a7) +; RV64I-NEXT: ld a0, 40(sp) +; RV64I-NEXT: sw a0, %lo(var+4)(a7) +; RV64I-NEXT: ld a0, 48(sp) +; RV64I-NEXT: sw a0, %lo(var)(a7) +; RV64I-NEXT: ld s11, 56(sp) +; RV64I-NEXT: ld s10, 64(sp) +; RV64I-NEXT: ld s9, 72(sp) +; RV64I-NEXT: ld s8, 80(sp) +; RV64I-NEXT: ld s7, 88(sp) +; RV64I-NEXT: ld s6, 96(sp) +; RV64I-NEXT: ld s5, 104(sp) +; RV64I-NEXT: ld s4, 112(sp) +; RV64I-NEXT: ld s3, 120(sp) +; RV64I-NEXT: ld s2, 128(sp) +; RV64I-NEXT: ld s1, 136(sp) +; RV64I-NEXT: ld s0, 144(sp) +; RV64I-NEXT: ld ra, 152(sp) +; RV64I-NEXT: addi sp, sp, 160 +; RV64I-NEXT: ret ; ; RV64I-WITH-FP-LABEL: callee: ; RV64I-WITH-FP: # %bb.0: @@ -106,10 +376,101 @@ ; RV64I-WITH-FP-NEXT: sd s10, 64(sp) ; RV64I-WITH-FP-NEXT: sd s11, 56(sp) ; RV64I-WITH-FP-NEXT: addi s0, sp, 160 -; RV64I-WITH-FP-NEXT: lui a0, %hi(var) -; RV64I-WITH-FP-NEXT: lw a1, %lo(var)(a0) -; RV64I-WITH-FP-NEXT: sd a1, -112(s0) -; RV64I-WITH-FP-NEXT: addi a2, a0, %lo(var) +; RV64I-WITH-FP-NEXT: lui a7, %hi(var) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(a7) +; RV64I-WITH-FP-NEXT: sd a0, -112(s0) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(a7) +; RV64I-WITH-FP-NEXT: sd a0, -120(s0) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(a7) +; RV64I-WITH-FP-NEXT: sd a0, -128(s0) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(a7) +; RV64I-WITH-FP-NEXT: sd a0, -136(s0) +; RV64I-WITH-FP-NEXT: addi a5, a7, %lo(var) +; RV64I-WITH-FP-NEXT: lw a0, 16(a5) +; RV64I-WITH-FP-NEXT: sd a0, -144(s0) +; RV64I-WITH-FP-NEXT: lw a0, 20(a5) +; RV64I-WITH-FP-NEXT: sd a0, -152(s0) +; RV64I-WITH-FP-NEXT: lw a0, 24(a5) +; RV64I-WITH-FP-NEXT: sd a0, -160(s0) +; RV64I-WITH-FP-NEXT: lw t5, 28(a5) +; RV64I-WITH-FP-NEXT: lw t6, 32(a5) +; RV64I-WITH-FP-NEXT: lw s2, 36(a5) +; RV64I-WITH-FP-NEXT: lw s3, 40(a5) +; RV64I-WITH-FP-NEXT: lw s4, 44(a5) +; RV64I-WITH-FP-NEXT: lw s5, 48(a5) +; RV64I-WITH-FP-NEXT: lw s6, 52(a5) +; RV64I-WITH-FP-NEXT: lw s7, 56(a5) +; RV64I-WITH-FP-NEXT: lw s8, 60(a5) +; RV64I-WITH-FP-NEXT: lw s9, 64(a5) +; RV64I-WITH-FP-NEXT: lw s10, 68(a5) +; RV64I-WITH-FP-NEXT: lw s11, 72(a5) +; RV64I-WITH-FP-NEXT: lw ra, 76(a5) +; RV64I-WITH-FP-NEXT: lw t4, 80(a5) +; RV64I-WITH-FP-NEXT: lw t3, 84(a5) +; RV64I-WITH-FP-NEXT: lw t2, 88(a5) +; RV64I-WITH-FP-NEXT: lw s1, 92(a5) +; RV64I-WITH-FP-NEXT: lw t1, 96(a5) +; RV64I-WITH-FP-NEXT: lw t0, 100(a5) +; RV64I-WITH-FP-NEXT: lw a6, 104(a5) +; RV64I-WITH-FP-NEXT: lw a4, 108(a5) +; RV64I-WITH-FP-NEXT: lw a0, 124(a5) +; RV64I-WITH-FP-NEXT: lw a1, 120(a5) +; RV64I-WITH-FP-NEXT: lw a2, 116(a5) +; RV64I-WITH-FP-NEXT: lw a3, 112(a5) +; RV64I-WITH-FP-NEXT: sw a0, 124(a5) +; RV64I-WITH-FP-NEXT: sw a1, 120(a5) +; RV64I-WITH-FP-NEXT: sw a2, 116(a5) +; RV64I-WITH-FP-NEXT: sw a3, 112(a5) +; RV64I-WITH-FP-NEXT: sw a4, 108(a5) +; RV64I-WITH-FP-NEXT: sw a6, 104(a5) +; RV64I-WITH-FP-NEXT: sw t0, 100(a5) +; RV64I-WITH-FP-NEXT: sw t1, 96(a5) +; RV64I-WITH-FP-NEXT: sw s1, 92(a5) +; RV64I-WITH-FP-NEXT: sw t2, 88(a5) +; RV64I-WITH-FP-NEXT: sw t3, 84(a5) +; RV64I-WITH-FP-NEXT: sw t4, 80(a5) +; RV64I-WITH-FP-NEXT: sw ra, 76(a5) +; RV64I-WITH-FP-NEXT: sw s11, 72(a5) +; RV64I-WITH-FP-NEXT: sw s10, 68(a5) +; RV64I-WITH-FP-NEXT: sw s9, 64(a5) +; RV64I-WITH-FP-NEXT: sw s8, 60(a5) +; RV64I-WITH-FP-NEXT: sw s7, 56(a5) +; RV64I-WITH-FP-NEXT: sw s6, 52(a5) +; RV64I-WITH-FP-NEXT: sw s5, 48(a5) +; RV64I-WITH-FP-NEXT: sw s4, 44(a5) +; RV64I-WITH-FP-NEXT: sw s3, 40(a5) +; RV64I-WITH-FP-NEXT: sw s2, 36(a5) +; RV64I-WITH-FP-NEXT: sw t6, 32(a5) +; RV64I-WITH-FP-NEXT: sw t5, 28(a5) +; RV64I-WITH-FP-NEXT: ld a0, -160(s0) +; RV64I-WITH-FP-NEXT: sw a0, 24(a5) +; RV64I-WITH-FP-NEXT: ld a0, -152(s0) +; RV64I-WITH-FP-NEXT: sw a0, 20(a5) +; RV64I-WITH-FP-NEXT: ld a0, -144(s0) +; RV64I-WITH-FP-NEXT: sw a0, 16(a5) +; RV64I-WITH-FP-NEXT: ld a0, -136(s0) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) +; RV64I-WITH-FP-NEXT: ld a0, -128(s0) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(a7) +; RV64I-WITH-FP-NEXT: ld a0, -120(s0) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(a7) +; RV64I-WITH-FP-NEXT: ld a0, -112(s0) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(a7) +; RV64I-WITH-FP-NEXT: ld s11, 56(sp) +; RV64I-WITH-FP-NEXT: ld s10, 64(sp) +; RV64I-WITH-FP-NEXT: ld s9, 72(sp) +; RV64I-WITH-FP-NEXT: ld s8, 80(sp) +; RV64I-WITH-FP-NEXT: ld s7, 88(sp) +; RV64I-WITH-FP-NEXT: ld s6, 96(sp) +; RV64I-WITH-FP-NEXT: ld s5, 104(sp) +; RV64I-WITH-FP-NEXT: ld s4, 112(sp) +; RV64I-WITH-FP-NEXT: ld s3, 120(sp) +; RV64I-WITH-FP-NEXT: ld s2, 128(sp) +; RV64I-WITH-FP-NEXT: ld s1, 136(sp) +; RV64I-WITH-FP-NEXT: ld s0, 144(sp) +; RV64I-WITH-FP-NEXT: ld ra, 152(sp) +; RV64I-WITH-FP-NEXT: addi sp, sp, 160 +; RV64I-WITH-FP-NEXT: ret %val = load [32 x i32], [32 x i32]* @var store volatile [32 x i32] %val, [32 x i32]* @var ret void @@ -120,127 +481,583 @@ define void @caller() nounwind { ; RV32I-LABEL: caller: -; RV32I: lui a0, %hi(var) -; RV32I-NEXT: lw a1, %lo(var)(a0) -; RV32I-NEXT: sw a1, 88(sp) -; RV32I-NEXT: addi s0, a0, %lo(var) - -; RV32I: sw a0, 8(sp) -; RV32I-NEXT: lw s2, 84(s0) -; RV32I-NEXT: lw s3, 88(s0) -; RV32I-NEXT: lw s4, 92(s0) -; RV32I-NEXT: lw s5, 96(s0) -; RV32I-NEXT: lw s6, 100(s0) -; RV32I-NEXT: lw s7, 104(s0) -; RV32I-NEXT: lw s8, 108(s0) -; RV32I-NEXT: lw s9, 112(s0) -; RV32I-NEXT: lw s10, 116(s0) -; RV32I-NEXT: lw s11, 120(s0) -; RV32I-NEXT: lw s1, 124(s0) +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -144 +; RV32I-NEXT: sw ra, 140(sp) +; RV32I-NEXT: sw s0, 136(sp) +; RV32I-NEXT: sw s1, 132(sp) +; RV32I-NEXT: sw s2, 128(sp) +; RV32I-NEXT: sw s3, 124(sp) +; RV32I-NEXT: sw s4, 120(sp) +; RV32I-NEXT: sw s5, 116(sp) +; RV32I-NEXT: sw s6, 112(sp) +; RV32I-NEXT: sw s7, 108(sp) +; RV32I-NEXT: sw s8, 104(sp) +; RV32I-NEXT: sw s9, 100(sp) +; RV32I-NEXT: sw s10, 96(sp) +; RV32I-NEXT: sw s11, 92(sp) +; RV32I-NEXT: lui s0, %hi(var) +; RV32I-NEXT: lw a0, %lo(var)(s0) +; RV32I-NEXT: sw a0, 88(sp) +; RV32I-NEXT: lw a0, %lo(var+4)(s0) +; RV32I-NEXT: sw a0, 84(sp) +; RV32I-NEXT: lw a0, %lo(var+8)(s0) +; RV32I-NEXT: sw a0, 80(sp) +; RV32I-NEXT: lw a0, %lo(var+12)(s0) +; RV32I-NEXT: sw a0, 76(sp) +; RV32I-NEXT: addi s1, s0, %lo(var) +; RV32I-NEXT: lw a0, 16(s1) +; RV32I-NEXT: sw a0, 72(sp) +; RV32I-NEXT: lw a0, 20(s1) +; RV32I-NEXT: sw a0, 68(sp) +; RV32I-NEXT: lw a0, 24(s1) +; RV32I-NEXT: sw a0, 64(sp) +; RV32I-NEXT: lw a0, 28(s1) +; RV32I-NEXT: sw a0, 60(sp) +; RV32I-NEXT: lw a0, 32(s1) +; RV32I-NEXT: sw a0, 56(sp) +; RV32I-NEXT: lw a0, 36(s1) +; RV32I-NEXT: sw a0, 52(sp) +; RV32I-NEXT: lw a0, 40(s1) +; RV32I-NEXT: sw a0, 48(sp) +; RV32I-NEXT: lw a0, 44(s1) +; RV32I-NEXT: sw a0, 44(sp) +; RV32I-NEXT: lw a0, 48(s1) +; RV32I-NEXT: sw a0, 40(sp) +; RV32I-NEXT: lw a0, 52(s1) +; RV32I-NEXT: sw a0, 36(sp) +; RV32I-NEXT: lw a0, 56(s1) +; RV32I-NEXT: sw a0, 32(sp) +; RV32I-NEXT: lw a0, 60(s1) +; RV32I-NEXT: sw a0, 28(sp) +; RV32I-NEXT: lw a0, 64(s1) +; RV32I-NEXT: sw a0, 24(sp) +; RV32I-NEXT: lw a0, 68(s1) +; RV32I-NEXT: sw a0, 20(sp) +; RV32I-NEXT: lw a0, 72(s1) +; RV32I-NEXT: sw a0, 16(sp) +; RV32I-NEXT: lw a0, 76(s1) +; RV32I-NEXT: sw a0, 12(sp) +; RV32I-NEXT: lw a0, 80(s1) +; RV32I-NEXT: sw a0, 8(sp) +; RV32I-NEXT: lw a0, 84(s1) +; RV32I-NEXT: sw a0, 4(sp) +; RV32I-NEXT: lw s4, 88(s1) +; RV32I-NEXT: lw s5, 92(s1) +; RV32I-NEXT: lw s6, 96(s1) +; RV32I-NEXT: lw s7, 100(s1) +; RV32I-NEXT: lw s8, 104(s1) +; RV32I-NEXT: lw s9, 108(s1) +; RV32I-NEXT: lw s10, 112(s1) +; RV32I-NEXT: lw s11, 116(s1) +; RV32I-NEXT: lw s2, 120(s1) +; RV32I-NEXT: lw s3, 124(s1) ; RV32I-NEXT: call callee -; RV32I-NEXT: sw s1, 124(s0) -; RV32I-NEXT: sw s11, 120(s0) -; RV32I-NEXT: sw s10, 116(s0) -; RV32I-NEXT: sw s9, 112(s0) -; RV32I-NEXT: sw s8, 108(s0) -; RV32I-NEXT: sw s7, 104(s0) -; RV32I-NEXT: sw s6, 100(s0) -; RV32I-NEXT: sw s5, 96(s0) -; RV32I-NEXT: sw s4, 92(s0) -; RV32I-NEXT: sw s3, 88(s0) -; RV32I-NEXT: sw s2, 84(s0) +; RV32I-NEXT: sw s3, 124(s1) +; RV32I-NEXT: sw s2, 120(s1) +; RV32I-NEXT: sw s11, 116(s1) +; RV32I-NEXT: sw s10, 112(s1) +; RV32I-NEXT: sw s9, 108(s1) +; RV32I-NEXT: sw s8, 104(s1) +; RV32I-NEXT: sw s7, 100(s1) +; RV32I-NEXT: sw s6, 96(s1) +; RV32I-NEXT: sw s5, 92(s1) +; RV32I-NEXT: sw s4, 88(s1) +; RV32I-NEXT: lw a0, 4(sp) +; RV32I-NEXT: sw a0, 84(s1) ; RV32I-NEXT: lw a0, 8(sp) +; RV32I-NEXT: sw a0, 80(s1) +; RV32I-NEXT: lw a0, 12(sp) +; RV32I-NEXT: sw a0, 76(s1) +; RV32I-NEXT: lw a0, 16(sp) +; RV32I-NEXT: sw a0, 72(s1) +; RV32I-NEXT: lw a0, 20(sp) +; RV32I-NEXT: sw a0, 68(s1) +; RV32I-NEXT: lw a0, 24(sp) +; RV32I-NEXT: sw a0, 64(s1) +; RV32I-NEXT: lw a0, 28(sp) +; RV32I-NEXT: sw a0, 60(s1) +; RV32I-NEXT: lw a0, 32(sp) +; RV32I-NEXT: sw a0, 56(s1) +; RV32I-NEXT: lw a0, 36(sp) +; RV32I-NEXT: sw a0, 52(s1) +; RV32I-NEXT: lw a0, 40(sp) +; RV32I-NEXT: sw a0, 48(s1) +; RV32I-NEXT: lw a0, 44(sp) +; RV32I-NEXT: sw a0, 44(s1) +; RV32I-NEXT: lw a0, 48(sp) +; RV32I-NEXT: sw a0, 40(s1) +; RV32I-NEXT: lw a0, 52(sp) +; RV32I-NEXT: sw a0, 36(s1) +; RV32I-NEXT: lw a0, 56(sp) +; RV32I-NEXT: sw a0, 32(s1) +; RV32I-NEXT: lw a0, 60(sp) +; RV32I-NEXT: sw a0, 28(s1) +; RV32I-NEXT: lw a0, 64(sp) +; RV32I-NEXT: sw a0, 24(s1) +; RV32I-NEXT: lw a0, 68(sp) +; RV32I-NEXT: sw a0, 20(s1) +; RV32I-NEXT: lw a0, 72(sp) +; RV32I-NEXT: sw a0, 16(s1) +; RV32I-NEXT: lw a0, 76(sp) +; RV32I-NEXT: sw a0, %lo(var+12)(s0) +; RV32I-NEXT: lw a0, 80(sp) +; RV32I-NEXT: sw a0, %lo(var+8)(s0) +; RV32I-NEXT: lw a0, 84(sp) +; RV32I-NEXT: sw a0, %lo(var+4)(s0) +; RV32I-NEXT: lw a0, 88(sp) +; RV32I-NEXT: sw a0, %lo(var)(s0) +; RV32I-NEXT: lw s11, 92(sp) +; RV32I-NEXT: lw s10, 96(sp) +; RV32I-NEXT: lw s9, 100(sp) +; RV32I-NEXT: lw s8, 104(sp) +; RV32I-NEXT: lw s7, 108(sp) +; RV32I-NEXT: lw s6, 112(sp) +; RV32I-NEXT: lw s5, 116(sp) +; RV32I-NEXT: lw s4, 120(sp) +; RV32I-NEXT: lw s3, 124(sp) +; RV32I-NEXT: lw s2, 128(sp) +; RV32I-NEXT: lw s1, 132(sp) +; RV32I-NEXT: lw s0, 136(sp) +; RV32I-NEXT: lw ra, 140(sp) +; RV32I-NEXT: addi sp, sp, 144 +; RV32I-NEXT: ret ; ; RV32I-WITH-FP-LABEL: caller: -; RV32I-WITH-FP: addi s0, sp, 144 -; RV32I-WITH-FP-NEXT: lui a0, %hi(var) -; RV32I-WITH-FP-NEXT: lw a1, %lo(var)(a0) -; RV32I-WITH-FP-NEXT: sw a1, -56(s0) -; RV32I-WITH-FP-NEXT: addi s1, a0, %lo(var) -; RV32I-WITH-FP: sw a0, -140(s0) -; RV32I-WITH-FP-NEXT: lw s5, 88(s1) -; RV32I-WITH-FP-NEXT: lw s6, 92(s1) -; RV32I-WITH-FP-NEXT: lw s7, 96(s1) -; RV32I-WITH-FP-NEXT: lw s8, 100(s1) -; RV32I-WITH-FP-NEXT: lw s9, 104(s1) -; RV32I-WITH-FP-NEXT: lw s10, 108(s1) -; RV32I-WITH-FP-NEXT: lw s11, 112(s1) -; RV32I-WITH-FP-NEXT: lw s2, 116(s1) -; RV32I-WITH-FP-NEXT: lw s3, 120(s1) -; RV32I-WITH-FP-NEXT: lw s4, 124(s1) +; RV32I-WITH-FP: # %bb.0: +; RV32I-WITH-FP-NEXT: addi sp, sp, -144 +; RV32I-WITH-FP-NEXT: sw ra, 140(sp) +; RV32I-WITH-FP-NEXT: sw s0, 136(sp) +; RV32I-WITH-FP-NEXT: sw s1, 132(sp) +; RV32I-WITH-FP-NEXT: sw s2, 128(sp) +; RV32I-WITH-FP-NEXT: sw s3, 124(sp) +; RV32I-WITH-FP-NEXT: sw s4, 120(sp) +; RV32I-WITH-FP-NEXT: sw s5, 116(sp) +; RV32I-WITH-FP-NEXT: sw s6, 112(sp) +; RV32I-WITH-FP-NEXT: sw s7, 108(sp) +; RV32I-WITH-FP-NEXT: sw s8, 104(sp) +; RV32I-WITH-FP-NEXT: sw s9, 100(sp) +; RV32I-WITH-FP-NEXT: sw s10, 96(sp) +; RV32I-WITH-FP-NEXT: sw s11, 92(sp) +; RV32I-WITH-FP-NEXT: addi s0, sp, 144 +; RV32I-WITH-FP-NEXT: lui s6, %hi(var) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(s6) +; RV32I-WITH-FP-NEXT: sw a0, -56(s0) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(s6) +; RV32I-WITH-FP-NEXT: sw a0, -60(s0) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(s6) +; RV32I-WITH-FP-NEXT: sw a0, -64(s0) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(s6) +; RV32I-WITH-FP-NEXT: sw a0, -68(s0) +; RV32I-WITH-FP-NEXT: addi s1, s6, %lo(var) +; RV32I-WITH-FP-NEXT: lw a0, 16(s1) +; RV32I-WITH-FP-NEXT: sw a0, -72(s0) +; RV32I-WITH-FP-NEXT: lw a0, 20(s1) +; RV32I-WITH-FP-NEXT: sw a0, -76(s0) +; RV32I-WITH-FP-NEXT: lw a0, 24(s1) +; RV32I-WITH-FP-NEXT: sw a0, -80(s0) +; RV32I-WITH-FP-NEXT: lw a0, 28(s1) +; RV32I-WITH-FP-NEXT: sw a0, -84(s0) +; RV32I-WITH-FP-NEXT: lw a0, 32(s1) +; RV32I-WITH-FP-NEXT: sw a0, -88(s0) +; RV32I-WITH-FP-NEXT: lw a0, 36(s1) +; RV32I-WITH-FP-NEXT: sw a0, -92(s0) +; RV32I-WITH-FP-NEXT: lw a0, 40(s1) +; RV32I-WITH-FP-NEXT: sw a0, -96(s0) +; RV32I-WITH-FP-NEXT: lw a0, 44(s1) +; RV32I-WITH-FP-NEXT: sw a0, -100(s0) +; RV32I-WITH-FP-NEXT: lw a0, 48(s1) +; RV32I-WITH-FP-NEXT: sw a0, -104(s0) +; RV32I-WITH-FP-NEXT: lw a0, 52(s1) +; RV32I-WITH-FP-NEXT: sw a0, -108(s0) +; RV32I-WITH-FP-NEXT: lw a0, 56(s1) +; RV32I-WITH-FP-NEXT: sw a0, -112(s0) +; RV32I-WITH-FP-NEXT: lw a0, 60(s1) +; RV32I-WITH-FP-NEXT: sw a0, -116(s0) +; RV32I-WITH-FP-NEXT: lw a0, 64(s1) +; RV32I-WITH-FP-NEXT: sw a0, -120(s0) +; RV32I-WITH-FP-NEXT: lw a0, 68(s1) +; RV32I-WITH-FP-NEXT: sw a0, -124(s0) +; RV32I-WITH-FP-NEXT: lw a0, 72(s1) +; RV32I-WITH-FP-NEXT: sw a0, -128(s0) +; RV32I-WITH-FP-NEXT: lw a0, 76(s1) +; RV32I-WITH-FP-NEXT: sw a0, -132(s0) +; RV32I-WITH-FP-NEXT: lw a0, 80(s1) +; RV32I-WITH-FP-NEXT: sw a0, -136(s0) +; RV32I-WITH-FP-NEXT: lw a0, 84(s1) +; RV32I-WITH-FP-NEXT: sw a0, -140(s0) +; RV32I-WITH-FP-NEXT: lw a0, 88(s1) +; RV32I-WITH-FP-NEXT: sw a0, -144(s0) +; RV32I-WITH-FP-NEXT: lw s8, 92(s1) +; RV32I-WITH-FP-NEXT: lw s9, 96(s1) +; RV32I-WITH-FP-NEXT: lw s10, 100(s1) +; RV32I-WITH-FP-NEXT: lw s11, 104(s1) +; RV32I-WITH-FP-NEXT: lw s2, 108(s1) +; RV32I-WITH-FP-NEXT: lw s3, 112(s1) +; RV32I-WITH-FP-NEXT: lw s4, 116(s1) +; RV32I-WITH-FP-NEXT: lw s5, 120(s1) +; RV32I-WITH-FP-NEXT: lw s7, 124(s1) ; RV32I-WITH-FP-NEXT: call callee -; RV32I-WITH-FP-NEXT: sw s4, 124(s1) -; RV32I-WITH-FP-NEXT: sw s3, 120(s1) -; RV32I-WITH-FP-NEXT: sw s2, 116(s1) -; RV32I-WITH-FP-NEXT: sw s11, 112(s1) -; RV32I-WITH-FP-NEXT: sw s10, 108(s1) -; RV32I-WITH-FP-NEXT: sw s9, 104(s1) -; RV32I-WITH-FP-NEXT: sw s8, 100(s1) -; RV32I-WITH-FP-NEXT: sw s7, 96(s1) -; RV32I-WITH-FP-NEXT: sw s6, 92(s1) -; RV32I-WITH-FP-NEXT: sw s5, 88(s1) +; RV32I-WITH-FP-NEXT: sw s7, 124(s1) +; RV32I-WITH-FP-NEXT: sw s5, 120(s1) +; RV32I-WITH-FP-NEXT: sw s4, 116(s1) +; RV32I-WITH-FP-NEXT: sw s3, 112(s1) +; RV32I-WITH-FP-NEXT: sw s2, 108(s1) +; RV32I-WITH-FP-NEXT: sw s11, 104(s1) +; RV32I-WITH-FP-NEXT: sw s10, 100(s1) +; RV32I-WITH-FP-NEXT: sw s9, 96(s1) +; RV32I-WITH-FP-NEXT: sw s8, 92(s1) +; RV32I-WITH-FP-NEXT: lw a0, -144(s0) +; RV32I-WITH-FP-NEXT: sw a0, 88(s1) ; RV32I-WITH-FP-NEXT: lw a0, -140(s0) +; RV32I-WITH-FP-NEXT: sw a0, 84(s1) +; RV32I-WITH-FP-NEXT: lw a0, -136(s0) +; RV32I-WITH-FP-NEXT: sw a0, 80(s1) +; RV32I-WITH-FP-NEXT: lw a0, -132(s0) +; RV32I-WITH-FP-NEXT: sw a0, 76(s1) +; RV32I-WITH-FP-NEXT: lw a0, -128(s0) +; RV32I-WITH-FP-NEXT: sw a0, 72(s1) +; RV32I-WITH-FP-NEXT: lw a0, -124(s0) +; RV32I-WITH-FP-NEXT: sw a0, 68(s1) +; RV32I-WITH-FP-NEXT: lw a0, -120(s0) +; RV32I-WITH-FP-NEXT: sw a0, 64(s1) +; RV32I-WITH-FP-NEXT: lw a0, -116(s0) +; RV32I-WITH-FP-NEXT: sw a0, 60(s1) +; RV32I-WITH-FP-NEXT: lw a0, -112(s0) +; RV32I-WITH-FP-NEXT: sw a0, 56(s1) +; RV32I-WITH-FP-NEXT: lw a0, -108(s0) +; RV32I-WITH-FP-NEXT: sw a0, 52(s1) +; RV32I-WITH-FP-NEXT: lw a0, -104(s0) +; RV32I-WITH-FP-NEXT: sw a0, 48(s1) +; RV32I-WITH-FP-NEXT: lw a0, -100(s0) +; RV32I-WITH-FP-NEXT: sw a0, 44(s1) +; RV32I-WITH-FP-NEXT: lw a0, -96(s0) +; RV32I-WITH-FP-NEXT: sw a0, 40(s1) +; RV32I-WITH-FP-NEXT: lw a0, -92(s0) +; RV32I-WITH-FP-NEXT: sw a0, 36(s1) +; RV32I-WITH-FP-NEXT: lw a0, -88(s0) +; RV32I-WITH-FP-NEXT: sw a0, 32(s1) +; RV32I-WITH-FP-NEXT: lw a0, -84(s0) +; RV32I-WITH-FP-NEXT: sw a0, 28(s1) +; RV32I-WITH-FP-NEXT: lw a0, -80(s0) +; RV32I-WITH-FP-NEXT: sw a0, 24(s1) +; RV32I-WITH-FP-NEXT: lw a0, -76(s0) +; RV32I-WITH-FP-NEXT: sw a0, 20(s1) +; RV32I-WITH-FP-NEXT: lw a0, -72(s0) +; RV32I-WITH-FP-NEXT: sw a0, 16(s1) +; RV32I-WITH-FP-NEXT: lw a0, -68(s0) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(s6) +; RV32I-WITH-FP-NEXT: lw a0, -64(s0) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(s6) +; RV32I-WITH-FP-NEXT: lw a0, -60(s0) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(s6) +; RV32I-WITH-FP-NEXT: lw a0, -56(s0) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(s6) +; RV32I-WITH-FP-NEXT: lw s11, 92(sp) +; RV32I-WITH-FP-NEXT: lw s10, 96(sp) +; RV32I-WITH-FP-NEXT: lw s9, 100(sp) +; RV32I-WITH-FP-NEXT: lw s8, 104(sp) +; RV32I-WITH-FP-NEXT: lw s7, 108(sp) +; RV32I-WITH-FP-NEXT: lw s6, 112(sp) +; RV32I-WITH-FP-NEXT: lw s5, 116(sp) +; RV32I-WITH-FP-NEXT: lw s4, 120(sp) +; RV32I-WITH-FP-NEXT: lw s3, 124(sp) +; RV32I-WITH-FP-NEXT: lw s2, 128(sp) +; RV32I-WITH-FP-NEXT: lw s1, 132(sp) +; RV32I-WITH-FP-NEXT: lw s0, 136(sp) +; RV32I-WITH-FP-NEXT: lw ra, 140(sp) +; RV32I-WITH-FP-NEXT: addi sp, sp, 144 +; RV32I-WITH-FP-NEXT: ret ; ; RV64I-LABEL: caller: -; RV64I: lui a0, %hi(var) -; RV64I-NEXT: lw a1, %lo(var)(a0) -; RV64I-NEXT: sd a1, 160(sp) -; RV64I-NEXT: addi s0, a0, %lo(var) -; RV64I: sd a0, 0(sp) -; RV64I-NEXT: lw s2, 84(s0) -; RV64I-NEXT: lw s3, 88(s0) -; RV64I-NEXT: lw s4, 92(s0) -; RV64I-NEXT: lw s5, 96(s0) -; RV64I-NEXT: lw s6, 100(s0) -; RV64I-NEXT: lw s7, 104(s0) -; RV64I-NEXT: lw s8, 108(s0) -; RV64I-NEXT: lw s9, 112(s0) -; RV64I-NEXT: lw s10, 116(s0) -; RV64I-NEXT: lw s11, 120(s0) -; RV64I-NEXT: lw s1, 124(s0) +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -288 +; RV64I-NEXT: sd ra, 280(sp) +; RV64I-NEXT: sd s0, 272(sp) +; RV64I-NEXT: sd s1, 264(sp) +; RV64I-NEXT: sd s2, 256(sp) +; RV64I-NEXT: sd s3, 248(sp) +; RV64I-NEXT: sd s4, 240(sp) +; RV64I-NEXT: sd s5, 232(sp) +; RV64I-NEXT: sd s6, 224(sp) +; RV64I-NEXT: sd s7, 216(sp) +; RV64I-NEXT: sd s8, 208(sp) +; RV64I-NEXT: sd s9, 200(sp) +; RV64I-NEXT: sd s10, 192(sp) +; RV64I-NEXT: sd s11, 184(sp) +; RV64I-NEXT: lui s0, %hi(var) +; RV64I-NEXT: lw a0, %lo(var)(s0) +; RV64I-NEXT: sd a0, 176(sp) +; RV64I-NEXT: lw a0, %lo(var+4)(s0) +; RV64I-NEXT: sd a0, 168(sp) +; RV64I-NEXT: lw a0, %lo(var+8)(s0) +; RV64I-NEXT: sd a0, 160(sp) +; RV64I-NEXT: lw a0, %lo(var+12)(s0) +; RV64I-NEXT: sd a0, 152(sp) +; RV64I-NEXT: addi s1, s0, %lo(var) +; RV64I-NEXT: lw a0, 16(s1) +; RV64I-NEXT: sd a0, 144(sp) +; RV64I-NEXT: lw a0, 20(s1) +; RV64I-NEXT: sd a0, 136(sp) +; RV64I-NEXT: lw a0, 24(s1) +; RV64I-NEXT: sd a0, 128(sp) +; RV64I-NEXT: lw a0, 28(s1) +; RV64I-NEXT: sd a0, 120(sp) +; RV64I-NEXT: lw a0, 32(s1) +; RV64I-NEXT: sd a0, 112(sp) +; RV64I-NEXT: lw a0, 36(s1) +; RV64I-NEXT: sd a0, 104(sp) +; RV64I-NEXT: lw a0, 40(s1) +; RV64I-NEXT: sd a0, 96(sp) +; RV64I-NEXT: lw a0, 44(s1) +; RV64I-NEXT: sd a0, 88(sp) +; RV64I-NEXT: lw a0, 48(s1) +; RV64I-NEXT: sd a0, 80(sp) +; RV64I-NEXT: lw a0, 52(s1) +; RV64I-NEXT: sd a0, 72(sp) +; RV64I-NEXT: lw a0, 56(s1) +; RV64I-NEXT: sd a0, 64(sp) +; RV64I-NEXT: lw a0, 60(s1) +; RV64I-NEXT: sd a0, 56(sp) +; RV64I-NEXT: lw a0, 64(s1) +; RV64I-NEXT: sd a0, 48(sp) +; RV64I-NEXT: lw a0, 68(s1) +; RV64I-NEXT: sd a0, 40(sp) +; RV64I-NEXT: lw a0, 72(s1) +; RV64I-NEXT: sd a0, 32(sp) +; RV64I-NEXT: lw a0, 76(s1) +; RV64I-NEXT: sd a0, 24(sp) +; RV64I-NEXT: lw a0, 80(s1) +; RV64I-NEXT: sd a0, 16(sp) +; RV64I-NEXT: lw a0, 84(s1) +; RV64I-NEXT: sd a0, 8(sp) +; RV64I-NEXT: lw s4, 88(s1) +; RV64I-NEXT: lw s5, 92(s1) +; RV64I-NEXT: lw s6, 96(s1) +; RV64I-NEXT: lw s7, 100(s1) +; RV64I-NEXT: lw s8, 104(s1) +; RV64I-NEXT: lw s9, 108(s1) +; RV64I-NEXT: lw s10, 112(s1) +; RV64I-NEXT: lw s11, 116(s1) +; RV64I-NEXT: lw s2, 120(s1) +; RV64I-NEXT: lw s3, 124(s1) ; RV64I-NEXT: call callee -; RV64I-NEXT: sw s1, 124(s0) -; RV64I-NEXT: sw s11, 120(s0) -; RV64I-NEXT: sw s10, 116(s0) -; RV64I-NEXT: sw s9, 112(s0) -; RV64I-NEXT: sw s8, 108(s0) -; RV64I-NEXT: sw s7, 104(s0) -; RV64I-NEXT: sw s6, 100(s0) -; RV64I-NEXT: sw s5, 96(s0) -; RV64I-NEXT: sw s4, 92(s0) -; RV64I-NEXT: sw s3, 88(s0) -; RV64I-NEXT: sw s2, 84(s0) -; RV64I-NEXT: ld a0, 0(sp) +; RV64I-NEXT: sw s3, 124(s1) +; RV64I-NEXT: sw s2, 120(s1) +; RV64I-NEXT: sw s11, 116(s1) +; RV64I-NEXT: sw s10, 112(s1) +; RV64I-NEXT: sw s9, 108(s1) +; RV64I-NEXT: sw s8, 104(s1) +; RV64I-NEXT: sw s7, 100(s1) +; RV64I-NEXT: sw s6, 96(s1) +; RV64I-NEXT: sw s5, 92(s1) +; RV64I-NEXT: sw s4, 88(s1) +; RV64I-NEXT: ld a0, 8(sp) +; RV64I-NEXT: sw a0, 84(s1) +; RV64I-NEXT: ld a0, 16(sp) +; RV64I-NEXT: sw a0, 80(s1) +; RV64I-NEXT: ld a0, 24(sp) +; RV64I-NEXT: sw a0, 76(s1) +; RV64I-NEXT: ld a0, 32(sp) +; RV64I-NEXT: sw a0, 72(s1) +; RV64I-NEXT: ld a0, 40(sp) +; RV64I-NEXT: sw a0, 68(s1) +; RV64I-NEXT: ld a0, 48(sp) +; RV64I-NEXT: sw a0, 64(s1) +; RV64I-NEXT: ld a0, 56(sp) +; RV64I-NEXT: sw a0, 60(s1) +; RV64I-NEXT: ld a0, 64(sp) +; RV64I-NEXT: sw a0, 56(s1) +; RV64I-NEXT: ld a0, 72(sp) +; RV64I-NEXT: sw a0, 52(s1) +; RV64I-NEXT: ld a0, 80(sp) +; RV64I-NEXT: sw a0, 48(s1) +; RV64I-NEXT: ld a0, 88(sp) +; RV64I-NEXT: sw a0, 44(s1) +; RV64I-NEXT: ld a0, 96(sp) +; RV64I-NEXT: sw a0, 40(s1) +; RV64I-NEXT: ld a0, 104(sp) +; RV64I-NEXT: sw a0, 36(s1) +; RV64I-NEXT: ld a0, 112(sp) +; RV64I-NEXT: sw a0, 32(s1) +; RV64I-NEXT: ld a0, 120(sp) +; RV64I-NEXT: sw a0, 28(s1) +; RV64I-NEXT: ld a0, 128(sp) +; RV64I-NEXT: sw a0, 24(s1) +; RV64I-NEXT: ld a0, 136(sp) +; RV64I-NEXT: sw a0, 20(s1) +; RV64I-NEXT: ld a0, 144(sp) +; RV64I-NEXT: sw a0, 16(s1) +; RV64I-NEXT: ld a0, 152(sp) +; RV64I-NEXT: sw a0, %lo(var+12)(s0) +; RV64I-NEXT: ld a0, 160(sp) +; RV64I-NEXT: sw a0, %lo(var+8)(s0) +; RV64I-NEXT: ld a0, 168(sp) +; RV64I-NEXT: sw a0, %lo(var+4)(s0) +; RV64I-NEXT: ld a0, 176(sp) +; RV64I-NEXT: sw a0, %lo(var)(s0) +; RV64I-NEXT: ld s11, 184(sp) +; RV64I-NEXT: ld s10, 192(sp) +; RV64I-NEXT: ld s9, 200(sp) +; RV64I-NEXT: ld s8, 208(sp) +; RV64I-NEXT: ld s7, 216(sp) +; RV64I-NEXT: ld s6, 224(sp) +; RV64I-NEXT: ld s5, 232(sp) +; RV64I-NEXT: ld s4, 240(sp) +; RV64I-NEXT: ld s3, 248(sp) +; RV64I-NEXT: ld s2, 256(sp) +; RV64I-NEXT: ld s1, 264(sp) +; RV64I-NEXT: ld s0, 272(sp) +; RV64I-NEXT: ld ra, 280(sp) +; RV64I-NEXT: addi sp, sp, 288 +; RV64I-NEXT: ret ; ; RV64I-WITH-FP-LABEL: caller: -; RV64I-WITH-FP: addi s0, sp, 288 -; RV64I-WITH-FP-NEXT: lui a0, %hi(var) -; RV64I-WITH-FP-NEXT: lw a1, %lo(var)(a0) -; RV64I-WITH-FP-NEXT: sd a1, -112(s0) -; RV64I-WITH-FP-NEXT: addi s1, a0, %lo(var) -; RV64I-WITH-FP: sd a0, -280(s0) -; RV64I-WITH-FP-NEXT: lw s5, 88(s1) -; RV64I-WITH-FP-NEXT: lw s6, 92(s1) -; RV64I-WITH-FP-NEXT: lw s7, 96(s1) -; RV64I-WITH-FP-NEXT: lw s8, 100(s1) -; RV64I-WITH-FP-NEXT: lw s9, 104(s1) -; RV64I-WITH-FP-NEXT: lw s10, 108(s1) -; RV64I-WITH-FP-NEXT: lw s11, 112(s1) -; RV64I-WITH-FP-NEXT: lw s2, 116(s1) -; RV64I-WITH-FP-NEXT: lw s3, 120(s1) -; RV64I-WITH-FP-NEXT: lw s4, 124(s1) +; RV64I-WITH-FP: # %bb.0: +; RV64I-WITH-FP-NEXT: addi sp, sp, -288 +; RV64I-WITH-FP-NEXT: sd ra, 280(sp) +; RV64I-WITH-FP-NEXT: sd s0, 272(sp) +; RV64I-WITH-FP-NEXT: sd s1, 264(sp) +; RV64I-WITH-FP-NEXT: sd s2, 256(sp) +; RV64I-WITH-FP-NEXT: sd s3, 248(sp) +; RV64I-WITH-FP-NEXT: sd s4, 240(sp) +; RV64I-WITH-FP-NEXT: sd s5, 232(sp) +; RV64I-WITH-FP-NEXT: sd s6, 224(sp) +; RV64I-WITH-FP-NEXT: sd s7, 216(sp) +; RV64I-WITH-FP-NEXT: sd s8, 208(sp) +; RV64I-WITH-FP-NEXT: sd s9, 200(sp) +; RV64I-WITH-FP-NEXT: sd s10, 192(sp) +; RV64I-WITH-FP-NEXT: sd s11, 184(sp) +; RV64I-WITH-FP-NEXT: addi s0, sp, 288 +; RV64I-WITH-FP-NEXT: lui s6, %hi(var) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(s6) +; RV64I-WITH-FP-NEXT: sd a0, -112(s0) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(s6) +; RV64I-WITH-FP-NEXT: sd a0, -120(s0) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(s6) +; RV64I-WITH-FP-NEXT: sd a0, -128(s0) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(s6) +; RV64I-WITH-FP-NEXT: sd a0, -136(s0) +; RV64I-WITH-FP-NEXT: addi s1, s6, %lo(var) +; RV64I-WITH-FP-NEXT: lw a0, 16(s1) +; RV64I-WITH-FP-NEXT: sd a0, -144(s0) +; RV64I-WITH-FP-NEXT: lw a0, 20(s1) +; RV64I-WITH-FP-NEXT: sd a0, -152(s0) +; RV64I-WITH-FP-NEXT: lw a0, 24(s1) +; RV64I-WITH-FP-NEXT: sd a0, -160(s0) +; RV64I-WITH-FP-NEXT: lw a0, 28(s1) +; RV64I-WITH-FP-NEXT: sd a0, -168(s0) +; RV64I-WITH-FP-NEXT: lw a0, 32(s1) +; RV64I-WITH-FP-NEXT: sd a0, -176(s0) +; RV64I-WITH-FP-NEXT: lw a0, 36(s1) +; RV64I-WITH-FP-NEXT: sd a0, -184(s0) +; RV64I-WITH-FP-NEXT: lw a0, 40(s1) +; RV64I-WITH-FP-NEXT: sd a0, -192(s0) +; RV64I-WITH-FP-NEXT: lw a0, 44(s1) +; RV64I-WITH-FP-NEXT: sd a0, -200(s0) +; RV64I-WITH-FP-NEXT: lw a0, 48(s1) +; RV64I-WITH-FP-NEXT: sd a0, -208(s0) +; RV64I-WITH-FP-NEXT: lw a0, 52(s1) +; RV64I-WITH-FP-NEXT: sd a0, -216(s0) +; RV64I-WITH-FP-NEXT: lw a0, 56(s1) +; RV64I-WITH-FP-NEXT: sd a0, -224(s0) +; RV64I-WITH-FP-NEXT: lw a0, 60(s1) +; RV64I-WITH-FP-NEXT: sd a0, -232(s0) +; RV64I-WITH-FP-NEXT: lw a0, 64(s1) +; RV64I-WITH-FP-NEXT: sd a0, -240(s0) +; RV64I-WITH-FP-NEXT: lw a0, 68(s1) +; RV64I-WITH-FP-NEXT: sd a0, -248(s0) +; RV64I-WITH-FP-NEXT: lw a0, 72(s1) +; RV64I-WITH-FP-NEXT: sd a0, -256(s0) +; RV64I-WITH-FP-NEXT: lw a0, 76(s1) +; RV64I-WITH-FP-NEXT: sd a0, -264(s0) +; RV64I-WITH-FP-NEXT: lw a0, 80(s1) +; RV64I-WITH-FP-NEXT: sd a0, -272(s0) +; RV64I-WITH-FP-NEXT: lw a0, 84(s1) +; RV64I-WITH-FP-NEXT: sd a0, -280(s0) +; RV64I-WITH-FP-NEXT: lw a0, 88(s1) +; RV64I-WITH-FP-NEXT: sd a0, -288(s0) +; RV64I-WITH-FP-NEXT: lw s8, 92(s1) +; RV64I-WITH-FP-NEXT: lw s9, 96(s1) +; RV64I-WITH-FP-NEXT: lw s10, 100(s1) +; RV64I-WITH-FP-NEXT: lw s11, 104(s1) +; RV64I-WITH-FP-NEXT: lw s2, 108(s1) +; RV64I-WITH-FP-NEXT: lw s3, 112(s1) +; RV64I-WITH-FP-NEXT: lw s4, 116(s1) +; RV64I-WITH-FP-NEXT: lw s5, 120(s1) +; RV64I-WITH-FP-NEXT: lw s7, 124(s1) ; RV64I-WITH-FP-NEXT: call callee -; RV64I-WITH-FP-NEXT: sw s4, 124(s1) -; RV64I-WITH-FP-NEXT: sw s3, 120(s1) -; RV64I-WITH-FP-NEXT: sw s2, 116(s1) -; RV64I-WITH-FP-NEXT: sw s11, 112(s1) -; RV64I-WITH-FP-NEXT: sw s10, 108(s1) -; RV64I-WITH-FP-NEXT: sw s9, 104(s1) -; RV64I-WITH-FP-NEXT: sw s8, 100(s1) -; RV64I-WITH-FP-NEXT: sw s7, 96(s1) -; RV64I-WITH-FP-NEXT: sw s6, 92(s1) -; RV64I-WITH-FP-NEXT: sw s5, 88(s1) +; RV64I-WITH-FP-NEXT: sw s7, 124(s1) +; RV64I-WITH-FP-NEXT: sw s5, 120(s1) +; RV64I-WITH-FP-NEXT: sw s4, 116(s1) +; RV64I-WITH-FP-NEXT: sw s3, 112(s1) +; RV64I-WITH-FP-NEXT: sw s2, 108(s1) +; RV64I-WITH-FP-NEXT: sw s11, 104(s1) +; RV64I-WITH-FP-NEXT: sw s10, 100(s1) +; RV64I-WITH-FP-NEXT: sw s9, 96(s1) +; RV64I-WITH-FP-NEXT: sw s8, 92(s1) +; RV64I-WITH-FP-NEXT: ld a0, -288(s0) +; RV64I-WITH-FP-NEXT: sw a0, 88(s1) ; RV64I-WITH-FP-NEXT: ld a0, -280(s0) +; RV64I-WITH-FP-NEXT: sw a0, 84(s1) +; RV64I-WITH-FP-NEXT: ld a0, -272(s0) +; RV64I-WITH-FP-NEXT: sw a0, 80(s1) +; RV64I-WITH-FP-NEXT: ld a0, -264(s0) +; RV64I-WITH-FP-NEXT: sw a0, 76(s1) +; RV64I-WITH-FP-NEXT: ld a0, -256(s0) +; RV64I-WITH-FP-NEXT: sw a0, 72(s1) +; RV64I-WITH-FP-NEXT: ld a0, -248(s0) +; RV64I-WITH-FP-NEXT: sw a0, 68(s1) +; RV64I-WITH-FP-NEXT: ld a0, -240(s0) +; RV64I-WITH-FP-NEXT: sw a0, 64(s1) +; RV64I-WITH-FP-NEXT: ld a0, -232(s0) +; RV64I-WITH-FP-NEXT: sw a0, 60(s1) +; RV64I-WITH-FP-NEXT: ld a0, -224(s0) +; RV64I-WITH-FP-NEXT: sw a0, 56(s1) +; RV64I-WITH-FP-NEXT: ld a0, -216(s0) +; RV64I-WITH-FP-NEXT: sw a0, 52(s1) +; RV64I-WITH-FP-NEXT: ld a0, -208(s0) +; RV64I-WITH-FP-NEXT: sw a0, 48(s1) +; RV64I-WITH-FP-NEXT: ld a0, -200(s0) +; RV64I-WITH-FP-NEXT: sw a0, 44(s1) +; RV64I-WITH-FP-NEXT: ld a0, -192(s0) +; RV64I-WITH-FP-NEXT: sw a0, 40(s1) +; RV64I-WITH-FP-NEXT: ld a0, -184(s0) +; RV64I-WITH-FP-NEXT: sw a0, 36(s1) +; RV64I-WITH-FP-NEXT: ld a0, -176(s0) +; RV64I-WITH-FP-NEXT: sw a0, 32(s1) +; RV64I-WITH-FP-NEXT: ld a0, -168(s0) +; RV64I-WITH-FP-NEXT: sw a0, 28(s1) +; RV64I-WITH-FP-NEXT: ld a0, -160(s0) +; RV64I-WITH-FP-NEXT: sw a0, 24(s1) +; RV64I-WITH-FP-NEXT: ld a0, -152(s0) +; RV64I-WITH-FP-NEXT: sw a0, 20(s1) +; RV64I-WITH-FP-NEXT: ld a0, -144(s0) +; RV64I-WITH-FP-NEXT: sw a0, 16(s1) +; RV64I-WITH-FP-NEXT: ld a0, -136(s0) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(s6) +; RV64I-WITH-FP-NEXT: ld a0, -128(s0) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(s6) +; RV64I-WITH-FP-NEXT: ld a0, -120(s0) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(s6) +; RV64I-WITH-FP-NEXT: ld a0, -112(s0) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(s6) +; RV64I-WITH-FP-NEXT: ld s11, 184(sp) +; RV64I-WITH-FP-NEXT: ld s10, 192(sp) +; RV64I-WITH-FP-NEXT: ld s9, 200(sp) +; RV64I-WITH-FP-NEXT: ld s8, 208(sp) +; RV64I-WITH-FP-NEXT: ld s7, 216(sp) +; RV64I-WITH-FP-NEXT: ld s6, 224(sp) +; RV64I-WITH-FP-NEXT: ld s5, 232(sp) +; RV64I-WITH-FP-NEXT: ld s4, 240(sp) +; RV64I-WITH-FP-NEXT: ld s3, 248(sp) +; RV64I-WITH-FP-NEXT: ld s2, 256(sp) +; RV64I-WITH-FP-NEXT: ld s1, 264(sp) +; RV64I-WITH-FP-NEXT: ld s0, 272(sp) +; RV64I-WITH-FP-NEXT: ld ra, 280(sp) +; RV64I-WITH-FP-NEXT: addi sp, sp, 288 +; RV64I-WITH-FP-NEXT: ret + %val = load [32 x i32], [32 x i32]* @var call void @callee() store volatile [32 x i32] %val, [32 x i32]* @var diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll --- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll +++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll @@ -23,8 +23,7 @@ ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a1, %hi(g_0) ; RV32I-NEXT: lw a0, %lo(g_0)(a1) -; RV32I-NEXT: addi a1, a1, %lo(g_0) -; RV32I-NEXT: lw a1, 4(a1) +; RV32I-NEXT: lw a1, %lo(g_0+4)(a1) ; RV32I-NEXT: ret ; ; RV64I-LABEL: load_g_0: @@ -99,8 +98,7 @@ ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a1, %hi(g_8) ; RV32I-NEXT: lw a0, %lo(g_8)(a1) -; RV32I-NEXT: addi a1, a1, %lo(g_8) -; RV32I-NEXT: lw a1, 4(a1) +; RV32I-NEXT: lw a1, %lo(g_8+4)(a1) ; RV32I-NEXT: ret ; ; RV64I-LABEL: load_g_8: @@ -118,8 +116,7 @@ ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a1, %hi(g_16) ; RV32I-NEXT: lw a0, %lo(g_16)(a1) -; RV32I-NEXT: addi a1, a1, %lo(g_16) -; RV32I-NEXT: lw a1, 4(a1) +; RV32I-NEXT: lw a1, %lo(g_16+4)(a1) ; RV32I-NEXT: ret ; ; RV64I-LABEL: load_g_16: @@ -155,9 +152,8 @@ ; RV32I-LABEL: store_g_8: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a0, %hi(g_8) +; RV32I-NEXT: sw zero, %lo(g_8+4)(a0) ; RV32I-NEXT: sw zero, %lo(g_8)(a0) -; RV32I-NEXT: addi a0, a0, %lo(g_8) -; RV32I-NEXT: sw zero, 4(a0) ; RV32I-NEXT: ret ; ; RV64I-LABEL: store_g_8: @@ -197,15 +193,14 @@ define i64 @load_ga_16() nounwind { ; RV32I-LABEL: load_ga_16: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: lui a0, %hi(ga_16) -; RV32I-NEXT: addi a1, a0, %lo(ga_16) -; RV32I-NEXT: lw a0, 8(a1) -; RV32I-NEXT: lw a1, 12(a1) +; RV32I-NEXT: lui a1, %hi(ga_16) +; RV32I-NEXT: lw a0, %lo(ga_16+8)(a1) +; RV32I-NEXT: lw a1, %lo(ga_16+12)(a1) ; RV32I-NEXT: ret ; ; RV64I-LABEL: load_ga_16: ; RV64I: # %bb.0: # %entry -; RV64I-NEXT: lui a0, %hi(ga_16+8) +; RV64I-NEXT: lui a0, %hi(ga_16) ; RV64I-NEXT: ld a0, %lo(ga_16+8)(a0) ; RV64I-NEXT: ret entry: @@ -245,8 +240,7 @@ ; RV32I-NEXT: lui a0, %tprel_hi(tl_8) ; RV32I-NEXT: add a1, a0, tp, %tprel_add(tl_8) ; RV32I-NEXT: lw a0, %tprel_lo(tl_8)(a1) -; RV32I-NEXT: addi a1, a1, %tprel_lo(tl_8) -; RV32I-NEXT: lw a1, 4(a1) +; RV32I-NEXT: lw a1, %tprel_lo(tl_8+4)(a1) ; RV32I-NEXT: ret ; ; RV64I-LABEL: load_tl_8: diff --git a/llvm/test/CodeGen/RISCV/fp128.ll b/llvm/test/CodeGen/RISCV/fp128.ll --- a/llvm/test/CodeGen/RISCV/fp128.ll +++ b/llvm/test/CodeGen/RISCV/fp128.ll @@ -14,27 +14,25 @@ ; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: lui a0, %hi(x) -; RV32I-NEXT: addi a1, a0, %lo(x) -; RV32I-NEXT: lw a6, 4(a1) -; RV32I-NEXT: lw a7, 8(a1) -; RV32I-NEXT: lw a1, 12(a1) -; RV32I-NEXT: lw a0, %lo(x)(a0) +; RV32I-NEXT: lw a6, %lo(x)(a0) +; RV32I-NEXT: lw a7, %lo(x+4)(a0) +; RV32I-NEXT: lw a3, %lo(x+8)(a0) +; RV32I-NEXT: lw a0, %lo(x+12)(a0) ; RV32I-NEXT: lui a4, %hi(y) -; RV32I-NEXT: addi a5, a4, %lo(y) -; RV32I-NEXT: lw a2, 4(a5) -; RV32I-NEXT: lw a3, 8(a5) -; RV32I-NEXT: lw a5, 12(a5) -; RV32I-NEXT: lw a4, %lo(y)(a4) -; RV32I-NEXT: sw a4, 8(sp) -; RV32I-NEXT: sw a0, 24(sp) -; RV32I-NEXT: sw a5, 20(sp) -; RV32I-NEXT: sw a3, 16(sp) +; RV32I-NEXT: lw a5, %lo(y)(a4) +; RV32I-NEXT: lw a2, %lo(y+4)(a4) +; RV32I-NEXT: lw a1, %lo(y+8)(a4) +; RV32I-NEXT: lw a4, %lo(y+12)(a4) +; RV32I-NEXT: sw a4, 20(sp) +; RV32I-NEXT: sw a1, 16(sp) ; RV32I-NEXT: sw a2, 12(sp) -; RV32I-NEXT: sw a1, 36(sp) -; RV32I-NEXT: sw a7, 32(sp) +; RV32I-NEXT: sw a5, 8(sp) +; RV32I-NEXT: sw a0, 36(sp) +; RV32I-NEXT: sw a3, 32(sp) +; RV32I-NEXT: sw a7, 28(sp) ; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a1, sp, 8 -; RV32I-NEXT: sw a6, 28(sp) +; RV32I-NEXT: sw a6, 24(sp) ; RV32I-NEXT: call __netf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 44(sp) @@ -53,28 +51,26 @@ ; RV32I-NEXT: addi sp, sp, -80 ; RV32I-NEXT: sw ra, 76(sp) ; RV32I-NEXT: lui a0, %hi(x) -; RV32I-NEXT: addi a1, a0, %lo(x) -; RV32I-NEXT: lw a6, 4(a1) -; RV32I-NEXT: lw a7, 8(a1) -; RV32I-NEXT: lw a1, 12(a1) -; RV32I-NEXT: lw a0, %lo(x)(a0) +; RV32I-NEXT: lw a6, %lo(x)(a0) +; RV32I-NEXT: lw a7, %lo(x+4)(a0) +; RV32I-NEXT: lw a2, %lo(x+8)(a0) +; RV32I-NEXT: lw a0, %lo(x+12)(a0) ; RV32I-NEXT: lui a4, %hi(y) -; RV32I-NEXT: addi a5, a4, %lo(y) -; RV32I-NEXT: lw a3, 4(a5) -; RV32I-NEXT: lw a2, 8(a5) -; RV32I-NEXT: lw a5, 12(a5) -; RV32I-NEXT: lw a4, %lo(y)(a4) -; RV32I-NEXT: sw a4, 24(sp) -; RV32I-NEXT: sw a0, 40(sp) -; RV32I-NEXT: sw a5, 36(sp) -; RV32I-NEXT: sw a2, 32(sp) +; RV32I-NEXT: lw a5, %lo(y)(a4) +; RV32I-NEXT: lw a3, %lo(y+4)(a4) +; RV32I-NEXT: lw a1, %lo(y+8)(a4) +; RV32I-NEXT: lw a4, %lo(y+12)(a4) +; RV32I-NEXT: sw a4, 36(sp) +; RV32I-NEXT: sw a1, 32(sp) ; RV32I-NEXT: sw a3, 28(sp) -; RV32I-NEXT: sw a1, 52(sp) -; RV32I-NEXT: sw a7, 48(sp) +; RV32I-NEXT: sw a5, 24(sp) +; RV32I-NEXT: sw a0, 52(sp) +; RV32I-NEXT: sw a2, 48(sp) +; RV32I-NEXT: sw a7, 44(sp) ; RV32I-NEXT: addi a0, sp, 56 ; RV32I-NEXT: addi a1, sp, 40 ; RV32I-NEXT: addi a2, sp, 24 -; RV32I-NEXT: sw a6, 44(sp) +; RV32I-NEXT: sw a6, 40(sp) ; RV32I-NEXT: call __addtf3 ; RV32I-NEXT: lw a1, 56(sp) ; RV32I-NEXT: lw a0, 60(sp) diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll --- a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll @@ -383,16 +383,13 @@ ; CHECK-RV32-NEXT: sw t6, 0(sp) ; CHECK-RV32-NEXT: lui a1, %hi(h) ; CHECK-RV32-NEXT: lw a0, %lo(h)(a1) -; CHECK-RV32-NEXT: addi a1, a1, %lo(h) -; CHECK-RV32-NEXT: lw a1, 4(a1) +; CHECK-RV32-NEXT: lw a1, %lo(h+4)(a1) ; CHECK-RV32-NEXT: lui a3, %hi(i) ; CHECK-RV32-NEXT: lw a2, %lo(i)(a3) -; CHECK-RV32-NEXT: addi a3, a3, %lo(i) -; CHECK-RV32-NEXT: lw a3, 4(a3) +; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3) ; CHECK-RV32-NEXT: call __adddf3 ; CHECK-RV32-NEXT: lui a2, %hi(g) -; CHECK-RV32-NEXT: addi a3, a2, %lo(g) -; CHECK-RV32-NEXT: sw a1, 4(a3) +; CHECK-RV32-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32-NEXT: sw a0, %lo(g)(a2) ; CHECK-RV32-NEXT: lw t6, 0(sp) ; CHECK-RV32-NEXT: lw t5, 4(sp) @@ -466,16 +463,13 @@ ; CHECK-RV32IF-NEXT: fsw fs11, 0(sp) ; CHECK-RV32IF-NEXT: lui a1, %hi(h) ; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1) -; CHECK-RV32IF-NEXT: addi a1, a1, %lo(h) -; CHECK-RV32IF-NEXT: lw a1, 4(a1) +; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1) ; CHECK-RV32IF-NEXT: lui a3, %hi(i) ; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3) -; CHECK-RV32IF-NEXT: addi a3, a3, %lo(i) -; CHECK-RV32IF-NEXT: lw a3, 4(a3) +; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3) ; CHECK-RV32IF-NEXT: call __adddf3 ; CHECK-RV32IF-NEXT: lui a2, %hi(g) -; CHECK-RV32IF-NEXT: addi a3, a2, %lo(g) -; CHECK-RV32IF-NEXT: sw a1, 4(a3) +; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2) ; CHECK-RV32IF-NEXT: flw fs11, 0(sp) ; CHECK-RV32IF-NEXT: flw fs10, 4(sp) @@ -580,16 +574,13 @@ ; CHECK-RV32-NEXT: addi s0, sp, 80 ; CHECK-RV32-NEXT: lui a1, %hi(h) ; CHECK-RV32-NEXT: lw a0, %lo(h)(a1) -; CHECK-RV32-NEXT: addi a1, a1, %lo(h) -; CHECK-RV32-NEXT: lw a1, 4(a1) +; CHECK-RV32-NEXT: lw a1, %lo(h+4)(a1) ; CHECK-RV32-NEXT: lui a3, %hi(i) ; CHECK-RV32-NEXT: lw a2, %lo(i)(a3) -; CHECK-RV32-NEXT: addi a3, a3, %lo(i) -; CHECK-RV32-NEXT: lw a3, 4(a3) +; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3) ; CHECK-RV32-NEXT: call __adddf3 ; CHECK-RV32-NEXT: lui a2, %hi(g) -; CHECK-RV32-NEXT: addi a3, a2, %lo(g) -; CHECK-RV32-NEXT: sw a1, 4(a3) +; CHECK-RV32-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32-NEXT: sw a0, %lo(g)(a2) ; CHECK-RV32-NEXT: lw t6, 12(sp) ; CHECK-RV32-NEXT: lw t5, 16(sp) @@ -666,16 +657,13 @@ ; CHECK-RV32IF-NEXT: addi s0, sp, 208 ; CHECK-RV32IF-NEXT: lui a1, %hi(h) ; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1) -; CHECK-RV32IF-NEXT: addi a1, a1, %lo(h) -; CHECK-RV32IF-NEXT: lw a1, 4(a1) +; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1) ; CHECK-RV32IF-NEXT: lui a3, %hi(i) ; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3) -; CHECK-RV32IF-NEXT: addi a3, a3, %lo(i) -; CHECK-RV32IF-NEXT: lw a3, 4(a3) +; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3) ; CHECK-RV32IF-NEXT: call __adddf3 ; CHECK-RV32IF-NEXT: lui a2, %hi(g) -; CHECK-RV32IF-NEXT: addi a3, a2, %lo(g) -; CHECK-RV32IF-NEXT: sw a1, 4(a3) +; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2) ; CHECK-RV32IF-NEXT: flw fs11, 12(sp) ; CHECK-RV32IF-NEXT: flw fs10, 16(sp) diff --git a/llvm/test/CodeGen/RISCV/wide-mem.ll b/llvm/test/CodeGen/RISCV/wide-mem.ll --- a/llvm/test/CodeGen/RISCV/wide-mem.ll +++ b/llvm/test/CodeGen/RISCV/wide-mem.ll @@ -22,8 +22,7 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, %hi(val64) ; RV32I-NEXT: lw a0, %lo(val64)(a1) -; RV32I-NEXT: addi a1, a1, %lo(val64) -; RV32I-NEXT: lw a1, 4(a1) +; RV32I-NEXT: lw a1, %lo(val64+4)(a1) ; RV32I-NEXT: ret %1 = load i64, i64* @val64 ret i64 %1