diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -223,6 +223,10 @@
       ImmOperand = CurDAG->getTargetGlobalAddress(
           GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(),
           GA->getOffset(), GA->getTargetFlags());
+    } else if (auto CP = dyn_cast<ConstantPoolSDNode>(ImmOperand)) {
+      ImmOperand = CurDAG->getTargetConstantPool(
+          CP->getConstVal(), ImmOperand.getValueType(), CP->getAlignment(),
+          CP->getOffset(), CP->getTargetFlags());
     } else {
       continue;
     }
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
@@ -23,8 +23,7 @@
 ; RV32-ILP32D-NEXT:    addi sp, sp, -16
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI1_0)(a0)
 ; RV32-ILP32D-NEXT:    addi a0, zero, 1
 ; RV32-ILP32D-NEXT:    call callee_double_in_fpr
 ; RV32-ILP32D-NEXT:    lw ra, 12(sp)
@@ -54,8 +53,7 @@
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    addi a1, zero, 5
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI3_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI3_0)(a0)
 ; RV32-ILP32D-NEXT:    addi a0, zero, 1
 ; RV32-ILP32D-NEXT:    addi a2, zero, 2
 ; RV32-ILP32D-NEXT:    addi a4, zero, 3
@@ -99,29 +97,21 @@
 ; RV32-ILP32D-NEXT:    addi sp, sp, -16
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI5_0)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_1)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_1)
-; RV32-ILP32D-NEXT:    fld fa1, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa1, %lo(.LCPI5_1)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_2)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_2)
-; RV32-ILP32D-NEXT:    fld fa2, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa2, %lo(.LCPI5_2)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_3)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_3)
-; RV32-ILP32D-NEXT:    fld fa3, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa3, %lo(.LCPI5_3)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_4)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_4)
-; RV32-ILP32D-NEXT:    fld fa4, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa4, %lo(.LCPI5_4)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_5)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_5)
-; RV32-ILP32D-NEXT:    fld fa5, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa5, %lo(.LCPI5_5)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_6)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_6)
-; RV32-ILP32D-NEXT:    fld fa6, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa6, %lo(.LCPI5_6)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_7)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_7)
-; RV32-ILP32D-NEXT:    fld fa7, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa7, %lo(.LCPI5_7)(a0)
 ; RV32-ILP32D-NEXT:    lui a1, 262688
 ; RV32-ILP32D-NEXT:    mv a0, zero
 ; RV32-ILP32D-NEXT:    call callee_double_in_gpr_exhausted_fprs
@@ -159,29 +149,21 @@
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    lui a1, 262816
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI7_0)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_1)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_1)
-; RV32-ILP32D-NEXT:    fld fa1, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa1, %lo(.LCPI7_1)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_2)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_2)
-; RV32-ILP32D-NEXT:    fld fa2, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa2, %lo(.LCPI7_2)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_3)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_3)
-; RV32-ILP32D-NEXT:    fld fa3, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa3, %lo(.LCPI7_3)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_4)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_4)
-; RV32-ILP32D-NEXT:    fld fa4, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa4, %lo(.LCPI7_4)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_5)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_5)
-; RV32-ILP32D-NEXT:    fld fa5, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa5, %lo(.LCPI7_5)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_6)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_6)
-; RV32-ILP32D-NEXT:    fld fa6, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa6, %lo(.LCPI7_6)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_7)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_7)
-; RV32-ILP32D-NEXT:    fld fa7, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa7, %lo(.LCPI7_7)(a0)
 ; RV32-ILP32D-NEXT:    addi a0, zero, 1
 ; RV32-ILP32D-NEXT:    addi a2, zero, 3
 ; RV32-ILP32D-NEXT:    addi a4, zero, 5
@@ -224,29 +206,21 @@
 ; RV32-ILP32D-NEXT:    lui a0, 262816
 ; RV32-ILP32D-NEXT:    sw a0, 4(sp)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI9_0)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_1)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_1)
-; RV32-ILP32D-NEXT:    fld fa1, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa1, %lo(.LCPI9_1)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_2)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_2)
-; RV32-ILP32D-NEXT:    fld fa2, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa2, %lo(.LCPI9_2)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_3)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_3)
-; RV32-ILP32D-NEXT:    fld fa3, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa3, %lo(.LCPI9_3)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_4)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_4)
-; RV32-ILP32D-NEXT:    fld fa4, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa4, %lo(.LCPI9_4)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_5)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_5)
-; RV32-ILP32D-NEXT:    fld fa5, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa5, %lo(.LCPI9_5)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_6)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_6)
-; RV32-ILP32D-NEXT:    fld fa6, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa6, %lo(.LCPI9_6)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_7)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_7)
-; RV32-ILP32D-NEXT:    fld fa7, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa7, %lo(.LCPI9_7)(a0)
 ; RV32-ILP32D-NEXT:    addi a0, zero, 1
 ; RV32-ILP32D-NEXT:    addi a2, zero, 3
 ; RV32-ILP32D-NEXT:    addi a4, zero, 5
@@ -270,8 +244,7 @@
 ; RV32-ILP32D-LABEL: callee_double_ret:
 ; RV32-ILP32D:       # %bb.0:
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI10_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI10_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI10_0)(a0)
 ; RV32-ILP32D-NEXT:    ret
   ret double 1.0
 }
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
--- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
@@ -26,8 +26,7 @@
 ; RV32-ILP32FD-NEXT:    addi sp, sp, -16
 ; RV32-ILP32FD-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV32-ILP32FD-NEXT:    addi a0, zero, 1
 ; RV32-ILP32FD-NEXT:    call callee_float_in_fpr
 ; RV32-ILP32FD-NEXT:    lw ra, 12(sp)
@@ -57,8 +56,7 @@
 ; RV32-ILP32FD-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    addi a1, zero, 5
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI3_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI3_0)(a0)
 ; RV32-ILP32FD-NEXT:    addi a0, zero, 1
 ; RV32-ILP32FD-NEXT:    addi a2, zero, 2
 ; RV32-ILP32FD-NEXT:    addi a4, zero, 3
@@ -98,29 +96,21 @@
 ; RV32-ILP32FD-NEXT:    addi sp, sp, -16
 ; RV32-ILP32FD-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI5_0)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_1)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_1)
-; RV32-ILP32FD-NEXT:    flw fa1, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa1, %lo(.LCPI5_1)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_2)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_2)
-; RV32-ILP32FD-NEXT:    flw fa2, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa2, %lo(.LCPI5_2)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_3)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_3)
-; RV32-ILP32FD-NEXT:    flw fa3, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa3, %lo(.LCPI5_3)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_4)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_4)
-; RV32-ILP32FD-NEXT:    flw fa4, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa4, %lo(.LCPI5_4)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_5)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_5)
-; RV32-ILP32FD-NEXT:    flw fa5, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa5, %lo(.LCPI5_5)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_6)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_6)
-; RV32-ILP32FD-NEXT:    flw fa6, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa6, %lo(.LCPI5_6)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_7)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_7)
-; RV32-ILP32FD-NEXT:    flw fa7, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa7, %lo(.LCPI5_7)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, 266496
 ; RV32-ILP32FD-NEXT:    call callee_float_in_gpr_exhausted_fprs
 ; RV32-ILP32FD-NEXT:    lw ra, 12(sp)
@@ -153,29 +143,21 @@
 ; RV32-ILP32FD-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    lui a1, 267520
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI7_0)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_1)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_1)
-; RV32-ILP32FD-NEXT:    flw fa1, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa1, %lo(.LCPI7_1)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_2)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_2)
-; RV32-ILP32FD-NEXT:    flw fa2, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa2, %lo(.LCPI7_2)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_3)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_3)
-; RV32-ILP32FD-NEXT:    flw fa3, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa3, %lo(.LCPI7_3)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_4)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_4)
-; RV32-ILP32FD-NEXT:    flw fa4, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa4, %lo(.LCPI7_4)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_5)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_5)
-; RV32-ILP32FD-NEXT:    flw fa5, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa5, %lo(.LCPI7_5)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_6)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_6)
-; RV32-ILP32FD-NEXT:    flw fa6, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa6, %lo(.LCPI7_6)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_7)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_7)
-; RV32-ILP32FD-NEXT:    flw fa7, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa7, %lo(.LCPI7_7)(a0)
 ; RV32-ILP32FD-NEXT:    addi a0, zero, 1
 ; RV32-ILP32FD-NEXT:    addi a2, zero, 3
 ; RV32-ILP32FD-NEXT:    addi a4, zero, 5
@@ -199,8 +181,7 @@
 ; RV32-ILP32FD-LABEL: callee_float_ret:
 ; RV32-ILP32FD:       # %bb.0:
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI8_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI8_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI8_0)(a0)
 ; RV32-ILP32FD-NEXT:    ret
   ret float 1.0
 }
diff --git a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
--- a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
+++ b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll
@@ -132,8 +132,7 @@
 ; RV32I-SMALL-LABEL: lower_constantpool:
 ; RV32I-SMALL:       # %bb.0:
 ; RV32I-SMALL-NEXT:    lui a1, %hi(.LCPI3_0)
-; RV32I-SMALL-NEXT:    addi a1, a1, %lo(.LCPI3_0)
-; RV32I-SMALL-NEXT:    flw ft0, 0(a1)
+; RV32I-SMALL-NEXT:    flw ft0, %lo(.LCPI3_0)(a1)
 ; RV32I-SMALL-NEXT:    fmv.w.x ft1, a0
 ; RV32I-SMALL-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32I-SMALL-NEXT:    fmv.x.w a0, ft0
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -38,8 +38,7 @@
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32IFD-NEXT:    fld ft1, 0(a0)
+; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_0)(a0)
 ; RV32IFD-NEXT:    fadd.d ft0, ft0, ft1
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
@@ -50,8 +49,7 @@
 ; RV64IFD-LABEL: double_imm_op:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV64IFD-NEXT:    addi a1, a1, %lo(.LCPI1_0)
-; RV64IFD-NEXT:    fld ft0, 0(a1)
+; RV64IFD-NEXT:    fld ft0, %lo(.LCPI1_0)(a1)
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -24,14 +24,12 @@
 ; RV32IFD-NEXT:    sw a1, 4(sp)
 ; RV32IFD-NEXT:    fld ft0, 0(sp)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32IFD-NEXT:    fld ft1, 0(a0)
+; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_0)(a0)
 ; RV32IFD-NEXT:    flt.d a0, ft0, ft1
 ; RV32IFD-NEXT:    bnez a0, .LBB1_3
 ; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_1)
-; RV32IFD-NEXT:    fld ft1, 0(a0)
+; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_1)(a0)
 ; RV32IFD-NEXT:    flt.d a0, ft1, ft0
 ; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:    beqz a0, .LBB1_3
diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll
--- a/llvm/test/CodeGen/RISCV/float-imm.ll
+++ b/llvm/test/CodeGen/RISCV/float-imm.ll
@@ -15,20 +15,17 @@
 ; RV64IF-LABEL: float_imm:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV64IF-NEXT:    addi a0, a0, %lo(.LCPI0_0)
-; RV64IF-NEXT:    flw ft0, 0(a0)
+; RV64IF-NEXT:    flw ft0, %lo(.LCPI0_0)(a0)
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   ret float 3.14159274101257324218750
 }
 
 define float @float_imm_op(float %a) nounwind {
-; TODO: addi should be folded in to the flw
 ; RV32IF-LABEL: float_imm_op:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV32IF-NEXT:    addi a1, a1, %lo(.LCPI1_0)
-; RV32IF-NEXT:    flw ft0, 0(a1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a1)
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
@@ -37,8 +34,7 @@
 ; RV64IF-LABEL: float_imm_op:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV64IF-NEXT:    addi a1, a1, %lo(.LCPI1_0)
-; RV64IF-NEXT:    flw ft0, 0(a1)
+; RV64IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a1)
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
diff --git a/llvm/test/CodeGen/RISCV/fp-imm.ll b/llvm/test/CodeGen/RISCV/fp-imm.ll
--- a/llvm/test/CodeGen/RISCV/fp-imm.ll
+++ b/llvm/test/CodeGen/RISCV/fp-imm.ll
@@ -35,29 +35,25 @@
 ; RV32F-LABEL: f32_negative_zero:
 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32F-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32F-NEXT:    flw fa0, 0(a0)
+; RV32F-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV32F-NEXT:    ret
 ;
 ; RV32D-LABEL: f32_negative_zero:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32D-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32D-NEXT:    flw fa0, 0(a0)
+; RV32D-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV32D-NEXT:    ret
 ;
 ; RV64F-LABEL: f32_negative_zero:
 ; RV64F:       # %bb.0:
 ; RV64F-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64F-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV64F-NEXT:    flw fa0, 0(a0)
+; RV64F-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV64F-NEXT:    ret
 ;
 ; RV64D-LABEL: f32_negative_zero:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64D-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV64D-NEXT:    flw fa0, 0(a0)
+; RV64D-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV64D-NEXT:    ret
   ret float -0.0
 }
@@ -96,8 +92,7 @@
 ; RV32D-LABEL: f64_negative_zero:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32D-NEXT:    addi a0, a0, %lo(.LCPI3_0)
-; RV32D-NEXT:    fld fa0, 0(a0)
+; RV32D-NEXT:    fld fa0, %lo(.LCPI3_0)(a0)
 ; RV32D-NEXT:    ret
 ;
 ; RV64F-LABEL: f64_negative_zero:
@@ -109,8 +104,7 @@
 ; RV64D-LABEL: f64_negative_zero:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV64D-NEXT:    addi a0, a0, %lo(.LCPI3_0)
-; RV64D-NEXT:    fld fa0, 0(a0)
+; RV64D-NEXT:    fld fa0, %lo(.LCPI3_0)(a0)
 ; RV64D-NEXT:    ret
   ret double -0.0
 }
diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll
--- a/llvm/test/CodeGen/RISCV/select-const.ll
+++ b/llvm/test/CodeGen/RISCV/select-const.ll
@@ -148,13 +148,12 @@
 ; RV32IF-NEXT:    bnez a0, .LBB4_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI4_0)
-; RV32IF-NEXT:    addi a0, a0, %lo(.LCPI4_0)
-; RV32IF-NEXT:    j .LBB4_3
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB4_2:
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI4_1)
-; RV32IF-NEXT:    addi a0, a0, %lo(.LCPI4_1)
-; RV32IF-NEXT:  .LBB4_3:
-; RV32IF-NEXT:    flw ft0, 0(a0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI4_1)(a0)
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
@@ -173,13 +172,12 @@
 ; RV64IFD-NEXT:    bnez a0, .LBB4_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    lui a0, %hi(.LCPI4_0)
-; RV64IFD-NEXT:    addi a0, a0, %lo(.LCPI4_0)
-; RV64IFD-NEXT:    j .LBB4_3
+; RV64IFD-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
+; RV64IFD-NEXT:    fmv.x.w a0, ft0
+; RV64IFD-NEXT:    ret
 ; RV64IFD-NEXT:  .LBB4_2:
 ; RV64IFD-NEXT:    lui a0, %hi(.LCPI4_1)
-; RV64IFD-NEXT:    addi a0, a0, %lo(.LCPI4_1)
-; RV64IFD-NEXT:  .LBB4_3:
-; RV64IFD-NEXT:    flw ft0, 0(a0)
+; RV64IFD-NEXT:    flw ft0, %lo(.LCPI4_1)(a0)
 ; RV64IFD-NEXT:    fmv.x.w a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = select i1 %a, float 3.0, float 4.0