Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -140,6 +140,13 @@
                            AssemblerPredicate<(all_of FeatureStdExtB),
                            "'B' (Bit Manipulation Instructions)">;
 
+def FeatureCLIC
+    : SubtargetFeature<"experimental-clic", "HasCLIC", "true",
+                       "Enable CLIC interrupt mode CSRs">;
+def HasCLIC : Predicate<"Subtarget->hasCLIC()">,
+                            AssemblerPredicate<(all_of FeatureCLIC),
+                            "CLIC interrupt mode CSRs">;
+
 def FeatureRVCHints
     : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
                        "Enable RVC Hint Instructions.">;
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,6 +50,7 @@
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
+  bool HasCLIC = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
@@ -110,6 +111,7 @@
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
+  bool hasCLIC() const { return HasCLIC; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVSystemOperands.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -51,6 +51,11 @@
 // 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
 // Volume II: Privileged Architecture.
 
+// CLIC mode CSRs encodings match those documented in Section 4 
+// in the RISC-V Core-Local Interrupt Controller (CLIC)
+// proposal for fast interrupt.
+
+
 //===--------------------------
 // User Trap Setup
 //===--------------------------
@@ -58,6 +63,10 @@
 def : SysReg<"uie", 0x004>;
 def : SysReg<"utvec", 0x005>;
 
+let FeaturesRequired = [{ {RISCV::FeatureCLIC} }] in {
+def : SysReg<"utvt", 0x007>;
+}
+
 //===--------------------------
 // User Trap Handling
 //===--------------------------
@@ -67,6 +76,14 @@
 def : SysReg<"utval", 0x043>;
 def : SysReg<"uip", 0x044>;
 
+let FeaturesRequired = [{ {RISCV::FeatureCLIC} }] in {
+def : SysReg<"unxti", 0x045>;
+def : SysReg<"uintstatus", 0x046>;
+def : SysReg<"uscratchcsw", 0x048>;
+def : SysReg<"uscratchcswl", 0x049>;
+// FIXME: uintstatus and uintthresh encoding not allocated yet.
+}
+
 //===--------------------------
 // User Floating-Point CSRs
 //===--------------------------
@@ -158,6 +175,10 @@
 def : SysReg<"stvec", 0x105>;
 def : SysReg<"scounteren", 0x106>;
 
+let FeaturesRequired = [{ {RISCV::FeatureCLIC} }] in {
+def : SysReg<"stvt", 0x107>;
+}
+
 //===--------------------------
 // Supervisor Trap Handling
 //===--------------------------
@@ -167,6 +188,14 @@
 def : SysReg<"stval", 0x143>;
 def : SysReg<"sip", 0x144>;
 
+let FeaturesRequired = [{ {RISCV::FeatureCLIC} }] in {
+def : SysReg<"snxti", 0x145>;
+def : SysReg<"sintstatus", 0x146>;
+def : SysReg<"sscratchcsw", 0x148>;
+def : SysReg<"sscratchcswl", 0x149>;
+// FIXME: sintstatus and sintthresh encoding not allocated yet.
+}
+
 //===-------------------------------------
 // Supervisor Protection and Translation
 //===-------------------------------------
@@ -192,6 +221,10 @@
 def : SysReg<"mtvec", 0x305>;
 def : SysReg<"mcounteren", 0x306>;
 
+let FeaturesRequired = [{ {RISCV::FeatureCLIC} }] in {
+def : SysReg<"mtvt", 0x307>;
+}
+
 //===-----------------------------
 // Machine Trap Handling
 //===-----------------------------
@@ -201,6 +234,14 @@
 def : SysReg<"mtval", 0x343>;
 def : SysReg<"mip", 0x344>;
 
+let FeaturesRequired = [{ {RISCV::FeatureCLIC} }] in {
+def : SysReg<"mnxti", 0x345>;
+def : SysReg<"mintstatus", 0x346>;
+def : SysReg<"mscratchcsw", 0x348>;
+def : SysReg<"mscratchcswl", 0x349>;
+// FIXME: mintstatus, mintthresh, mclicbase encoding not allocated yet.
+}
+
 //===----------------------------------
 // Machine Protection and Translation
 //===----------------------------------
Index: llvm/test/MC/RISCV/clic-csr-names-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/clic-csr-names-invalid.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-clic < %s 2>&1 \
+# RUN:  | FileCheck -check-prefixes=CHECK-NEED-CLIC %s
+# RUN: not llvm-mc -triple riscv64 -mattr=-experimental-clic < %s 2>&1 \
+# RUN:  | FileCheck -check-prefixes=CHECK-NEED-CLIC %s
+
+# These user mode CSR register names are CLIC mode only.
+
+csrr t1, mtvt # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, mnxti # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, mintstatus # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled 
+csrr t1, mscratchcsw # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, mscratchcswl # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled       
+csrr t1, utvt # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, unxti # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, uintstatus # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled    
+csrr t1, uscratchcsw # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, uscratchcswl # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled      
+csrr t1, stvt # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, snxti # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, sintstatus # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled 
+csrr t1, sscratchcsw # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled
+csrr t1, sscratchcswl # CHECK-NEED-CLIC: :[[@LINE]]:10: error: system register use requires an option to be enabled       
+
Index: llvm/test/MC/RISCV/clic-machine-csr-names.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/clic-machine-csr-names.s
@@ -0,0 +1,87 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-clic -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST-CLIC,CHECK-ENC-CLIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-clic < %s \
+# RUN:     | llvm-objdump -d  --mattr=+experimental-clic - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-CLIC %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-clic -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST-CLIC,CHECK-ENC-CLIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-clic < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-clic - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-CLIC %s
+
+##################################
+# CLIC Mode Machine Trap Setup
+##################################
+
+# mtvt
+# name
+# CHECK-INST-CLIC: csrrs t1, mtvt, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x70,0x30]
+# CHECK-INST-ALIAS-CLIC: csrr t1, mtvt
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, mtvt, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x70,0x30]
+# CHECK-INST-ALIAS-CLIC: csrr t2, mtvt
+# name
+csrrs t1, mtvt, zero
+# uimm12
+csrrs t2, 0x307, zero
+
+# mnxti
+# name
+# CHECK-INST-CLIC: csrrs t1, mnxti, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x50,0x34]
+# CHECK-INST-ALIAS-CLIC: csrr t1, mnxti
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, mnxti, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x50,0x34]
+# CHECK-INST-ALIAS-CLIC: csrr t2, mnxti
+# name
+csrrs t1, mnxti, zero
+# uimm12
+csrrs t2, 0x345, zero
+
+# mintstatus
+# name
+# CHECK-INST-CLIC: csrrs t1, mintstatus, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x60,0x34]
+# CHECK-INST-ALIAS-CLIC: csrr t1, mintstatus
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, mintstatus, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x60,0x34]
+# CHECK-INST-ALIAS-CLIC: csrr t2, mintstatus
+# name
+csrrs t1, mintstatus, zero
+# uimm12
+csrrs t2, 0x346, zero
+
+# mscratchcsw
+# name
+# CHECK-INST-CLIC: csrrs t1, mscratchcsw, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x80,0x34]
+# CHECK-INST-ALIAS-CLIC: csrr t1, mscratchcsw
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, mscratchcsw, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x80,0x34]
+# CHECK-INST-ALIAS-CLIC: csrr t2, mscratchcsw
+# name
+csrrs t1, mscratchcsw, zero
+# uimm12
+csrrs t2, 0x348, zero
+
+# mscratchcswl
+# name
+# CHECK-INST-CLIC: csrrs t1, mscratchcswl, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x90,0x34]
+# CHECK-INST-ALIAS-CLIC: csrr t1, mscratchcswl
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, mscratchcswl, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x90,0x34]
+# CHECK-INST-ALIAS-CLIC: csrr t2, mscratchcswl
+# name
+csrrs t1, mscratchcswl, zero
+# uimm12
+csrrs t2, 0x349, zero
+
+
Index: llvm/test/MC/RISCV/clic-supervisor-csr-names.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/clic-supervisor-csr-names.s
@@ -0,0 +1,86 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-clic -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST-CLIC,CHECK-ENC-CLIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-clic < %s \
+# RUN:     | llvm-objdump -d  --mattr=+experimental-clic - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-CLIC %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-clic -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST-CLIC,CHECK-ENC-CLIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-clic < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-clic - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-CLIC %s
+
+##################################
+# CLIC Mode Supervisor Trap Setup
+##################################
+
+# stvt
+# name
+# CHECK-INST-CLIC: csrrs t1, stvt, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x70,0x10]
+# CHECK-INST-ALIAS-CLIC: csrr t1, stvt
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, stvt, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x70,0x10]
+# CHECK-INST-ALIAS-CLIC: csrr t2, stvt
+# name
+csrrs t1, stvt, zero
+# uimm12
+csrrs t2, 0x107, zero
+
+# snxti
+# name
+# CHECK-INST-CLIC: csrrs t1, snxti, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x50,0x14]
+# CHECK-INST-ALIAS-CLIC: csrr t1, snxti
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, snxti, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x50,0x14]
+# CHECK-INST-ALIAS-CLIC: csrr t2, snxti
+# name
+csrrs t1, snxti, zero
+# uimm12
+csrrs t2, 0x145, zero
+
+# uintstatus
+# name
+# CHECK-INST-CLIC: csrrs t1, sintstatus, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x60,0x14]
+# CHECK-INST-ALIAS-CLIC: csrr t1, sintstatus
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, sintstatus, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x60,0x14]
+# CHECK-INST-ALIAS-CLIC: csrr t2, sintstatus
+# name
+csrrs t1, sintstatus, zero
+# uimm12
+csrrs t2, 0x146, zero
+
+# sscratchcsw
+# name
+# CHECK-INST-CLIC: csrrs t1, sscratchcsw, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x80,0x14]
+# CHECK-INST-ALIAS-CLIC: csrr t1, sscratchcsw
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, sscratchcsw, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x80,0x14]
+# CHECK-INST-ALIAS-CLIC: csrr t2, sscratchcsw
+# name
+csrrs t1, sscratchcsw, zero
+# uimm12
+csrrs t2, 0x148, zero
+
+# sscratchcswl
+# name
+# CHECK-INST-CLIC: csrrs t1, sscratchcswl, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x90,0x14]
+# CHECK-INST-ALIAS-CLIC: csrr t1, sscratchcswl
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, sscratchcswl, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x90,0x14]
+# CHECK-INST-ALIAS-CLIC: csrr t2, sscratchcswl
+# name
+csrrs t1, sscratchcswl, zero
+# uimm12
+csrrs t2, 0x149, zero
+
Index: llvm/test/MC/RISCV/clic-user-csr-names.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/clic-user-csr-names.s
@@ -0,0 +1,86 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-clic -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST-CLIC,CHECK-ENC-CLIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-clic < %s \
+# RUN:     | llvm-objdump -d  --mattr=+experimental-clic - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-CLIC %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-clic -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST-CLIC,CHECK-ENC-CLIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-clic < %s \
+# RUN:     | llvm-objdump -d --mattr=+experimental-clic - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS-CLIC %s
+
+##################################
+# CLIC Mode User Trap Setup
+##################################
+
+# utvt
+# name
+# CHECK-INST-CLIC: csrrs t1, utvt, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x70,0x00]
+# CHECK-INST-ALIAS-CLIC: csrr t1, utvt
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, utvt, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x70,0x00]
+# CHECK-INST-ALIAS-CLIC: csrr t2, utvt
+# name
+csrrs t1, utvt, zero
+# uimm12
+csrrs t2, 0x007, zero
+
+# unxti
+# name
+# CHECK-INST-CLIC: csrrs t1, unxti, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x50,0x04]
+# CHECK-INST-ALIAS-CLIC: csrr t1, unxti
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, unxti, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x50,0x04]
+# CHECK-INST-ALIAS-CLIC: csrr t2, unxti
+# name
+csrrs t1, unxti, zero
+# uimm12
+csrrs t2, 0x045, zero
+
+# uintstatus
+# name
+# CHECK-INST-CLIC: csrrs t1, uintstatus, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x60,0x04]
+# CHECK-INST-ALIAS-CLIC: csrr t1, uintstatus
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, uintstatus, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x60,0x04]
+# CHECK-INST-ALIAS-CLIC: csrr t2, uintstatus
+# name
+csrrs t1, uintstatus, zero
+# uimm12
+csrrs t2, 0x046, zero
+
+# uscratchcsw
+# name
+# CHECK-INST-CLIC: csrrs t1, uscratchcsw, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x80,0x04]
+# CHECK-INST-ALIAS-CLIC: csrr t1, uscratchcsw
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, uscratchcsw, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x80,0x04]
+# CHECK-INST-ALIAS-CLIC: csrr t2, uscratchcsw
+# name
+csrrs t1, uscratchcsw, zero
+# uimm12
+csrrs t2, 0x048, zero
+
+# uscratchcswl
+# name
+# CHECK-INST-CLIC: csrrs t1, uscratchcswl, zero
+# CHECK-ENC-CLIC: encoding: [0x73,0x23,0x90,0x04]
+# CHECK-INST-ALIAS-CLIC: csrr t1, uscratchcswl
+# uimm12
+# CHECK-INST-CLIC: csrrs t2, uscratchcswl, zero
+# CHECK-ENC-CLIC: encoding: [0xf3,0x23,0x90,0x04]
+# CHECK-INST-ALIAS-CLIC: csrr t2, uscratchcswl
+# name
+csrrs t1, uscratchcswl, zero
+# uimm12
+csrrs t2, 0x049, zero
+